| module user_project_wrapper (user_clock2, |
| wb_clk_i, |
| wb_rst_i, |
| wbs_ack_o, |
| wbs_cyc_i, |
| wbs_stb_i, |
| wbs_we_i, |
| vssa2, |
| vdda2, |
| vssa1, |
| vdda1, |
| vssd2, |
| vccd2, |
| vssd1, |
| vccd1, |
| analog_io, |
| io_in, |
| io_oeb, |
| io_out, |
| la_data_in, |
| la_data_out, |
| la_oenb, |
| user_irq, |
| wbs_adr_i, |
| wbs_dat_i, |
| wbs_dat_o, |
| wbs_sel_i); |
| input user_clock2; |
| input wb_clk_i; |
| input wb_rst_i; |
| output wbs_ack_o; |
| input wbs_cyc_i; |
| input wbs_stb_i; |
| input wbs_we_i; |
| input vssa2; |
| input vdda2; |
| input vssa1; |
| input vdda1; |
| input vssd2; |
| input vccd2; |
| input vssd1; |
| input vccd1; |
| inout [28:0] analog_io; |
| input [37:0] io_in; |
| output [37:0] io_oeb; |
| output [37:0] io_out; |
| input [127:0] la_data_in; |
| output [127:0] la_data_out; |
| input [127:0] la_oenb; |
| output [2:0] user_irq; |
| input [31:0] wbs_adr_i; |
| input [31:0] wbs_dat_i; |
| output [31:0] wbs_dat_o; |
| input [3:0] wbs_sel_i; |
| |
| wire \buf_out_north[0] ; |
| wire \buf_out_north[10] ; |
| wire \buf_out_north[11] ; |
| wire \buf_out_north[12] ; |
| wire \buf_out_north[13] ; |
| wire \buf_out_north[14] ; |
| wire \buf_out_north[15] ; |
| wire \buf_out_north[16] ; |
| wire \buf_out_north[17] ; |
| wire \buf_out_north[18] ; |
| wire \buf_out_north[19] ; |
| wire \buf_out_north[1] ; |
| wire \buf_out_north[20] ; |
| wire \buf_out_north[21] ; |
| wire \buf_out_north[22] ; |
| wire \buf_out_north[23] ; |
| wire \buf_out_north[24] ; |
| wire \buf_out_north[25] ; |
| wire \buf_out_north[26] ; |
| wire \buf_out_north[27] ; |
| wire \buf_out_north[28] ; |
| wire \buf_out_north[29] ; |
| wire \buf_out_north[2] ; |
| wire \buf_out_north[30] ; |
| wire \buf_out_north[31] ; |
| wire \buf_out_north[32] ; |
| wire \buf_out_north[33] ; |
| wire \buf_out_north[34] ; |
| wire \buf_out_north[35] ; |
| wire \buf_out_north[36] ; |
| wire \buf_out_north[37] ; |
| wire \buf_out_north[38] ; |
| wire \buf_out_north[39] ; |
| wire \buf_out_north[3] ; |
| wire \buf_out_north[40] ; |
| wire \buf_out_north[41] ; |
| wire \buf_out_north[4] ; |
| wire \buf_out_north[5] ; |
| wire \buf_out_north[6] ; |
| wire \buf_out_north[7] ; |
| wire \buf_out_north[8] ; |
| wire \buf_out_north[9] ; |
| wire \cfg_ccska_aes_rp[0] ; |
| wire \cfg_ccska_aes_rp[1] ; |
| wire \cfg_ccska_aes_rp[2] ; |
| wire \cfg_ccska_aes_rp[3] ; |
| wire \cfg_ccska_fpu_rp[0] ; |
| wire \cfg_ccska_fpu_rp[1] ; |
| wire \cfg_ccska_fpu_rp[2] ; |
| wire \cfg_ccska_fpu_rp[3] ; |
| wire \cfg_ccska_riscv_core2_rp[0] ; |
| wire \cfg_ccska_riscv_core2_rp[1] ; |
| wire \cfg_ccska_riscv_core2_rp[2] ; |
| wire \cfg_ccska_riscv_core2_rp[3] ; |
| wire \cfg_ccska_riscv_core3_rp[0] ; |
| wire \cfg_ccska_riscv_core3_rp[1] ; |
| wire \cfg_ccska_riscv_core3_rp[2] ; |
| wire \cfg_ccska_riscv_core3_rp[3] ; |
| wire \cfg_clk_skew_ctrl1[0] ; |
| wire \cfg_clk_skew_ctrl1[10] ; |
| wire \cfg_clk_skew_ctrl1[11] ; |
| wire \cfg_clk_skew_ctrl1[12] ; |
| wire \cfg_clk_skew_ctrl1[13] ; |
| wire \cfg_clk_skew_ctrl1[14] ; |
| wire \cfg_clk_skew_ctrl1[15] ; |
| wire \cfg_clk_skew_ctrl1[16] ; |
| wire \cfg_clk_skew_ctrl1[17] ; |
| wire \cfg_clk_skew_ctrl1[18] ; |
| wire \cfg_clk_skew_ctrl1[19] ; |
| wire \cfg_clk_skew_ctrl1[1] ; |
| wire \cfg_clk_skew_ctrl1[20] ; |
| wire \cfg_clk_skew_ctrl1[21] ; |
| wire \cfg_clk_skew_ctrl1[22] ; |
| wire \cfg_clk_skew_ctrl1[23] ; |
| wire \cfg_clk_skew_ctrl1[24] ; |
| wire \cfg_clk_skew_ctrl1[25] ; |
| wire \cfg_clk_skew_ctrl1[26] ; |
| wire \cfg_clk_skew_ctrl1[27] ; |
| wire \cfg_clk_skew_ctrl1[28] ; |
| wire \cfg_clk_skew_ctrl1[29] ; |
| wire \cfg_clk_skew_ctrl1[2] ; |
| wire \cfg_clk_skew_ctrl1[30] ; |
| wire \cfg_clk_skew_ctrl1[31] ; |
| wire \cfg_clk_skew_ctrl1[3] ; |
| wire \cfg_clk_skew_ctrl1[4] ; |
| wire \cfg_clk_skew_ctrl1[5] ; |
| wire \cfg_clk_skew_ctrl1[6] ; |
| wire \cfg_clk_skew_ctrl1[7] ; |
| wire \cfg_clk_skew_ctrl1[8] ; |
| wire \cfg_clk_skew_ctrl1[9] ; |
| wire \cfg_clk_skew_ctrl2[0] ; |
| wire \cfg_clk_skew_ctrl2[10] ; |
| wire \cfg_clk_skew_ctrl2[11] ; |
| wire \cfg_clk_skew_ctrl2[12] ; |
| wire \cfg_clk_skew_ctrl2[13] ; |
| wire \cfg_clk_skew_ctrl2[14] ; |
| wire \cfg_clk_skew_ctrl2[15] ; |
| wire \cfg_clk_skew_ctrl2[16] ; |
| wire \cfg_clk_skew_ctrl2[17] ; |
| wire \cfg_clk_skew_ctrl2[18] ; |
| wire \cfg_clk_skew_ctrl2[19] ; |
| wire \cfg_clk_skew_ctrl2[1] ; |
| wire \cfg_clk_skew_ctrl2[20] ; |
| wire \cfg_clk_skew_ctrl2[21] ; |
| wire \cfg_clk_skew_ctrl2[22] ; |
| wire \cfg_clk_skew_ctrl2[23] ; |
| wire \cfg_clk_skew_ctrl2[24] ; |
| wire \cfg_clk_skew_ctrl2[25] ; |
| wire \cfg_clk_skew_ctrl2[26] ; |
| wire \cfg_clk_skew_ctrl2[27] ; |
| wire \cfg_clk_skew_ctrl2[28] ; |
| wire \cfg_clk_skew_ctrl2[29] ; |
| wire \cfg_clk_skew_ctrl2[2] ; |
| wire \cfg_clk_skew_ctrl2[30] ; |
| wire \cfg_clk_skew_ctrl2[31] ; |
| wire \cfg_clk_skew_ctrl2[3] ; |
| wire \cfg_clk_skew_ctrl2[4] ; |
| wire \cfg_clk_skew_ctrl2[5] ; |
| wire \cfg_clk_skew_ctrl2[6] ; |
| wire \cfg_clk_skew_ctrl2[7] ; |
| wire \cfg_clk_skew_ctrl2[8] ; |
| wire \cfg_clk_skew_ctrl2[9] ; |
| wire \cfg_dac0_mux_sel[0] ; |
| wire \cfg_dac0_mux_sel[1] ; |
| wire \cfg_dac0_mux_sel[2] ; |
| wire \cfg_dac0_mux_sel[3] ; |
| wire \cfg_dac0_mux_sel[4] ; |
| wire \cfg_dac0_mux_sel[5] ; |
| wire \cfg_dac0_mux_sel[6] ; |
| wire \cfg_dac0_mux_sel[7] ; |
| wire \cfg_dac1_mux_sel[0] ; |
| wire \cfg_dac1_mux_sel[1] ; |
| wire \cfg_dac1_mux_sel[2] ; |
| wire \cfg_dac1_mux_sel[3] ; |
| wire \cfg_dac1_mux_sel[4] ; |
| wire \cfg_dac1_mux_sel[5] ; |
| wire \cfg_dac1_mux_sel[6] ; |
| wire \cfg_dac1_mux_sel[7] ; |
| wire \cfg_dac2_mux_sel[0] ; |
| wire \cfg_dac2_mux_sel[1] ; |
| wire \cfg_dac2_mux_sel[2] ; |
| wire \cfg_dac2_mux_sel[3] ; |
| wire \cfg_dac2_mux_sel[4] ; |
| wire \cfg_dac2_mux_sel[5] ; |
| wire \cfg_dac2_mux_sel[6] ; |
| wire \cfg_dac2_mux_sel[7] ; |
| wire \cfg_dac3_mux_sel[0] ; |
| wire \cfg_dac3_mux_sel[1] ; |
| wire \cfg_dac3_mux_sel[2] ; |
| wire \cfg_dac3_mux_sel[3] ; |
| wire \cfg_dac3_mux_sel[4] ; |
| wire \cfg_dac3_mux_sel[5] ; |
| wire \cfg_dac3_mux_sel[6] ; |
| wire \cfg_dac3_mux_sel[7] ; |
| wire \cfg_dc_trim[0] ; |
| wire \cfg_dc_trim[10] ; |
| wire \cfg_dc_trim[11] ; |
| wire \cfg_dc_trim[12] ; |
| wire \cfg_dc_trim[13] ; |
| wire \cfg_dc_trim[14] ; |
| wire \cfg_dc_trim[15] ; |
| wire \cfg_dc_trim[16] ; |
| wire \cfg_dc_trim[17] ; |
| wire \cfg_dc_trim[18] ; |
| wire \cfg_dc_trim[19] ; |
| wire \cfg_dc_trim[1] ; |
| wire \cfg_dc_trim[20] ; |
| wire \cfg_dc_trim[21] ; |
| wire \cfg_dc_trim[22] ; |
| wire \cfg_dc_trim[23] ; |
| wire \cfg_dc_trim[24] ; |
| wire \cfg_dc_trim[25] ; |
| wire \cfg_dc_trim[2] ; |
| wire \cfg_dc_trim[3] ; |
| wire \cfg_dc_trim[4] ; |
| wire \cfg_dc_trim[5] ; |
| wire \cfg_dc_trim[6] ; |
| wire \cfg_dc_trim[7] ; |
| wire \cfg_dc_trim[8] ; |
| wire \cfg_dc_trim[9] ; |
| wire cfg_dco_mode; |
| wire cfg_pll_enb; |
| wire \cfg_pll_fed_div[0] ; |
| wire \cfg_pll_fed_div[1] ; |
| wire \cfg_pll_fed_div[2] ; |
| wire \cfg_pll_fed_div[3] ; |
| wire \cfg_pll_fed_div[4] ; |
| wire \cfg_riscv_ctrl[0] ; |
| wire \cfg_riscv_ctrl[10] ; |
| wire \cfg_riscv_ctrl[11] ; |
| wire \cfg_riscv_ctrl[12] ; |
| wire \cfg_riscv_ctrl[13] ; |
| wire \cfg_riscv_ctrl[14] ; |
| wire \cfg_riscv_ctrl[15] ; |
| wire \cfg_riscv_ctrl[1] ; |
| wire \cfg_riscv_ctrl[2] ; |
| wire \cfg_riscv_ctrl[3] ; |
| wire \cfg_riscv_ctrl[4] ; |
| wire \cfg_riscv_ctrl[5] ; |
| wire \cfg_riscv_ctrl[6] ; |
| wire \cfg_riscv_ctrl[7] ; |
| wire \cfg_riscv_ctrl[8] ; |
| wire \cfg_riscv_ctrl[9] ; |
| wire cfg_strap_pad_ctrl; |
| wire cfg_strap_pad_ctrl_rp; |
| wire \cfg_wcska_peri_rp[0] ; |
| wire \cfg_wcska_peri_rp[1] ; |
| wire \cfg_wcska_peri_rp[2] ; |
| wire \cfg_wcska_peri_rp[3] ; |
| wire \cfg_wcska_pinmux_rp[0] ; |
| wire \cfg_wcska_pinmux_rp[1] ; |
| wire \cfg_wcska_pinmux_rp[2] ; |
| wire \cfg_wcska_pinmux_rp[3] ; |
| wire \cfg_wcska_qspi_co_rp[0] ; |
| wire \cfg_wcska_qspi_co_rp[1] ; |
| wire \cfg_wcska_qspi_co_rp[2] ; |
| wire \cfg_wcska_qspi_co_rp[3] ; |
| wire \cfg_wcska_qspi_rp[0] ; |
| wire \cfg_wcska_qspi_rp[1] ; |
| wire \cfg_wcska_qspi_rp[2] ; |
| wire \cfg_wcska_qspi_rp[3] ; |
| wire \cfg_wcska_uart_rp[0] ; |
| wire \cfg_wcska_uart_rp[1] ; |
| wire \cfg_wcska_uart_rp[2] ; |
| wire \cfg_wcska_uart_rp[3] ; |
| wire \ch_out_east[11] ; |
| wire \ch_out_east[14] ; |
| wire \ch_out_east[17] ; |
| wire \ch_out_east[20] ; |
| wire \ch_out_east[23] ; |
| wire \ch_out_east[26] ; |
| wire \ch_out_east[29] ; |
| wire \ch_out_east[2] ; |
| wire \ch_out_east[32] ; |
| wire \ch_out_east[35] ; |
| wire \ch_out_east[38] ; |
| wire \ch_out_east[41] ; |
| wire \ch_out_east[44] ; |
| wire \ch_out_east[5] ; |
| wire \ch_out_east[8] ; |
| wire \ch_out_north[11] ; |
| wire \ch_out_north[14] ; |
| wire \ch_out_north[17] ; |
| wire \ch_out_north[20] ; |
| wire \ch_out_north[23] ; |
| wire \ch_out_north[26] ; |
| wire \ch_out_north[2] ; |
| wire \ch_out_north[5] ; |
| wire \ch_out_north[8] ; |
| wire \ch_out_south[0] ; |
| wire \ch_out_south[100] ; |
| wire \ch_out_south[101] ; |
| wire \ch_out_south[103] ; |
| wire \ch_out_south[104] ; |
| wire \ch_out_south[106] ; |
| wire \ch_out_south[108] ; |
| wire \ch_out_south[10] ; |
| wire \ch_out_south[110] ; |
| wire \ch_out_south[112] ; |
| wire \ch_out_south[114] ; |
| wire \ch_out_south[116] ; |
| wire \ch_out_south[118] ; |
| wire \ch_out_south[11] ; |
| wire \ch_out_south[120] ; |
| wire \ch_out_south[122] ; |
| wire \ch_out_south[124] ; |
| wire \ch_out_south[126] ; |
| wire \ch_out_south[128] ; |
| wire \ch_out_south[130] ; |
| wire \ch_out_south[132] ; |
| wire \ch_out_south[134] ; |
| wire \ch_out_south[136] ; |
| wire \ch_out_south[138] ; |
| wire \ch_out_south[13] ; |
| wire \ch_out_south[140] ; |
| wire \ch_out_south[14] ; |
| wire \ch_out_south[15] ; |
| wire \ch_out_south[17] ; |
| wire \ch_out_south[18] ; |
| wire \ch_out_south[19] ; |
| wire \ch_out_south[1] ; |
| wire \ch_out_south[21] ; |
| wire \ch_out_south[22] ; |
| wire \ch_out_south[23] ; |
| wire \ch_out_south[252] ; |
| wire \ch_out_south[25] ; |
| wire \ch_out_south[26] ; |
| wire \ch_out_south[28] ; |
| wire \ch_out_south[29] ; |
| wire \ch_out_south[31] ; |
| wire \ch_out_south[32] ; |
| wire \ch_out_south[34] ; |
| wire \ch_out_south[35] ; |
| wire \ch_out_south[37] ; |
| wire \ch_out_south[38] ; |
| wire \ch_out_south[3] ; |
| wire \ch_out_south[40] ; |
| wire \ch_out_south[41] ; |
| wire \ch_out_south[43] ; |
| wire \ch_out_south[44] ; |
| wire \ch_out_south[46] ; |
| wire \ch_out_south[47] ; |
| wire \ch_out_south[49] ; |
| wire \ch_out_south[4] ; |
| wire \ch_out_south[50] ; |
| wire \ch_out_south[52] ; |
| wire \ch_out_south[53] ; |
| wire \ch_out_south[55] ; |
| wire \ch_out_south[56] ; |
| wire \ch_out_south[58] ; |
| wire \ch_out_south[59] ; |
| wire \ch_out_south[5] ; |
| wire \ch_out_south[61] ; |
| wire \ch_out_south[62] ; |
| wire \ch_out_south[64] ; |
| wire \ch_out_south[65] ; |
| wire \ch_out_south[67] ; |
| wire \ch_out_south[68] ; |
| wire \ch_out_south[6] ; |
| wire \ch_out_south[70] ; |
| wire \ch_out_south[71] ; |
| wire \ch_out_south[73] ; |
| wire \ch_out_south[74] ; |
| wire \ch_out_south[76] ; |
| wire \ch_out_south[77] ; |
| wire \ch_out_south[79] ; |
| wire \ch_out_south[7] ; |
| wire \ch_out_south[80] ; |
| wire \ch_out_south[82] ; |
| wire \ch_out_south[83] ; |
| wire \ch_out_south[85] ; |
| wire \ch_out_south[86] ; |
| wire \ch_out_south[88] ; |
| wire \ch_out_south[89] ; |
| wire \ch_out_south[91] ; |
| wire \ch_out_south[92] ; |
| wire \ch_out_south[94] ; |
| wire \ch_out_south[95] ; |
| wire \ch_out_south[97] ; |
| wire \ch_out_south[98] ; |
| wire \ch_out_south[9] ; |
| wire \ch_out_west[0] ; |
| wire \ch_out_west[12] ; |
| wire \ch_out_west[15] ; |
| wire \ch_out_west[18] ; |
| wire \ch_out_west[21] ; |
| wire \ch_out_west[24] ; |
| wire \ch_out_west[27] ; |
| wire \ch_out_west[30] ; |
| wire \ch_out_west[33] ; |
| wire \ch_out_west[36] ; |
| wire \ch_out_west[39] ; |
| wire \ch_out_west[3] ; |
| wire \ch_out_west[6] ; |
| wire \ch_out_west[9] ; |
| wire cpu_clk; |
| wire cpu_clk_aes_skew; |
| wire cpu_clk_fpu_skew; |
| wire \cpu_clk_rp[2] ; |
| wire \cpu_core_rst_n[0] ; |
| wire \cpu_core_rst_n[1] ; |
| wire \cpu_core_rst_n[2] ; |
| wire \cpu_core_rst_n[3] ; |
| wire e_reset_n; |
| wire e_reset_n_rp; |
| wire i2c_rst_n; |
| wire i2cm_clk_i; |
| wire i2cm_clk_o; |
| wire i2cm_clk_oen; |
| wire i2cm_data_i; |
| wire i2cm_data_o; |
| wire i2cm_data_oen; |
| wire i2cm_intr_o; |
| wire \io_oeb_int[0] ; |
| wire \io_oeb_int[10] ; |
| wire \io_oeb_int[11] ; |
| wire \io_oeb_int[12] ; |
| wire \io_oeb_int[13] ; |
| wire \io_oeb_int[14] ; |
| wire \io_oeb_int[15] ; |
| wire \io_oeb_int[16] ; |
| wire \io_oeb_int[17] ; |
| wire \io_oeb_int[18] ; |
| wire \io_oeb_int[19] ; |
| wire \io_oeb_int[1] ; |
| wire \io_oeb_int[20] ; |
| wire \io_oeb_int[21] ; |
| wire \io_oeb_int[22] ; |
| wire \io_oeb_int[23] ; |
| wire \io_oeb_int[24] ; |
| wire \io_oeb_int[25] ; |
| wire \io_oeb_int[26] ; |
| wire \io_oeb_int[27] ; |
| wire \io_oeb_int[28] ; |
| wire \io_oeb_int[29] ; |
| wire \io_oeb_int[2] ; |
| wire \io_oeb_int[30] ; |
| wire \io_oeb_int[31] ; |
| wire \io_oeb_int[32] ; |
| wire \io_oeb_int[33] ; |
| wire \io_oeb_int[34] ; |
| wire \io_oeb_int[35] ; |
| wire \io_oeb_int[36] ; |
| wire \io_oeb_int[37] ; |
| wire \io_oeb_int[3] ; |
| wire \io_oeb_int[4] ; |
| wire \io_oeb_int[5] ; |
| wire \io_oeb_int[6] ; |
| wire \io_oeb_int[7] ; |
| wire \io_oeb_int[8] ; |
| wire \io_oeb_int[9] ; |
| wire \io_out_int[0] ; |
| wire \io_out_int[10] ; |
| wire \io_out_int[11] ; |
| wire \io_out_int[12] ; |
| wire \io_out_int[13] ; |
| wire \io_out_int[14] ; |
| wire \io_out_int[15] ; |
| wire \io_out_int[16] ; |
| wire \io_out_int[17] ; |
| wire \io_out_int[18] ; |
| wire \io_out_int[19] ; |
| wire \io_out_int[1] ; |
| wire \io_out_int[20] ; |
| wire \io_out_int[21] ; |
| wire \io_out_int[22] ; |
| wire \io_out_int[23] ; |
| wire \io_out_int[24] ; |
| wire \io_out_int[25] ; |
| wire \io_out_int[26] ; |
| wire \io_out_int[27] ; |
| wire \io_out_int[28] ; |
| wire \io_out_int[29] ; |
| wire \io_out_int[2] ; |
| wire \io_out_int[30] ; |
| wire \io_out_int[31] ; |
| wire \io_out_int[32] ; |
| wire \io_out_int[33] ; |
| wire \io_out_int[34] ; |
| wire \io_out_int[35] ; |
| wire \io_out_int[36] ; |
| wire \io_out_int[37] ; |
| wire \io_out_int[3] ; |
| wire \io_out_int[4] ; |
| wire \io_out_int[5] ; |
| wire \io_out_int[6] ; |
| wire \io_out_int[7] ; |
| wire \io_out_int[8] ; |
| wire \io_out_int[9] ; |
| wire ir_intr; |
| wire ir_rx; |
| wire ir_tx; |
| wire \irq_lines[0] ; |
| wire \irq_lines[10] ; |
| wire \irq_lines[11] ; |
| wire \irq_lines[12] ; |
| wire \irq_lines[13] ; |
| wire \irq_lines[14] ; |
| wire \irq_lines[15] ; |
| wire \irq_lines[16] ; |
| wire \irq_lines[17] ; |
| wire \irq_lines[18] ; |
| wire \irq_lines[19] ; |
| wire \irq_lines[1] ; |
| wire \irq_lines[20] ; |
| wire \irq_lines[21] ; |
| wire \irq_lines[22] ; |
| wire \irq_lines[23] ; |
| wire \irq_lines[24] ; |
| wire \irq_lines[25] ; |
| wire \irq_lines[26] ; |
| wire \irq_lines[27] ; |
| wire \irq_lines[28] ; |
| wire \irq_lines[29] ; |
| wire \irq_lines[2] ; |
| wire \irq_lines[30] ; |
| wire \irq_lines[31] ; |
| wire \irq_lines[3] ; |
| wire \irq_lines[4] ; |
| wire \irq_lines[5] ; |
| wire \irq_lines[6] ; |
| wire \irq_lines[7] ; |
| wire \irq_lines[8] ; |
| wire \irq_lines[9] ; |
| wire p_reset_n; |
| wire p_reset_n_rp; |
| wire \pinmux_debug[0] ; |
| wire \pinmux_debug[10] ; |
| wire \pinmux_debug[11] ; |
| wire \pinmux_debug[12] ; |
| wire \pinmux_debug[13] ; |
| wire \pinmux_debug[14] ; |
| wire \pinmux_debug[15] ; |
| wire \pinmux_debug[16] ; |
| wire \pinmux_debug[17] ; |
| wire \pinmux_debug[18] ; |
| wire \pinmux_debug[19] ; |
| wire \pinmux_debug[1] ; |
| wire \pinmux_debug[20] ; |
| wire \pinmux_debug[21] ; |
| wire \pinmux_debug[22] ; |
| wire \pinmux_debug[23] ; |
| wire \pinmux_debug[24] ; |
| wire \pinmux_debug[25] ; |
| wire \pinmux_debug[26] ; |
| wire \pinmux_debug[27] ; |
| wire \pinmux_debug[28] ; |
| wire \pinmux_debug[29] ; |
| wire \pinmux_debug[2] ; |
| wire \pinmux_debug[30] ; |
| wire \pinmux_debug[31] ; |
| wire \pinmux_debug[3] ; |
| wire \pinmux_debug[4] ; |
| wire \pinmux_debug[5] ; |
| wire \pinmux_debug[6] ; |
| wire \pinmux_debug[7] ; |
| wire \pinmux_debug[8] ; |
| wire \pinmux_debug[9] ; |
| wire \pll_clk_out[0] ; |
| wire \pll_clk_out[1] ; |
| wire pll_ref_clk; |
| wire pulse1m_mclk; |
| wire qspim_rst_n; |
| wire reg_peri_ack; |
| wire \reg_peri_addr[0] ; |
| wire \reg_peri_addr[10] ; |
| wire \reg_peri_addr[1] ; |
| wire \reg_peri_addr[2] ; |
| wire \reg_peri_addr[3] ; |
| wire \reg_peri_addr[4] ; |
| wire \reg_peri_addr[5] ; |
| wire \reg_peri_addr[6] ; |
| wire \reg_peri_addr[7] ; |
| wire \reg_peri_addr[8] ; |
| wire \reg_peri_addr[9] ; |
| wire \reg_peri_be[0] ; |
| wire \reg_peri_be[1] ; |
| wire \reg_peri_be[2] ; |
| wire \reg_peri_be[3] ; |
| wire reg_peri_cs; |
| wire \reg_peri_rdata[0] ; |
| wire \reg_peri_rdata[10] ; |
| wire \reg_peri_rdata[11] ; |
| wire \reg_peri_rdata[12] ; |
| wire \reg_peri_rdata[13] ; |
| wire \reg_peri_rdata[14] ; |
| wire \reg_peri_rdata[15] ; |
| wire \reg_peri_rdata[16] ; |
| wire \reg_peri_rdata[17] ; |
| wire \reg_peri_rdata[18] ; |
| wire \reg_peri_rdata[19] ; |
| wire \reg_peri_rdata[1] ; |
| wire \reg_peri_rdata[20] ; |
| wire \reg_peri_rdata[21] ; |
| wire \reg_peri_rdata[22] ; |
| wire \reg_peri_rdata[23] ; |
| wire \reg_peri_rdata[24] ; |
| wire \reg_peri_rdata[25] ; |
| wire \reg_peri_rdata[26] ; |
| wire \reg_peri_rdata[27] ; |
| wire \reg_peri_rdata[28] ; |
| wire \reg_peri_rdata[29] ; |
| wire \reg_peri_rdata[2] ; |
| wire \reg_peri_rdata[30] ; |
| wire \reg_peri_rdata[31] ; |
| wire \reg_peri_rdata[3] ; |
| wire \reg_peri_rdata[4] ; |
| wire \reg_peri_rdata[5] ; |
| wire \reg_peri_rdata[6] ; |
| wire \reg_peri_rdata[7] ; |
| wire \reg_peri_rdata[8] ; |
| wire \reg_peri_rdata[9] ; |
| wire \reg_peri_wdata[0] ; |
| wire \reg_peri_wdata[10] ; |
| wire \reg_peri_wdata[11] ; |
| wire \reg_peri_wdata[12] ; |
| wire \reg_peri_wdata[13] ; |
| wire \reg_peri_wdata[14] ; |
| wire \reg_peri_wdata[15] ; |
| wire \reg_peri_wdata[16] ; |
| wire \reg_peri_wdata[17] ; |
| wire \reg_peri_wdata[18] ; |
| wire \reg_peri_wdata[19] ; |
| wire \reg_peri_wdata[1] ; |
| wire \reg_peri_wdata[20] ; |
| wire \reg_peri_wdata[21] ; |
| wire \reg_peri_wdata[22] ; |
| wire \reg_peri_wdata[23] ; |
| wire \reg_peri_wdata[24] ; |
| wire \reg_peri_wdata[25] ; |
| wire \reg_peri_wdata[26] ; |
| wire \reg_peri_wdata[27] ; |
| wire \reg_peri_wdata[28] ; |
| wire \reg_peri_wdata[29] ; |
| wire \reg_peri_wdata[2] ; |
| wire \reg_peri_wdata[30] ; |
| wire \reg_peri_wdata[31] ; |
| wire \reg_peri_wdata[3] ; |
| wire \reg_peri_wdata[4] ; |
| wire \reg_peri_wdata[5] ; |
| wire \reg_peri_wdata[6] ; |
| wire \reg_peri_wdata[7] ; |
| wire \reg_peri_wdata[8] ; |
| wire \reg_peri_wdata[9] ; |
| wire reg_peri_wr; |
| wire rtc_intr; |
| wire s_reset_n; |
| wire \sflash_di[0] ; |
| wire \sflash_di[1] ; |
| wire \sflash_di[2] ; |
| wire \sflash_di[3] ; |
| wire \sflash_do[0] ; |
| wire \sflash_do[1] ; |
| wire \sflash_do[2] ; |
| wire \sflash_do[3] ; |
| wire \sflash_oen[0] ; |
| wire \sflash_oen[1] ; |
| wire \sflash_oen[2] ; |
| wire \sflash_oen[3] ; |
| wire sflash_sck; |
| wire soft_irq; |
| wire \spi_csn[0] ; |
| wire \spi_csn[1] ; |
| wire \spi_csn[2] ; |
| wire \spi_csn[3] ; |
| wire \spi_debug[0] ; |
| wire \spi_debug[10] ; |
| wire \spi_debug[11] ; |
| wire \spi_debug[12] ; |
| wire \spi_debug[13] ; |
| wire \spi_debug[14] ; |
| wire \spi_debug[15] ; |
| wire \spi_debug[16] ; |
| wire \spi_debug[17] ; |
| wire \spi_debug[18] ; |
| wire \spi_debug[19] ; |
| wire \spi_debug[1] ; |
| wire \spi_debug[20] ; |
| wire \spi_debug[21] ; |
| wire \spi_debug[22] ; |
| wire \spi_debug[23] ; |
| wire \spi_debug[24] ; |
| wire \spi_debug[25] ; |
| wire \spi_debug[26] ; |
| wire \spi_debug[27] ; |
| wire \spi_debug[28] ; |
| wire \spi_debug[29] ; |
| wire \spi_debug[2] ; |
| wire \spi_debug[30] ; |
| wire \spi_debug[31] ; |
| wire \spi_debug[3] ; |
| wire \spi_debug[4] ; |
| wire \spi_debug[5] ; |
| wire \spi_debug[6] ; |
| wire \spi_debug[7] ; |
| wire \spi_debug[8] ; |
| wire \spi_debug[9] ; |
| wire sspim_rst_n; |
| wire sspim_sck; |
| wire sspim_si; |
| wire sspim_so; |
| wire \sspim_ssn[0] ; |
| wire \sspim_ssn[1] ; |
| wire \sspim_ssn[2] ; |
| wire \sspim_ssn[3] ; |
| wire sspis_sck; |
| wire sspis_si; |
| wire sspis_so; |
| wire sspis_ssn; |
| wire \strap_sticky[0] ; |
| wire \strap_sticky[10] ; |
| wire \strap_sticky[11] ; |
| wire \strap_sticky[12] ; |
| wire \strap_sticky[13] ; |
| wire \strap_sticky[14] ; |
| wire \strap_sticky[15] ; |
| wire \strap_sticky[16] ; |
| wire \strap_sticky[17] ; |
| wire \strap_sticky[18] ; |
| wire \strap_sticky[19] ; |
| wire \strap_sticky[1] ; |
| wire \strap_sticky[20] ; |
| wire \strap_sticky[21] ; |
| wire \strap_sticky[22] ; |
| wire \strap_sticky[23] ; |
| wire \strap_sticky[24] ; |
| wire \strap_sticky[25] ; |
| wire \strap_sticky[26] ; |
| wire \strap_sticky[27] ; |
| wire \strap_sticky[28] ; |
| wire \strap_sticky[29] ; |
| wire \strap_sticky[2] ; |
| wire \strap_sticky[30] ; |
| wire \strap_sticky[31] ; |
| wire \strap_sticky[3] ; |
| wire \strap_sticky[4] ; |
| wire \strap_sticky[5] ; |
| wire \strap_sticky[6] ; |
| wire \strap_sticky[7] ; |
| wire \strap_sticky[8] ; |
| wire \strap_sticky[9] ; |
| wire \strap_sticky_rp[0] ; |
| wire \strap_sticky_rp[10] ; |
| wire \strap_sticky_rp[11] ; |
| wire \strap_sticky_rp[12] ; |
| wire \strap_sticky_rp[13] ; |
| wire \strap_sticky_rp[14] ; |
| wire \strap_sticky_rp[15] ; |
| wire \strap_sticky_rp[16] ; |
| wire \strap_sticky_rp[17] ; |
| wire \strap_sticky_rp[18] ; |
| wire \strap_sticky_rp[19] ; |
| wire \strap_sticky_rp[1] ; |
| wire \strap_sticky_rp[20] ; |
| wire \strap_sticky_rp[21] ; |
| wire \strap_sticky_rp[22] ; |
| wire \strap_sticky_rp[23] ; |
| wire \strap_sticky_rp[24] ; |
| wire \strap_sticky_rp[25] ; |
| wire \strap_sticky_rp[26] ; |
| wire \strap_sticky_rp[27] ; |
| wire \strap_sticky_rp[28] ; |
| wire \strap_sticky_rp[29] ; |
| wire \strap_sticky_rp[2] ; |
| wire \strap_sticky_rp[30] ; |
| wire \strap_sticky_rp[31] ; |
| wire \strap_sticky_rp[3] ; |
| wire \strap_sticky_rp[4] ; |
| wire \strap_sticky_rp[5] ; |
| wire \strap_sticky_rp[6] ; |
| wire \strap_sticky_rp[7] ; |
| wire \strap_sticky_rp[8] ; |
| wire \strap_sticky_rp[9] ; |
| wire \strap_uartm[0] ; |
| wire \strap_uartm[1] ; |
| wire \strap_uartm_rp[0] ; |
| wire \strap_uartm_rp[1] ; |
| wire \system_strap[0] ; |
| wire \system_strap[10] ; |
| wire \system_strap[11] ; |
| wire \system_strap[12] ; |
| wire \system_strap[13] ; |
| wire \system_strap[14] ; |
| wire \system_strap[15] ; |
| wire \system_strap[16] ; |
| wire \system_strap[17] ; |
| wire \system_strap[18] ; |
| wire \system_strap[19] ; |
| wire \system_strap[1] ; |
| wire \system_strap[20] ; |
| wire \system_strap[21] ; |
| wire \system_strap[22] ; |
| wire \system_strap[23] ; |
| wire \system_strap[24] ; |
| wire \system_strap[25] ; |
| wire \system_strap[26] ; |
| wire \system_strap[27] ; |
| wire \system_strap[28] ; |
| wire \system_strap[29] ; |
| wire \system_strap[2] ; |
| wire \system_strap[30] ; |
| wire \system_strap[31] ; |
| wire \system_strap[3] ; |
| wire \system_strap[4] ; |
| wire \system_strap[5] ; |
| wire \system_strap[6] ; |
| wire \system_strap[7] ; |
| wire \system_strap[8] ; |
| wire \system_strap[9] ; |
| wire \system_strap_rp[0] ; |
| wire \system_strap_rp[10] ; |
| wire \system_strap_rp[11] ; |
| wire \system_strap_rp[12] ; |
| wire \system_strap_rp[13] ; |
| wire \system_strap_rp[14] ; |
| wire \system_strap_rp[15] ; |
| wire \system_strap_rp[16] ; |
| wire \system_strap_rp[17] ; |
| wire \system_strap_rp[18] ; |
| wire \system_strap_rp[19] ; |
| wire \system_strap_rp[1] ; |
| wire \system_strap_rp[20] ; |
| wire \system_strap_rp[21] ; |
| wire \system_strap_rp[22] ; |
| wire \system_strap_rp[23] ; |
| wire \system_strap_rp[24] ; |
| wire \system_strap_rp[25] ; |
| wire \system_strap_rp[26] ; |
| wire \system_strap_rp[27] ; |
| wire \system_strap_rp[28] ; |
| wire \system_strap_rp[29] ; |
| wire \system_strap_rp[2] ; |
| wire \system_strap_rp[30] ; |
| wire \system_strap_rp[31] ; |
| wire \system_strap_rp[3] ; |
| wire \system_strap_rp[4] ; |
| wire \system_strap_rp[5] ; |
| wire \system_strap_rp[6] ; |
| wire \system_strap_rp[7] ; |
| wire \system_strap_rp[8] ; |
| wire \system_strap_rp[9] ; |
| wire \u_riscv_top.aes_dmem_addr[0] ; |
| wire \u_riscv_top.aes_dmem_addr[1] ; |
| wire \u_riscv_top.aes_dmem_addr[2] ; |
| wire \u_riscv_top.aes_dmem_addr[3] ; |
| wire \u_riscv_top.aes_dmem_addr[4] ; |
| wire \u_riscv_top.aes_dmem_addr[5] ; |
| wire \u_riscv_top.aes_dmem_addr[6] ; |
| wire \u_riscv_top.aes_dmem_cmd ; |
| wire \u_riscv_top.aes_dmem_rdata[0] ; |
| wire \u_riscv_top.aes_dmem_rdata[10] ; |
| wire \u_riscv_top.aes_dmem_rdata[11] ; |
| wire \u_riscv_top.aes_dmem_rdata[12] ; |
| wire \u_riscv_top.aes_dmem_rdata[13] ; |
| wire \u_riscv_top.aes_dmem_rdata[14] ; |
| wire \u_riscv_top.aes_dmem_rdata[15] ; |
| wire \u_riscv_top.aes_dmem_rdata[16] ; |
| wire \u_riscv_top.aes_dmem_rdata[17] ; |
| wire \u_riscv_top.aes_dmem_rdata[18] ; |
| wire \u_riscv_top.aes_dmem_rdata[19] ; |
| wire \u_riscv_top.aes_dmem_rdata[1] ; |
| wire \u_riscv_top.aes_dmem_rdata[20] ; |
| wire \u_riscv_top.aes_dmem_rdata[21] ; |
| wire \u_riscv_top.aes_dmem_rdata[22] ; |
| wire \u_riscv_top.aes_dmem_rdata[23] ; |
| wire \u_riscv_top.aes_dmem_rdata[24] ; |
| wire \u_riscv_top.aes_dmem_rdata[25] ; |
| wire \u_riscv_top.aes_dmem_rdata[26] ; |
| wire \u_riscv_top.aes_dmem_rdata[27] ; |
| wire \u_riscv_top.aes_dmem_rdata[28] ; |
| wire \u_riscv_top.aes_dmem_rdata[29] ; |
| wire \u_riscv_top.aes_dmem_rdata[2] ; |
| wire \u_riscv_top.aes_dmem_rdata[30] ; |
| wire \u_riscv_top.aes_dmem_rdata[31] ; |
| wire \u_riscv_top.aes_dmem_rdata[3] ; |
| wire \u_riscv_top.aes_dmem_rdata[4] ; |
| wire \u_riscv_top.aes_dmem_rdata[5] ; |
| wire \u_riscv_top.aes_dmem_rdata[6] ; |
| wire \u_riscv_top.aes_dmem_rdata[7] ; |
| wire \u_riscv_top.aes_dmem_rdata[8] ; |
| wire \u_riscv_top.aes_dmem_rdata[9] ; |
| wire \u_riscv_top.aes_dmem_req ; |
| wire \u_riscv_top.aes_dmem_req_ack ; |
| wire \u_riscv_top.aes_dmem_resp[0] ; |
| wire \u_riscv_top.aes_dmem_resp[1] ; |
| wire \u_riscv_top.aes_dmem_wdata[0] ; |
| wire \u_riscv_top.aes_dmem_wdata[10] ; |
| wire \u_riscv_top.aes_dmem_wdata[11] ; |
| wire \u_riscv_top.aes_dmem_wdata[12] ; |
| wire \u_riscv_top.aes_dmem_wdata[13] ; |
| wire \u_riscv_top.aes_dmem_wdata[14] ; |
| wire \u_riscv_top.aes_dmem_wdata[15] ; |
| wire \u_riscv_top.aes_dmem_wdata[16] ; |
| wire \u_riscv_top.aes_dmem_wdata[17] ; |
| wire \u_riscv_top.aes_dmem_wdata[18] ; |
| wire \u_riscv_top.aes_dmem_wdata[19] ; |
| wire \u_riscv_top.aes_dmem_wdata[1] ; |
| wire \u_riscv_top.aes_dmem_wdata[20] ; |
| wire \u_riscv_top.aes_dmem_wdata[21] ; |
| wire \u_riscv_top.aes_dmem_wdata[22] ; |
| wire \u_riscv_top.aes_dmem_wdata[23] ; |
| wire \u_riscv_top.aes_dmem_wdata[24] ; |
| wire \u_riscv_top.aes_dmem_wdata[25] ; |
| wire \u_riscv_top.aes_dmem_wdata[26] ; |
| wire \u_riscv_top.aes_dmem_wdata[27] ; |
| wire \u_riscv_top.aes_dmem_wdata[28] ; |
| wire \u_riscv_top.aes_dmem_wdata[29] ; |
| wire \u_riscv_top.aes_dmem_wdata[2] ; |
| wire \u_riscv_top.aes_dmem_wdata[30] ; |
| wire \u_riscv_top.aes_dmem_wdata[31] ; |
| wire \u_riscv_top.aes_dmem_wdata[3] ; |
| wire \u_riscv_top.aes_dmem_wdata[4] ; |
| wire \u_riscv_top.aes_dmem_wdata[5] ; |
| wire \u_riscv_top.aes_dmem_wdata[6] ; |
| wire \u_riscv_top.aes_dmem_wdata[7] ; |
| wire \u_riscv_top.aes_dmem_wdata[8] ; |
| wire \u_riscv_top.aes_dmem_wdata[9] ; |
| wire \u_riscv_top.aes_dmem_width[0] ; |
| wire \u_riscv_top.aes_dmem_width[1] ; |
| wire \u_riscv_top.cfg_ccska_riscv_core0[0] ; |
| wire \u_riscv_top.cfg_ccska_riscv_core0[1] ; |
| wire \u_riscv_top.cfg_ccska_riscv_core0[2] ; |
| wire \u_riscv_top.cfg_ccska_riscv_core0[3] ; |
| wire \u_riscv_top.cfg_ccska_riscv_core1[0] ; |
| wire \u_riscv_top.cfg_ccska_riscv_core1[1] ; |
| wire \u_riscv_top.cfg_ccska_riscv_core1[2] ; |
| wire \u_riscv_top.cfg_ccska_riscv_core1[3] ; |
| wire \u_riscv_top.cfg_ccska_riscv_icon[0] ; |
| wire \u_riscv_top.cfg_ccska_riscv_icon[1] ; |
| wire \u_riscv_top.cfg_ccska_riscv_icon[2] ; |
| wire \u_riscv_top.cfg_ccska_riscv_icon[3] ; |
| wire \u_riscv_top.cfg_ccska_riscv_intf[0] ; |
| wire \u_riscv_top.cfg_ccska_riscv_intf[1] ; |
| wire \u_riscv_top.cfg_ccska_riscv_intf[2] ; |
| wire \u_riscv_top.cfg_ccska_riscv_intf[3] ; |
| wire \u_riscv_top.cfg_dcache_force_flush ; |
| wire \u_riscv_top.cfg_wcska_riscv_intf[0] ; |
| wire \u_riscv_top.cfg_wcska_riscv_intf[1] ; |
| wire \u_riscv_top.cfg_wcska_riscv_intf[2] ; |
| wire \u_riscv_top.cfg_wcska_riscv_intf[3] ; |
| wire \u_riscv_top.core0_clk ; |
| wire \u_riscv_top.core0_debug[0] ; |
| wire \u_riscv_top.core0_debug[10] ; |
| wire \u_riscv_top.core0_debug[11] ; |
| wire \u_riscv_top.core0_debug[12] ; |
| wire \u_riscv_top.core0_debug[13] ; |
| wire \u_riscv_top.core0_debug[14] ; |
| wire \u_riscv_top.core0_debug[15] ; |
| wire \u_riscv_top.core0_debug[16] ; |
| wire \u_riscv_top.core0_debug[17] ; |
| wire \u_riscv_top.core0_debug[18] ; |
| wire \u_riscv_top.core0_debug[19] ; |
| wire \u_riscv_top.core0_debug[1] ; |
| wire \u_riscv_top.core0_debug[20] ; |
| wire \u_riscv_top.core0_debug[21] ; |
| wire \u_riscv_top.core0_debug[22] ; |
| wire \u_riscv_top.core0_debug[23] ; |
| wire \u_riscv_top.core0_debug[24] ; |
| wire \u_riscv_top.core0_debug[25] ; |
| wire \u_riscv_top.core0_debug[26] ; |
| wire \u_riscv_top.core0_debug[27] ; |
| wire \u_riscv_top.core0_debug[28] ; |
| wire \u_riscv_top.core0_debug[29] ; |
| wire \u_riscv_top.core0_debug[2] ; |
| wire \u_riscv_top.core0_debug[30] ; |
| wire \u_riscv_top.core0_debug[31] ; |
| wire \u_riscv_top.core0_debug[32] ; |
| wire \u_riscv_top.core0_debug[33] ; |
| wire \u_riscv_top.core0_debug[34] ; |
| wire \u_riscv_top.core0_debug[35] ; |
| wire \u_riscv_top.core0_debug[36] ; |
| wire \u_riscv_top.core0_debug[37] ; |
| wire \u_riscv_top.core0_debug[38] ; |
| wire \u_riscv_top.core0_debug[39] ; |
| wire \u_riscv_top.core0_debug[3] ; |
| wire \u_riscv_top.core0_debug[40] ; |
| wire \u_riscv_top.core0_debug[41] ; |
| wire \u_riscv_top.core0_debug[42] ; |
| wire \u_riscv_top.core0_debug[43] ; |
| wire \u_riscv_top.core0_debug[44] ; |
| wire \u_riscv_top.core0_debug[45] ; |
| wire \u_riscv_top.core0_debug[46] ; |
| wire \u_riscv_top.core0_debug[47] ; |
| wire \u_riscv_top.core0_debug[48] ; |
| wire \u_riscv_top.core0_debug[4] ; |
| wire \u_riscv_top.core0_debug[5] ; |
| wire \u_riscv_top.core0_debug[6] ; |
| wire \u_riscv_top.core0_debug[7] ; |
| wire \u_riscv_top.core0_debug[8] ; |
| wire \u_riscv_top.core0_debug[9] ; |
| wire \u_riscv_top.core0_dmem_addr[0] ; |
| wire \u_riscv_top.core0_dmem_addr[10] ; |
| wire \u_riscv_top.core0_dmem_addr[11] ; |
| wire \u_riscv_top.core0_dmem_addr[12] ; |
| wire \u_riscv_top.core0_dmem_addr[13] ; |
| wire \u_riscv_top.core0_dmem_addr[14] ; |
| wire \u_riscv_top.core0_dmem_addr[15] ; |
| wire \u_riscv_top.core0_dmem_addr[16] ; |
| wire \u_riscv_top.core0_dmem_addr[17] ; |
| wire \u_riscv_top.core0_dmem_addr[18] ; |
| wire \u_riscv_top.core0_dmem_addr[19] ; |
| wire \u_riscv_top.core0_dmem_addr[1] ; |
| wire \u_riscv_top.core0_dmem_addr[20] ; |
| wire \u_riscv_top.core0_dmem_addr[21] ; |
| wire \u_riscv_top.core0_dmem_addr[22] ; |
| wire \u_riscv_top.core0_dmem_addr[23] ; |
| wire \u_riscv_top.core0_dmem_addr[24] ; |
| wire \u_riscv_top.core0_dmem_addr[25] ; |
| wire \u_riscv_top.core0_dmem_addr[26] ; |
| wire \u_riscv_top.core0_dmem_addr[27] ; |
| wire \u_riscv_top.core0_dmem_addr[28] ; |
| wire \u_riscv_top.core0_dmem_addr[29] ; |
| wire \u_riscv_top.core0_dmem_addr[2] ; |
| wire \u_riscv_top.core0_dmem_addr[30] ; |
| wire \u_riscv_top.core0_dmem_addr[31] ; |
| wire \u_riscv_top.core0_dmem_addr[3] ; |
| wire \u_riscv_top.core0_dmem_addr[4] ; |
| wire \u_riscv_top.core0_dmem_addr[5] ; |
| wire \u_riscv_top.core0_dmem_addr[6] ; |
| wire \u_riscv_top.core0_dmem_addr[7] ; |
| wire \u_riscv_top.core0_dmem_addr[8] ; |
| wire \u_riscv_top.core0_dmem_addr[9] ; |
| wire \u_riscv_top.core0_dmem_cmd ; |
| wire \u_riscv_top.core0_dmem_rdata[0] ; |
| wire \u_riscv_top.core0_dmem_rdata[10] ; |
| wire \u_riscv_top.core0_dmem_rdata[11] ; |
| wire \u_riscv_top.core0_dmem_rdata[12] ; |
| wire \u_riscv_top.core0_dmem_rdata[13] ; |
| wire \u_riscv_top.core0_dmem_rdata[14] ; |
| wire \u_riscv_top.core0_dmem_rdata[15] ; |
| wire \u_riscv_top.core0_dmem_rdata[16] ; |
| wire \u_riscv_top.core0_dmem_rdata[17] ; |
| wire \u_riscv_top.core0_dmem_rdata[18] ; |
| wire \u_riscv_top.core0_dmem_rdata[19] ; |
| wire \u_riscv_top.core0_dmem_rdata[1] ; |
| wire \u_riscv_top.core0_dmem_rdata[20] ; |
| wire \u_riscv_top.core0_dmem_rdata[21] ; |
| wire \u_riscv_top.core0_dmem_rdata[22] ; |
| wire \u_riscv_top.core0_dmem_rdata[23] ; |
| wire \u_riscv_top.core0_dmem_rdata[24] ; |
| wire \u_riscv_top.core0_dmem_rdata[25] ; |
| wire \u_riscv_top.core0_dmem_rdata[26] ; |
| wire \u_riscv_top.core0_dmem_rdata[27] ; |
| wire \u_riscv_top.core0_dmem_rdata[28] ; |
| wire \u_riscv_top.core0_dmem_rdata[29] ; |
| wire \u_riscv_top.core0_dmem_rdata[2] ; |
| wire \u_riscv_top.core0_dmem_rdata[30] ; |
| wire \u_riscv_top.core0_dmem_rdata[31] ; |
| wire \u_riscv_top.core0_dmem_rdata[3] ; |
| wire \u_riscv_top.core0_dmem_rdata[4] ; |
| wire \u_riscv_top.core0_dmem_rdata[5] ; |
| wire \u_riscv_top.core0_dmem_rdata[6] ; |
| wire \u_riscv_top.core0_dmem_rdata[7] ; |
| wire \u_riscv_top.core0_dmem_rdata[8] ; |
| wire \u_riscv_top.core0_dmem_rdata[9] ; |
| wire \u_riscv_top.core0_dmem_req ; |
| wire \u_riscv_top.core0_dmem_req_ack ; |
| wire \u_riscv_top.core0_dmem_resp[0] ; |
| wire \u_riscv_top.core0_dmem_resp[1] ; |
| wire \u_riscv_top.core0_dmem_wdata[0] ; |
| wire \u_riscv_top.core0_dmem_wdata[10] ; |
| wire \u_riscv_top.core0_dmem_wdata[11] ; |
| wire \u_riscv_top.core0_dmem_wdata[12] ; |
| wire \u_riscv_top.core0_dmem_wdata[13] ; |
| wire \u_riscv_top.core0_dmem_wdata[14] ; |
| wire \u_riscv_top.core0_dmem_wdata[15] ; |
| wire \u_riscv_top.core0_dmem_wdata[16] ; |
| wire \u_riscv_top.core0_dmem_wdata[17] ; |
| wire \u_riscv_top.core0_dmem_wdata[18] ; |
| wire \u_riscv_top.core0_dmem_wdata[19] ; |
| wire \u_riscv_top.core0_dmem_wdata[1] ; |
| wire \u_riscv_top.core0_dmem_wdata[20] ; |
| wire \u_riscv_top.core0_dmem_wdata[21] ; |
| wire \u_riscv_top.core0_dmem_wdata[22] ; |
| wire \u_riscv_top.core0_dmem_wdata[23] ; |
| wire \u_riscv_top.core0_dmem_wdata[24] ; |
| wire \u_riscv_top.core0_dmem_wdata[25] ; |
| wire \u_riscv_top.core0_dmem_wdata[26] ; |
| wire \u_riscv_top.core0_dmem_wdata[27] ; |
| wire \u_riscv_top.core0_dmem_wdata[28] ; |
| wire \u_riscv_top.core0_dmem_wdata[29] ; |
| wire \u_riscv_top.core0_dmem_wdata[2] ; |
| wire \u_riscv_top.core0_dmem_wdata[30] ; |
| wire \u_riscv_top.core0_dmem_wdata[31] ; |
| wire \u_riscv_top.core0_dmem_wdata[3] ; |
| wire \u_riscv_top.core0_dmem_wdata[4] ; |
| wire \u_riscv_top.core0_dmem_wdata[5] ; |
| wire \u_riscv_top.core0_dmem_wdata[6] ; |
| wire \u_riscv_top.core0_dmem_wdata[7] ; |
| wire \u_riscv_top.core0_dmem_wdata[8] ; |
| wire \u_riscv_top.core0_dmem_wdata[9] ; |
| wire \u_riscv_top.core0_dmem_width[0] ; |
| wire \u_riscv_top.core0_dmem_width[1] ; |
| wire \u_riscv_top.core0_imem_addr[0] ; |
| wire \u_riscv_top.core0_imem_addr[10] ; |
| wire \u_riscv_top.core0_imem_addr[11] ; |
| wire \u_riscv_top.core0_imem_addr[12] ; |
| wire \u_riscv_top.core0_imem_addr[13] ; |
| wire \u_riscv_top.core0_imem_addr[14] ; |
| wire \u_riscv_top.core0_imem_addr[15] ; |
| wire \u_riscv_top.core0_imem_addr[16] ; |
| wire \u_riscv_top.core0_imem_addr[17] ; |
| wire \u_riscv_top.core0_imem_addr[18] ; |
| wire \u_riscv_top.core0_imem_addr[19] ; |
| wire \u_riscv_top.core0_imem_addr[1] ; |
| wire \u_riscv_top.core0_imem_addr[20] ; |
| wire \u_riscv_top.core0_imem_addr[21] ; |
| wire \u_riscv_top.core0_imem_addr[22] ; |
| wire \u_riscv_top.core0_imem_addr[23] ; |
| wire \u_riscv_top.core0_imem_addr[24] ; |
| wire \u_riscv_top.core0_imem_addr[25] ; |
| wire \u_riscv_top.core0_imem_addr[26] ; |
| wire \u_riscv_top.core0_imem_addr[27] ; |
| wire \u_riscv_top.core0_imem_addr[28] ; |
| wire \u_riscv_top.core0_imem_addr[29] ; |
| wire \u_riscv_top.core0_imem_addr[2] ; |
| wire \u_riscv_top.core0_imem_addr[30] ; |
| wire \u_riscv_top.core0_imem_addr[31] ; |
| wire \u_riscv_top.core0_imem_addr[3] ; |
| wire \u_riscv_top.core0_imem_addr[4] ; |
| wire \u_riscv_top.core0_imem_addr[5] ; |
| wire \u_riscv_top.core0_imem_addr[6] ; |
| wire \u_riscv_top.core0_imem_addr[7] ; |
| wire \u_riscv_top.core0_imem_addr[8] ; |
| wire \u_riscv_top.core0_imem_addr[9] ; |
| wire \u_riscv_top.core0_imem_bl[0] ; |
| wire \u_riscv_top.core0_imem_bl[1] ; |
| wire \u_riscv_top.core0_imem_bl[2] ; |
| wire \u_riscv_top.core0_imem_cmd ; |
| wire \u_riscv_top.core0_imem_rdata[0] ; |
| wire \u_riscv_top.core0_imem_rdata[10] ; |
| wire \u_riscv_top.core0_imem_rdata[11] ; |
| wire \u_riscv_top.core0_imem_rdata[12] ; |
| wire \u_riscv_top.core0_imem_rdata[13] ; |
| wire \u_riscv_top.core0_imem_rdata[14] ; |
| wire \u_riscv_top.core0_imem_rdata[15] ; |
| wire \u_riscv_top.core0_imem_rdata[16] ; |
| wire \u_riscv_top.core0_imem_rdata[17] ; |
| wire \u_riscv_top.core0_imem_rdata[18] ; |
| wire \u_riscv_top.core0_imem_rdata[19] ; |
| wire \u_riscv_top.core0_imem_rdata[1] ; |
| wire \u_riscv_top.core0_imem_rdata[20] ; |
| wire \u_riscv_top.core0_imem_rdata[21] ; |
| wire \u_riscv_top.core0_imem_rdata[22] ; |
| wire \u_riscv_top.core0_imem_rdata[23] ; |
| wire \u_riscv_top.core0_imem_rdata[24] ; |
| wire \u_riscv_top.core0_imem_rdata[25] ; |
| wire \u_riscv_top.core0_imem_rdata[26] ; |
| wire \u_riscv_top.core0_imem_rdata[27] ; |
| wire \u_riscv_top.core0_imem_rdata[28] ; |
| wire \u_riscv_top.core0_imem_rdata[29] ; |
| wire \u_riscv_top.core0_imem_rdata[2] ; |
| wire \u_riscv_top.core0_imem_rdata[30] ; |
| wire \u_riscv_top.core0_imem_rdata[31] ; |
| wire \u_riscv_top.core0_imem_rdata[3] ; |
| wire \u_riscv_top.core0_imem_rdata[4] ; |
| wire \u_riscv_top.core0_imem_rdata[5] ; |
| wire \u_riscv_top.core0_imem_rdata[6] ; |
| wire \u_riscv_top.core0_imem_rdata[7] ; |
| wire \u_riscv_top.core0_imem_rdata[8] ; |
| wire \u_riscv_top.core0_imem_rdata[9] ; |
| wire \u_riscv_top.core0_imem_req ; |
| wire \u_riscv_top.core0_imem_req_ack ; |
| wire \u_riscv_top.core0_imem_resp[0] ; |
| wire \u_riscv_top.core0_imem_resp[1] ; |
| wire \u_riscv_top.core0_irq_lines[0] ; |
| wire \u_riscv_top.core0_irq_lines[10] ; |
| wire \u_riscv_top.core0_irq_lines[11] ; |
| wire \u_riscv_top.core0_irq_lines[12] ; |
| wire \u_riscv_top.core0_irq_lines[13] ; |
| wire \u_riscv_top.core0_irq_lines[14] ; |
| wire \u_riscv_top.core0_irq_lines[15] ; |
| wire \u_riscv_top.core0_irq_lines[16] ; |
| wire \u_riscv_top.core0_irq_lines[17] ; |
| wire \u_riscv_top.core0_irq_lines[18] ; |
| wire \u_riscv_top.core0_irq_lines[19] ; |
| wire \u_riscv_top.core0_irq_lines[1] ; |
| wire \u_riscv_top.core0_irq_lines[20] ; |
| wire \u_riscv_top.core0_irq_lines[21] ; |
| wire \u_riscv_top.core0_irq_lines[22] ; |
| wire \u_riscv_top.core0_irq_lines[23] ; |
| wire \u_riscv_top.core0_irq_lines[24] ; |
| wire \u_riscv_top.core0_irq_lines[25] ; |
| wire \u_riscv_top.core0_irq_lines[26] ; |
| wire \u_riscv_top.core0_irq_lines[27] ; |
| wire \u_riscv_top.core0_irq_lines[28] ; |
| wire \u_riscv_top.core0_irq_lines[29] ; |
| wire \u_riscv_top.core0_irq_lines[2] ; |
| wire \u_riscv_top.core0_irq_lines[30] ; |
| wire \u_riscv_top.core0_irq_lines[31] ; |
| wire \u_riscv_top.core0_irq_lines[3] ; |
| wire \u_riscv_top.core0_irq_lines[4] ; |
| wire \u_riscv_top.core0_irq_lines[5] ; |
| wire \u_riscv_top.core0_irq_lines[6] ; |
| wire \u_riscv_top.core0_irq_lines[7] ; |
| wire \u_riscv_top.core0_irq_lines[8] ; |
| wire \u_riscv_top.core0_irq_lines[9] ; |
| wire \u_riscv_top.core0_soft_irq ; |
| wire \u_riscv_top.core0_timer_irq ; |
| wire \u_riscv_top.core0_timer_val[0] ; |
| wire \u_riscv_top.core0_timer_val[10] ; |
| wire \u_riscv_top.core0_timer_val[11] ; |
| wire \u_riscv_top.core0_timer_val[12] ; |
| wire \u_riscv_top.core0_timer_val[13] ; |
| wire \u_riscv_top.core0_timer_val[14] ; |
| wire \u_riscv_top.core0_timer_val[15] ; |
| wire \u_riscv_top.core0_timer_val[16] ; |
| wire \u_riscv_top.core0_timer_val[17] ; |
| wire \u_riscv_top.core0_timer_val[18] ; |
| wire \u_riscv_top.core0_timer_val[19] ; |
| wire \u_riscv_top.core0_timer_val[1] ; |
| wire \u_riscv_top.core0_timer_val[20] ; |
| wire \u_riscv_top.core0_timer_val[21] ; |
| wire \u_riscv_top.core0_timer_val[22] ; |
| wire \u_riscv_top.core0_timer_val[23] ; |
| wire \u_riscv_top.core0_timer_val[24] ; |
| wire \u_riscv_top.core0_timer_val[25] ; |
| wire \u_riscv_top.core0_timer_val[26] ; |
| wire \u_riscv_top.core0_timer_val[27] ; |
| wire \u_riscv_top.core0_timer_val[28] ; |
| wire \u_riscv_top.core0_timer_val[29] ; |
| wire \u_riscv_top.core0_timer_val[2] ; |
| wire \u_riscv_top.core0_timer_val[30] ; |
| wire \u_riscv_top.core0_timer_val[31] ; |
| wire \u_riscv_top.core0_timer_val[32] ; |
| wire \u_riscv_top.core0_timer_val[33] ; |
| wire \u_riscv_top.core0_timer_val[34] ; |
| wire \u_riscv_top.core0_timer_val[35] ; |
| wire \u_riscv_top.core0_timer_val[36] ; |
| wire \u_riscv_top.core0_timer_val[37] ; |
| wire \u_riscv_top.core0_timer_val[38] ; |
| wire \u_riscv_top.core0_timer_val[39] ; |
| wire \u_riscv_top.core0_timer_val[3] ; |
| wire \u_riscv_top.core0_timer_val[40] ; |
| wire \u_riscv_top.core0_timer_val[41] ; |
| wire \u_riscv_top.core0_timer_val[42] ; |
| wire \u_riscv_top.core0_timer_val[43] ; |
| wire \u_riscv_top.core0_timer_val[44] ; |
| wire \u_riscv_top.core0_timer_val[45] ; |
| wire \u_riscv_top.core0_timer_val[46] ; |
| wire \u_riscv_top.core0_timer_val[47] ; |
| wire \u_riscv_top.core0_timer_val[48] ; |
| wire \u_riscv_top.core0_timer_val[49] ; |
| wire \u_riscv_top.core0_timer_val[4] ; |
| wire \u_riscv_top.core0_timer_val[50] ; |
| wire \u_riscv_top.core0_timer_val[51] ; |
| wire \u_riscv_top.core0_timer_val[52] ; |
| wire \u_riscv_top.core0_timer_val[53] ; |
| wire \u_riscv_top.core0_timer_val[54] ; |
| wire \u_riscv_top.core0_timer_val[55] ; |
| wire \u_riscv_top.core0_timer_val[56] ; |
| wire \u_riscv_top.core0_timer_val[57] ; |
| wire \u_riscv_top.core0_timer_val[58] ; |
| wire \u_riscv_top.core0_timer_val[59] ; |
| wire \u_riscv_top.core0_timer_val[5] ; |
| wire \u_riscv_top.core0_timer_val[60] ; |
| wire \u_riscv_top.core0_timer_val[61] ; |
| wire \u_riscv_top.core0_timer_val[62] ; |
| wire \u_riscv_top.core0_timer_val[63] ; |
| wire \u_riscv_top.core0_timer_val[6] ; |
| wire \u_riscv_top.core0_timer_val[7] ; |
| wire \u_riscv_top.core0_timer_val[8] ; |
| wire \u_riscv_top.core0_timer_val[9] ; |
| wire \u_riscv_top.core0_uid[0] ; |
| wire \u_riscv_top.core0_uid[1] ; |
| wire \u_riscv_top.core1_clk ; |
| wire \u_riscv_top.core1_debug[0] ; |
| wire \u_riscv_top.core1_debug[10] ; |
| wire \u_riscv_top.core1_debug[11] ; |
| wire \u_riscv_top.core1_debug[12] ; |
| wire \u_riscv_top.core1_debug[13] ; |
| wire \u_riscv_top.core1_debug[14] ; |
| wire \u_riscv_top.core1_debug[15] ; |
| wire \u_riscv_top.core1_debug[16] ; |
| wire \u_riscv_top.core1_debug[17] ; |
| wire \u_riscv_top.core1_debug[18] ; |
| wire \u_riscv_top.core1_debug[19] ; |
| wire \u_riscv_top.core1_debug[1] ; |
| wire \u_riscv_top.core1_debug[20] ; |
| wire \u_riscv_top.core1_debug[21] ; |
| wire \u_riscv_top.core1_debug[22] ; |
| wire \u_riscv_top.core1_debug[23] ; |
| wire \u_riscv_top.core1_debug[24] ; |
| wire \u_riscv_top.core1_debug[25] ; |
| wire \u_riscv_top.core1_debug[26] ; |
| wire \u_riscv_top.core1_debug[27] ; |
| wire \u_riscv_top.core1_debug[28] ; |
| wire \u_riscv_top.core1_debug[29] ; |
| wire \u_riscv_top.core1_debug[2] ; |
| wire \u_riscv_top.core1_debug[30] ; |
| wire \u_riscv_top.core1_debug[31] ; |
| wire \u_riscv_top.core1_debug[32] ; |
| wire \u_riscv_top.core1_debug[33] ; |
| wire \u_riscv_top.core1_debug[34] ; |
| wire \u_riscv_top.core1_debug[35] ; |
| wire \u_riscv_top.core1_debug[36] ; |
| wire \u_riscv_top.core1_debug[37] ; |
| wire \u_riscv_top.core1_debug[38] ; |
| wire \u_riscv_top.core1_debug[39] ; |
| wire \u_riscv_top.core1_debug[3] ; |
| wire \u_riscv_top.core1_debug[40] ; |
| wire \u_riscv_top.core1_debug[41] ; |
| wire \u_riscv_top.core1_debug[42] ; |
| wire \u_riscv_top.core1_debug[43] ; |
| wire \u_riscv_top.core1_debug[44] ; |
| wire \u_riscv_top.core1_debug[45] ; |
| wire \u_riscv_top.core1_debug[46] ; |
| wire \u_riscv_top.core1_debug[47] ; |
| wire \u_riscv_top.core1_debug[48] ; |
| wire \u_riscv_top.core1_debug[4] ; |
| wire \u_riscv_top.core1_debug[5] ; |
| wire \u_riscv_top.core1_debug[6] ; |
| wire \u_riscv_top.core1_debug[7] ; |
| wire \u_riscv_top.core1_debug[8] ; |
| wire \u_riscv_top.core1_debug[9] ; |
| wire \u_riscv_top.core1_dmem_addr[0] ; |
| wire \u_riscv_top.core1_dmem_addr[10] ; |
| wire \u_riscv_top.core1_dmem_addr[11] ; |
| wire \u_riscv_top.core1_dmem_addr[12] ; |
| wire \u_riscv_top.core1_dmem_addr[13] ; |
| wire \u_riscv_top.core1_dmem_addr[14] ; |
| wire \u_riscv_top.core1_dmem_addr[15] ; |
| wire \u_riscv_top.core1_dmem_addr[16] ; |
| wire \u_riscv_top.core1_dmem_addr[17] ; |
| wire \u_riscv_top.core1_dmem_addr[18] ; |
| wire \u_riscv_top.core1_dmem_addr[19] ; |
| wire \u_riscv_top.core1_dmem_addr[1] ; |
| wire \u_riscv_top.core1_dmem_addr[20] ; |
| wire \u_riscv_top.core1_dmem_addr[21] ; |
| wire \u_riscv_top.core1_dmem_addr[22] ; |
| wire \u_riscv_top.core1_dmem_addr[23] ; |
| wire \u_riscv_top.core1_dmem_addr[24] ; |
| wire \u_riscv_top.core1_dmem_addr[25] ; |
| wire \u_riscv_top.core1_dmem_addr[26] ; |
| wire \u_riscv_top.core1_dmem_addr[27] ; |
| wire \u_riscv_top.core1_dmem_addr[28] ; |
| wire \u_riscv_top.core1_dmem_addr[29] ; |
| wire \u_riscv_top.core1_dmem_addr[2] ; |
| wire \u_riscv_top.core1_dmem_addr[30] ; |
| wire \u_riscv_top.core1_dmem_addr[31] ; |
| wire \u_riscv_top.core1_dmem_addr[3] ; |
| wire \u_riscv_top.core1_dmem_addr[4] ; |
| wire \u_riscv_top.core1_dmem_addr[5] ; |
| wire \u_riscv_top.core1_dmem_addr[6] ; |
| wire \u_riscv_top.core1_dmem_addr[7] ; |
| wire \u_riscv_top.core1_dmem_addr[8] ; |
| wire \u_riscv_top.core1_dmem_addr[9] ; |
| wire \u_riscv_top.core1_dmem_cmd ; |
| wire \u_riscv_top.core1_dmem_rdata[0] ; |
| wire \u_riscv_top.core1_dmem_rdata[10] ; |
| wire \u_riscv_top.core1_dmem_rdata[11] ; |
| wire \u_riscv_top.core1_dmem_rdata[12] ; |
| wire \u_riscv_top.core1_dmem_rdata[13] ; |
| wire \u_riscv_top.core1_dmem_rdata[14] ; |
| wire \u_riscv_top.core1_dmem_rdata[15] ; |
| wire \u_riscv_top.core1_dmem_rdata[16] ; |
| wire \u_riscv_top.core1_dmem_rdata[17] ; |
| wire \u_riscv_top.core1_dmem_rdata[18] ; |
| wire \u_riscv_top.core1_dmem_rdata[19] ; |
| wire \u_riscv_top.core1_dmem_rdata[1] ; |
| wire \u_riscv_top.core1_dmem_rdata[20] ; |
| wire \u_riscv_top.core1_dmem_rdata[21] ; |
| wire \u_riscv_top.core1_dmem_rdata[22] ; |
| wire \u_riscv_top.core1_dmem_rdata[23] ; |
| wire \u_riscv_top.core1_dmem_rdata[24] ; |
| wire \u_riscv_top.core1_dmem_rdata[25] ; |
| wire \u_riscv_top.core1_dmem_rdata[26] ; |
| wire \u_riscv_top.core1_dmem_rdata[27] ; |
| wire \u_riscv_top.core1_dmem_rdata[28] ; |
| wire \u_riscv_top.core1_dmem_rdata[29] ; |
| wire \u_riscv_top.core1_dmem_rdata[2] ; |
| wire \u_riscv_top.core1_dmem_rdata[30] ; |
| wire \u_riscv_top.core1_dmem_rdata[31] ; |
| wire \u_riscv_top.core1_dmem_rdata[3] ; |
| wire \u_riscv_top.core1_dmem_rdata[4] ; |
| wire \u_riscv_top.core1_dmem_rdata[5] ; |
| wire \u_riscv_top.core1_dmem_rdata[6] ; |
| wire \u_riscv_top.core1_dmem_rdata[7] ; |
| wire \u_riscv_top.core1_dmem_rdata[8] ; |
| wire \u_riscv_top.core1_dmem_rdata[9] ; |
| wire \u_riscv_top.core1_dmem_req ; |
| wire \u_riscv_top.core1_dmem_req_ack ; |
| wire \u_riscv_top.core1_dmem_resp[0] ; |
| wire \u_riscv_top.core1_dmem_resp[1] ; |
| wire \u_riscv_top.core1_dmem_wdata[0] ; |
| wire \u_riscv_top.core1_dmem_wdata[10] ; |
| wire \u_riscv_top.core1_dmem_wdata[11] ; |
| wire \u_riscv_top.core1_dmem_wdata[12] ; |
| wire \u_riscv_top.core1_dmem_wdata[13] ; |
| wire \u_riscv_top.core1_dmem_wdata[14] ; |
| wire \u_riscv_top.core1_dmem_wdata[15] ; |
| wire \u_riscv_top.core1_dmem_wdata[16] ; |
| wire \u_riscv_top.core1_dmem_wdata[17] ; |
| wire \u_riscv_top.core1_dmem_wdata[18] ; |
| wire \u_riscv_top.core1_dmem_wdata[19] ; |
| wire \u_riscv_top.core1_dmem_wdata[1] ; |
| wire \u_riscv_top.core1_dmem_wdata[20] ; |
| wire \u_riscv_top.core1_dmem_wdata[21] ; |
| wire \u_riscv_top.core1_dmem_wdata[22] ; |
| wire \u_riscv_top.core1_dmem_wdata[23] ; |
| wire \u_riscv_top.core1_dmem_wdata[24] ; |
| wire \u_riscv_top.core1_dmem_wdata[25] ; |
| wire \u_riscv_top.core1_dmem_wdata[26] ; |
| wire \u_riscv_top.core1_dmem_wdata[27] ; |
| wire \u_riscv_top.core1_dmem_wdata[28] ; |
| wire \u_riscv_top.core1_dmem_wdata[29] ; |
| wire \u_riscv_top.core1_dmem_wdata[2] ; |
| wire \u_riscv_top.core1_dmem_wdata[30] ; |
| wire \u_riscv_top.core1_dmem_wdata[31] ; |
| wire \u_riscv_top.core1_dmem_wdata[3] ; |
| wire \u_riscv_top.core1_dmem_wdata[4] ; |
| wire \u_riscv_top.core1_dmem_wdata[5] ; |
| wire \u_riscv_top.core1_dmem_wdata[6] ; |
| wire \u_riscv_top.core1_dmem_wdata[7] ; |
| wire \u_riscv_top.core1_dmem_wdata[8] ; |
| wire \u_riscv_top.core1_dmem_wdata[9] ; |
| wire \u_riscv_top.core1_dmem_width[0] ; |
| wire \u_riscv_top.core1_dmem_width[1] ; |
| wire \u_riscv_top.core1_imem_addr[0] ; |
| wire \u_riscv_top.core1_imem_addr[10] ; |
| wire \u_riscv_top.core1_imem_addr[11] ; |
| wire \u_riscv_top.core1_imem_addr[12] ; |
| wire \u_riscv_top.core1_imem_addr[13] ; |
| wire \u_riscv_top.core1_imem_addr[14] ; |
| wire \u_riscv_top.core1_imem_addr[15] ; |
| wire \u_riscv_top.core1_imem_addr[16] ; |
| wire \u_riscv_top.core1_imem_addr[17] ; |
| wire \u_riscv_top.core1_imem_addr[18] ; |
| wire \u_riscv_top.core1_imem_addr[19] ; |
| wire \u_riscv_top.core1_imem_addr[1] ; |
| wire \u_riscv_top.core1_imem_addr[20] ; |
| wire \u_riscv_top.core1_imem_addr[21] ; |
| wire \u_riscv_top.core1_imem_addr[22] ; |
| wire \u_riscv_top.core1_imem_addr[23] ; |
| wire \u_riscv_top.core1_imem_addr[24] ; |
| wire \u_riscv_top.core1_imem_addr[25] ; |
| wire \u_riscv_top.core1_imem_addr[26] ; |
| wire \u_riscv_top.core1_imem_addr[27] ; |
| wire \u_riscv_top.core1_imem_addr[28] ; |
| wire \u_riscv_top.core1_imem_addr[29] ; |
| wire \u_riscv_top.core1_imem_addr[2] ; |
| wire \u_riscv_top.core1_imem_addr[30] ; |
| wire \u_riscv_top.core1_imem_addr[31] ; |
| wire \u_riscv_top.core1_imem_addr[3] ; |
| wire \u_riscv_top.core1_imem_addr[4] ; |
| wire \u_riscv_top.core1_imem_addr[5] ; |
| wire \u_riscv_top.core1_imem_addr[6] ; |
| wire \u_riscv_top.core1_imem_addr[7] ; |
| wire \u_riscv_top.core1_imem_addr[8] ; |
| wire \u_riscv_top.core1_imem_addr[9] ; |
| wire \u_riscv_top.core1_imem_bl[0] ; |
| wire \u_riscv_top.core1_imem_bl[1] ; |
| wire \u_riscv_top.core1_imem_bl[2] ; |
| wire \u_riscv_top.core1_imem_cmd ; |
| wire \u_riscv_top.core1_imem_rdata[0] ; |
| wire \u_riscv_top.core1_imem_rdata[10] ; |
| wire \u_riscv_top.core1_imem_rdata[11] ; |
| wire \u_riscv_top.core1_imem_rdata[12] ; |
| wire \u_riscv_top.core1_imem_rdata[13] ; |
| wire \u_riscv_top.core1_imem_rdata[14] ; |
| wire \u_riscv_top.core1_imem_rdata[15] ; |
| wire \u_riscv_top.core1_imem_rdata[16] ; |
| wire \u_riscv_top.core1_imem_rdata[17] ; |
| wire \u_riscv_top.core1_imem_rdata[18] ; |
| wire \u_riscv_top.core1_imem_rdata[19] ; |
| wire \u_riscv_top.core1_imem_rdata[1] ; |
| wire \u_riscv_top.core1_imem_rdata[20] ; |
| wire \u_riscv_top.core1_imem_rdata[21] ; |
| wire \u_riscv_top.core1_imem_rdata[22] ; |
| wire \u_riscv_top.core1_imem_rdata[23] ; |
| wire \u_riscv_top.core1_imem_rdata[24] ; |
| wire \u_riscv_top.core1_imem_rdata[25] ; |
| wire \u_riscv_top.core1_imem_rdata[26] ; |
| wire \u_riscv_top.core1_imem_rdata[27] ; |
| wire \u_riscv_top.core1_imem_rdata[28] ; |
| wire \u_riscv_top.core1_imem_rdata[29] ; |
| wire \u_riscv_top.core1_imem_rdata[2] ; |
| wire \u_riscv_top.core1_imem_rdata[30] ; |
| wire \u_riscv_top.core1_imem_rdata[31] ; |
| wire \u_riscv_top.core1_imem_rdata[3] ; |
| wire \u_riscv_top.core1_imem_rdata[4] ; |
| wire \u_riscv_top.core1_imem_rdata[5] ; |
| wire \u_riscv_top.core1_imem_rdata[6] ; |
| wire \u_riscv_top.core1_imem_rdata[7] ; |
| wire \u_riscv_top.core1_imem_rdata[8] ; |
| wire \u_riscv_top.core1_imem_rdata[9] ; |
| wire \u_riscv_top.core1_imem_req ; |
| wire \u_riscv_top.core1_imem_req_ack ; |
| wire \u_riscv_top.core1_imem_resp[0] ; |
| wire \u_riscv_top.core1_imem_resp[1] ; |
| wire \u_riscv_top.core1_irq_lines[0] ; |
| wire \u_riscv_top.core1_irq_lines[10] ; |
| wire \u_riscv_top.core1_irq_lines[11] ; |
| wire \u_riscv_top.core1_irq_lines[12] ; |
| wire \u_riscv_top.core1_irq_lines[13] ; |
| wire \u_riscv_top.core1_irq_lines[14] ; |
| wire \u_riscv_top.core1_irq_lines[15] ; |
| wire \u_riscv_top.core1_irq_lines[16] ; |
| wire \u_riscv_top.core1_irq_lines[17] ; |
| wire \u_riscv_top.core1_irq_lines[18] ; |
| wire \u_riscv_top.core1_irq_lines[19] ; |
| wire \u_riscv_top.core1_irq_lines[1] ; |
| wire \u_riscv_top.core1_irq_lines[20] ; |
| wire \u_riscv_top.core1_irq_lines[21] ; |
| wire \u_riscv_top.core1_irq_lines[22] ; |
| wire \u_riscv_top.core1_irq_lines[23] ; |
| wire \u_riscv_top.core1_irq_lines[24] ; |
| wire \u_riscv_top.core1_irq_lines[25] ; |
| wire \u_riscv_top.core1_irq_lines[26] ; |
| wire \u_riscv_top.core1_irq_lines[27] ; |
| wire \u_riscv_top.core1_irq_lines[28] ; |
| wire \u_riscv_top.core1_irq_lines[29] ; |
| wire \u_riscv_top.core1_irq_lines[2] ; |
| wire \u_riscv_top.core1_irq_lines[30] ; |
| wire \u_riscv_top.core1_irq_lines[31] ; |
| wire \u_riscv_top.core1_irq_lines[3] ; |
| wire \u_riscv_top.core1_irq_lines[4] ; |
| wire \u_riscv_top.core1_irq_lines[5] ; |
| wire \u_riscv_top.core1_irq_lines[6] ; |
| wire \u_riscv_top.core1_irq_lines[7] ; |
| wire \u_riscv_top.core1_irq_lines[8] ; |
| wire \u_riscv_top.core1_irq_lines[9] ; |
| wire \u_riscv_top.core1_soft_irq ; |
| wire \u_riscv_top.core1_timer_irq ; |
| wire \u_riscv_top.core1_timer_val[0] ; |
| wire \u_riscv_top.core1_timer_val[10] ; |
| wire \u_riscv_top.core1_timer_val[11] ; |
| wire \u_riscv_top.core1_timer_val[12] ; |
| wire \u_riscv_top.core1_timer_val[13] ; |
| wire \u_riscv_top.core1_timer_val[14] ; |
| wire \u_riscv_top.core1_timer_val[15] ; |
| wire \u_riscv_top.core1_timer_val[16] ; |
| wire \u_riscv_top.core1_timer_val[17] ; |
| wire \u_riscv_top.core1_timer_val[18] ; |
| wire \u_riscv_top.core1_timer_val[19] ; |
| wire \u_riscv_top.core1_timer_val[1] ; |
| wire \u_riscv_top.core1_timer_val[20] ; |
| wire \u_riscv_top.core1_timer_val[21] ; |
| wire \u_riscv_top.core1_timer_val[22] ; |
| wire \u_riscv_top.core1_timer_val[23] ; |
| wire \u_riscv_top.core1_timer_val[24] ; |
| wire \u_riscv_top.core1_timer_val[25] ; |
| wire \u_riscv_top.core1_timer_val[26] ; |
| wire \u_riscv_top.core1_timer_val[27] ; |
| wire \u_riscv_top.core1_timer_val[28] ; |
| wire \u_riscv_top.core1_timer_val[29] ; |
| wire \u_riscv_top.core1_timer_val[2] ; |
| wire \u_riscv_top.core1_timer_val[30] ; |
| wire \u_riscv_top.core1_timer_val[31] ; |
| wire \u_riscv_top.core1_timer_val[32] ; |
| wire \u_riscv_top.core1_timer_val[33] ; |
| wire \u_riscv_top.core1_timer_val[34] ; |
| wire \u_riscv_top.core1_timer_val[35] ; |
| wire \u_riscv_top.core1_timer_val[36] ; |
| wire \u_riscv_top.core1_timer_val[37] ; |
| wire \u_riscv_top.core1_timer_val[38] ; |
| wire \u_riscv_top.core1_timer_val[39] ; |
| wire \u_riscv_top.core1_timer_val[3] ; |
| wire \u_riscv_top.core1_timer_val[40] ; |
| wire \u_riscv_top.core1_timer_val[41] ; |
| wire \u_riscv_top.core1_timer_val[42] ; |
| wire \u_riscv_top.core1_timer_val[43] ; |
| wire \u_riscv_top.core1_timer_val[44] ; |
| wire \u_riscv_top.core1_timer_val[45] ; |
| wire \u_riscv_top.core1_timer_val[46] ; |
| wire \u_riscv_top.core1_timer_val[47] ; |
| wire \u_riscv_top.core1_timer_val[48] ; |
| wire \u_riscv_top.core1_timer_val[49] ; |
| wire \u_riscv_top.core1_timer_val[4] ; |
| wire \u_riscv_top.core1_timer_val[50] ; |
| wire \u_riscv_top.core1_timer_val[51] ; |
| wire \u_riscv_top.core1_timer_val[52] ; |
| wire \u_riscv_top.core1_timer_val[53] ; |
| wire \u_riscv_top.core1_timer_val[54] ; |
| wire \u_riscv_top.core1_timer_val[55] ; |
| wire \u_riscv_top.core1_timer_val[56] ; |
| wire \u_riscv_top.core1_timer_val[57] ; |
| wire \u_riscv_top.core1_timer_val[58] ; |
| wire \u_riscv_top.core1_timer_val[59] ; |
| wire \u_riscv_top.core1_timer_val[5] ; |
| wire \u_riscv_top.core1_timer_val[60] ; |
| wire \u_riscv_top.core1_timer_val[61] ; |
| wire \u_riscv_top.core1_timer_val[62] ; |
| wire \u_riscv_top.core1_timer_val[63] ; |
| wire \u_riscv_top.core1_timer_val[6] ; |
| wire \u_riscv_top.core1_timer_val[7] ; |
| wire \u_riscv_top.core1_timer_val[8] ; |
| wire \u_riscv_top.core1_timer_val[9] ; |
| wire \u_riscv_top.core1_uid[0] ; |
| wire \u_riscv_top.core1_uid[1] ; |
| wire \u_riscv_top.core_clk_core0_skew ; |
| wire \u_riscv_top.core_clk_core1_skew ; |
| wire \u_riscv_top.core_clk_icon_skew ; |
| wire \u_riscv_top.core_clk_int[0] ; |
| wire \u_riscv_top.core_clk_int[1] ; |
| wire \u_riscv_top.core_clk_intf_skew ; |
| wire \u_riscv_top.core_clk_out[0] ; |
| wire \u_riscv_top.core_clk_out[1] ; |
| wire \u_riscv_top.core_dcache_addr[0] ; |
| wire \u_riscv_top.core_dcache_addr[10] ; |
| wire \u_riscv_top.core_dcache_addr[11] ; |
| wire \u_riscv_top.core_dcache_addr[12] ; |
| wire \u_riscv_top.core_dcache_addr[13] ; |
| wire \u_riscv_top.core_dcache_addr[14] ; |
| wire \u_riscv_top.core_dcache_addr[15] ; |
| wire \u_riscv_top.core_dcache_addr[16] ; |
| wire \u_riscv_top.core_dcache_addr[17] ; |
| wire \u_riscv_top.core_dcache_addr[18] ; |
| wire \u_riscv_top.core_dcache_addr[19] ; |
| wire \u_riscv_top.core_dcache_addr[1] ; |
| wire \u_riscv_top.core_dcache_addr[20] ; |
| wire \u_riscv_top.core_dcache_addr[21] ; |
| wire \u_riscv_top.core_dcache_addr[22] ; |
| wire \u_riscv_top.core_dcache_addr[23] ; |
| wire \u_riscv_top.core_dcache_addr[24] ; |
| wire \u_riscv_top.core_dcache_addr[25] ; |
| wire \u_riscv_top.core_dcache_addr[26] ; |
| wire \u_riscv_top.core_dcache_addr[27] ; |
| wire \u_riscv_top.core_dcache_addr[28] ; |
| wire \u_riscv_top.core_dcache_addr[29] ; |
| wire \u_riscv_top.core_dcache_addr[2] ; |
| wire \u_riscv_top.core_dcache_addr[30] ; |
| wire \u_riscv_top.core_dcache_addr[31] ; |
| wire \u_riscv_top.core_dcache_addr[3] ; |
| wire \u_riscv_top.core_dcache_addr[4] ; |
| wire \u_riscv_top.core_dcache_addr[5] ; |
| wire \u_riscv_top.core_dcache_addr[6] ; |
| wire \u_riscv_top.core_dcache_addr[7] ; |
| wire \u_riscv_top.core_dcache_addr[8] ; |
| wire \u_riscv_top.core_dcache_addr[9] ; |
| wire \u_riscv_top.core_dcache_cmd ; |
| wire \u_riscv_top.core_dcache_rdata[0] ; |
| wire \u_riscv_top.core_dcache_rdata[10] ; |
| wire \u_riscv_top.core_dcache_rdata[11] ; |
| wire \u_riscv_top.core_dcache_rdata[12] ; |
| wire \u_riscv_top.core_dcache_rdata[13] ; |
| wire \u_riscv_top.core_dcache_rdata[14] ; |
| wire \u_riscv_top.core_dcache_rdata[15] ; |
| wire \u_riscv_top.core_dcache_rdata[16] ; |
| wire \u_riscv_top.core_dcache_rdata[17] ; |
| wire \u_riscv_top.core_dcache_rdata[18] ; |
| wire \u_riscv_top.core_dcache_rdata[19] ; |
| wire \u_riscv_top.core_dcache_rdata[1] ; |
| wire \u_riscv_top.core_dcache_rdata[20] ; |
| wire \u_riscv_top.core_dcache_rdata[21] ; |
| wire \u_riscv_top.core_dcache_rdata[22] ; |
| wire \u_riscv_top.core_dcache_rdata[23] ; |
| wire \u_riscv_top.core_dcache_rdata[24] ; |
| wire \u_riscv_top.core_dcache_rdata[25] ; |
| wire \u_riscv_top.core_dcache_rdata[26] ; |
| wire \u_riscv_top.core_dcache_rdata[27] ; |
| wire \u_riscv_top.core_dcache_rdata[28] ; |
| wire \u_riscv_top.core_dcache_rdata[29] ; |
| wire \u_riscv_top.core_dcache_rdata[2] ; |
| wire \u_riscv_top.core_dcache_rdata[30] ; |
| wire \u_riscv_top.core_dcache_rdata[31] ; |
| wire \u_riscv_top.core_dcache_rdata[3] ; |
| wire \u_riscv_top.core_dcache_rdata[4] ; |
| wire \u_riscv_top.core_dcache_rdata[5] ; |
| wire \u_riscv_top.core_dcache_rdata[6] ; |
| wire \u_riscv_top.core_dcache_rdata[7] ; |
| wire \u_riscv_top.core_dcache_rdata[8] ; |
| wire \u_riscv_top.core_dcache_rdata[9] ; |
| wire \u_riscv_top.core_dcache_req ; |
| wire \u_riscv_top.core_dcache_req_ack ; |
| wire \u_riscv_top.core_dcache_resp[0] ; |
| wire \u_riscv_top.core_dcache_resp[1] ; |
| wire \u_riscv_top.core_dcache_wdata[0] ; |
| wire \u_riscv_top.core_dcache_wdata[10] ; |
| wire \u_riscv_top.core_dcache_wdata[11] ; |
| wire \u_riscv_top.core_dcache_wdata[12] ; |
| wire \u_riscv_top.core_dcache_wdata[13] ; |
| wire \u_riscv_top.core_dcache_wdata[14] ; |
| wire \u_riscv_top.core_dcache_wdata[15] ; |
| wire \u_riscv_top.core_dcache_wdata[16] ; |
| wire \u_riscv_top.core_dcache_wdata[17] ; |
| wire \u_riscv_top.core_dcache_wdata[18] ; |
| wire \u_riscv_top.core_dcache_wdata[19] ; |
| wire \u_riscv_top.core_dcache_wdata[1] ; |
| wire \u_riscv_top.core_dcache_wdata[20] ; |
| wire \u_riscv_top.core_dcache_wdata[21] ; |
| wire \u_riscv_top.core_dcache_wdata[22] ; |
| wire \u_riscv_top.core_dcache_wdata[23] ; |
| wire \u_riscv_top.core_dcache_wdata[24] ; |
| wire \u_riscv_top.core_dcache_wdata[25] ; |
| wire \u_riscv_top.core_dcache_wdata[26] ; |
| wire \u_riscv_top.core_dcache_wdata[27] ; |
| wire \u_riscv_top.core_dcache_wdata[28] ; |
| wire \u_riscv_top.core_dcache_wdata[29] ; |
| wire \u_riscv_top.core_dcache_wdata[2] ; |
| wire \u_riscv_top.core_dcache_wdata[30] ; |
| wire \u_riscv_top.core_dcache_wdata[31] ; |
| wire \u_riscv_top.core_dcache_wdata[3] ; |
| wire \u_riscv_top.core_dcache_wdata[4] ; |
| wire \u_riscv_top.core_dcache_wdata[5] ; |
| wire \u_riscv_top.core_dcache_wdata[6] ; |
| wire \u_riscv_top.core_dcache_wdata[7] ; |
| wire \u_riscv_top.core_dcache_wdata[8] ; |
| wire \u_riscv_top.core_dcache_wdata[9] ; |
| wire \u_riscv_top.core_dcache_width[0] ; |
| wire \u_riscv_top.core_dcache_width[1] ; |
| wire \u_riscv_top.core_dmem_addr[0] ; |
| wire \u_riscv_top.core_dmem_addr[10] ; |
| wire \u_riscv_top.core_dmem_addr[11] ; |
| wire \u_riscv_top.core_dmem_addr[12] ; |
| wire \u_riscv_top.core_dmem_addr[13] ; |
| wire \u_riscv_top.core_dmem_addr[14] ; |
| wire \u_riscv_top.core_dmem_addr[15] ; |
| wire \u_riscv_top.core_dmem_addr[16] ; |
| wire \u_riscv_top.core_dmem_addr[17] ; |
| wire \u_riscv_top.core_dmem_addr[18] ; |
| wire \u_riscv_top.core_dmem_addr[19] ; |
| wire \u_riscv_top.core_dmem_addr[1] ; |
| wire \u_riscv_top.core_dmem_addr[20] ; |
| wire \u_riscv_top.core_dmem_addr[21] ; |
| wire \u_riscv_top.core_dmem_addr[22] ; |
| wire \u_riscv_top.core_dmem_addr[23] ; |
| wire \u_riscv_top.core_dmem_addr[24] ; |
| wire \u_riscv_top.core_dmem_addr[25] ; |
| wire \u_riscv_top.core_dmem_addr[26] ; |
| wire \u_riscv_top.core_dmem_addr[27] ; |
| wire \u_riscv_top.core_dmem_addr[28] ; |
| wire \u_riscv_top.core_dmem_addr[29] ; |
| wire \u_riscv_top.core_dmem_addr[2] ; |
| wire \u_riscv_top.core_dmem_addr[30] ; |
| wire \u_riscv_top.core_dmem_addr[31] ; |
| wire \u_riscv_top.core_dmem_addr[3] ; |
| wire \u_riscv_top.core_dmem_addr[4] ; |
| wire \u_riscv_top.core_dmem_addr[5] ; |
| wire \u_riscv_top.core_dmem_addr[6] ; |
| wire \u_riscv_top.core_dmem_addr[7] ; |
| wire \u_riscv_top.core_dmem_addr[8] ; |
| wire \u_riscv_top.core_dmem_addr[9] ; |
| wire \u_riscv_top.core_dmem_bl[0] ; |
| wire \u_riscv_top.core_dmem_bl[1] ; |
| wire \u_riscv_top.core_dmem_bl[2] ; |
| wire \u_riscv_top.core_dmem_cmd ; |
| wire \u_riscv_top.core_dmem_rdata[0] ; |
| wire \u_riscv_top.core_dmem_rdata[10] ; |
| wire \u_riscv_top.core_dmem_rdata[11] ; |
| wire \u_riscv_top.core_dmem_rdata[12] ; |
| wire \u_riscv_top.core_dmem_rdata[13] ; |
| wire \u_riscv_top.core_dmem_rdata[14] ; |
| wire \u_riscv_top.core_dmem_rdata[15] ; |
| wire \u_riscv_top.core_dmem_rdata[16] ; |
| wire \u_riscv_top.core_dmem_rdata[17] ; |
| wire \u_riscv_top.core_dmem_rdata[18] ; |
| wire \u_riscv_top.core_dmem_rdata[19] ; |
| wire \u_riscv_top.core_dmem_rdata[1] ; |
| wire \u_riscv_top.core_dmem_rdata[20] ; |
| wire \u_riscv_top.core_dmem_rdata[21] ; |
| wire \u_riscv_top.core_dmem_rdata[22] ; |
| wire \u_riscv_top.core_dmem_rdata[23] ; |
| wire \u_riscv_top.core_dmem_rdata[24] ; |
| wire \u_riscv_top.core_dmem_rdata[25] ; |
| wire \u_riscv_top.core_dmem_rdata[26] ; |
| wire \u_riscv_top.core_dmem_rdata[27] ; |
| wire \u_riscv_top.core_dmem_rdata[28] ; |
| wire \u_riscv_top.core_dmem_rdata[29] ; |
| wire \u_riscv_top.core_dmem_rdata[2] ; |
| wire \u_riscv_top.core_dmem_rdata[30] ; |
| wire \u_riscv_top.core_dmem_rdata[31] ; |
| wire \u_riscv_top.core_dmem_rdata[3] ; |
| wire \u_riscv_top.core_dmem_rdata[4] ; |
| wire \u_riscv_top.core_dmem_rdata[5] ; |
| wire \u_riscv_top.core_dmem_rdata[6] ; |
| wire \u_riscv_top.core_dmem_rdata[7] ; |
| wire \u_riscv_top.core_dmem_rdata[8] ; |
| wire \u_riscv_top.core_dmem_rdata[9] ; |
| wire \u_riscv_top.core_dmem_req ; |
| wire \u_riscv_top.core_dmem_req_ack ; |
| wire \u_riscv_top.core_dmem_resp[0] ; |
| wire \u_riscv_top.core_dmem_resp[1] ; |
| wire \u_riscv_top.core_dmem_wdata[0] ; |
| wire \u_riscv_top.core_dmem_wdata[10] ; |
| wire \u_riscv_top.core_dmem_wdata[11] ; |
| wire \u_riscv_top.core_dmem_wdata[12] ; |
| wire \u_riscv_top.core_dmem_wdata[13] ; |
| wire \u_riscv_top.core_dmem_wdata[14] ; |
| wire \u_riscv_top.core_dmem_wdata[15] ; |
| wire \u_riscv_top.core_dmem_wdata[16] ; |
| wire \u_riscv_top.core_dmem_wdata[17] ; |
| wire \u_riscv_top.core_dmem_wdata[18] ; |
| wire \u_riscv_top.core_dmem_wdata[19] ; |
| wire \u_riscv_top.core_dmem_wdata[1] ; |
| wire \u_riscv_top.core_dmem_wdata[20] ; |
| wire \u_riscv_top.core_dmem_wdata[21] ; |
| wire \u_riscv_top.core_dmem_wdata[22] ; |
| wire \u_riscv_top.core_dmem_wdata[23] ; |
| wire \u_riscv_top.core_dmem_wdata[24] ; |
| wire \u_riscv_top.core_dmem_wdata[25] ; |
| wire \u_riscv_top.core_dmem_wdata[26] ; |
| wire \u_riscv_top.core_dmem_wdata[27] ; |
| wire \u_riscv_top.core_dmem_wdata[28] ; |
| wire \u_riscv_top.core_dmem_wdata[29] ; |
| wire \u_riscv_top.core_dmem_wdata[2] ; |
| wire \u_riscv_top.core_dmem_wdata[30] ; |
| wire \u_riscv_top.core_dmem_wdata[31] ; |
| wire \u_riscv_top.core_dmem_wdata[3] ; |
| wire \u_riscv_top.core_dmem_wdata[4] ; |
| wire \u_riscv_top.core_dmem_wdata[5] ; |
| wire \u_riscv_top.core_dmem_wdata[6] ; |
| wire \u_riscv_top.core_dmem_wdata[7] ; |
| wire \u_riscv_top.core_dmem_wdata[8] ; |
| wire \u_riscv_top.core_dmem_wdata[9] ; |
| wire \u_riscv_top.core_dmem_width[0] ; |
| wire \u_riscv_top.core_dmem_width[1] ; |
| wire \u_riscv_top.core_icache_addr[0] ; |
| wire \u_riscv_top.core_icache_addr[10] ; |
| wire \u_riscv_top.core_icache_addr[11] ; |
| wire \u_riscv_top.core_icache_addr[12] ; |
| wire \u_riscv_top.core_icache_addr[13] ; |
| wire \u_riscv_top.core_icache_addr[14] ; |
| wire \u_riscv_top.core_icache_addr[15] ; |
| wire \u_riscv_top.core_icache_addr[16] ; |
| wire \u_riscv_top.core_icache_addr[17] ; |
| wire \u_riscv_top.core_icache_addr[18] ; |
| wire \u_riscv_top.core_icache_addr[19] ; |
| wire \u_riscv_top.core_icache_addr[1] ; |
| wire \u_riscv_top.core_icache_addr[20] ; |
| wire \u_riscv_top.core_icache_addr[21] ; |
| wire \u_riscv_top.core_icache_addr[22] ; |
| wire \u_riscv_top.core_icache_addr[23] ; |
| wire \u_riscv_top.core_icache_addr[24] ; |
| wire \u_riscv_top.core_icache_addr[25] ; |
| wire \u_riscv_top.core_icache_addr[26] ; |
| wire \u_riscv_top.core_icache_addr[27] ; |
| wire \u_riscv_top.core_icache_addr[28] ; |
| wire \u_riscv_top.core_icache_addr[29] ; |
| wire \u_riscv_top.core_icache_addr[2] ; |
| wire \u_riscv_top.core_icache_addr[30] ; |
| wire \u_riscv_top.core_icache_addr[31] ; |
| wire \u_riscv_top.core_icache_addr[3] ; |
| wire \u_riscv_top.core_icache_addr[4] ; |
| wire \u_riscv_top.core_icache_addr[5] ; |
| wire \u_riscv_top.core_icache_addr[6] ; |
| wire \u_riscv_top.core_icache_addr[7] ; |
| wire \u_riscv_top.core_icache_addr[8] ; |
| wire \u_riscv_top.core_icache_addr[9] ; |
| wire \u_riscv_top.core_icache_bl[0] ; |
| wire \u_riscv_top.core_icache_bl[1] ; |
| wire \u_riscv_top.core_icache_bl[2] ; |
| wire \u_riscv_top.core_icache_cmd ; |
| wire \u_riscv_top.core_icache_rdata[0] ; |
| wire \u_riscv_top.core_icache_rdata[10] ; |
| wire \u_riscv_top.core_icache_rdata[11] ; |
| wire \u_riscv_top.core_icache_rdata[12] ; |
| wire \u_riscv_top.core_icache_rdata[13] ; |
| wire \u_riscv_top.core_icache_rdata[14] ; |
| wire \u_riscv_top.core_icache_rdata[15] ; |
| wire \u_riscv_top.core_icache_rdata[16] ; |
| wire \u_riscv_top.core_icache_rdata[17] ; |
| wire \u_riscv_top.core_icache_rdata[18] ; |
| wire \u_riscv_top.core_icache_rdata[19] ; |
| wire \u_riscv_top.core_icache_rdata[1] ; |
| wire \u_riscv_top.core_icache_rdata[20] ; |
| wire \u_riscv_top.core_icache_rdata[21] ; |
| wire \u_riscv_top.core_icache_rdata[22] ; |
| wire \u_riscv_top.core_icache_rdata[23] ; |
| wire \u_riscv_top.core_icache_rdata[24] ; |
| wire \u_riscv_top.core_icache_rdata[25] ; |
| wire \u_riscv_top.core_icache_rdata[26] ; |
| wire \u_riscv_top.core_icache_rdata[27] ; |
| wire \u_riscv_top.core_icache_rdata[28] ; |
| wire \u_riscv_top.core_icache_rdata[29] ; |
| wire \u_riscv_top.core_icache_rdata[2] ; |
| wire \u_riscv_top.core_icache_rdata[30] ; |
| wire \u_riscv_top.core_icache_rdata[31] ; |
| wire \u_riscv_top.core_icache_rdata[3] ; |
| wire \u_riscv_top.core_icache_rdata[4] ; |
| wire \u_riscv_top.core_icache_rdata[5] ; |
| wire \u_riscv_top.core_icache_rdata[6] ; |
| wire \u_riscv_top.core_icache_rdata[7] ; |
| wire \u_riscv_top.core_icache_rdata[8] ; |
| wire \u_riscv_top.core_icache_rdata[9] ; |
| wire \u_riscv_top.core_icache_req ; |
| wire \u_riscv_top.core_icache_req_ack ; |
| wire \u_riscv_top.core_icache_resp[0] ; |
| wire \u_riscv_top.core_icache_resp[1] ; |
| wire \u_riscv_top.core_icache_width[0] ; |
| wire \u_riscv_top.core_icache_width[1] ; |
| wire \u_riscv_top.cpu_clk_aes ; |
| wire \u_riscv_top.cpu_clk_fpu ; |
| wire \u_riscv_top.cpu_intf_rst_n ; |
| wire \u_riscv_top.dcache_mem_addr0[0] ; |
| wire \u_riscv_top.dcache_mem_addr0[1] ; |
| wire \u_riscv_top.dcache_mem_addr0[2] ; |
| wire \u_riscv_top.dcache_mem_addr0[3] ; |
| wire \u_riscv_top.dcache_mem_addr0[4] ; |
| wire \u_riscv_top.dcache_mem_addr0[5] ; |
| wire \u_riscv_top.dcache_mem_addr0[6] ; |
| wire \u_riscv_top.dcache_mem_addr0[7] ; |
| wire \u_riscv_top.dcache_mem_addr0[8] ; |
| wire \u_riscv_top.dcache_mem_addr1[0] ; |
| wire \u_riscv_top.dcache_mem_addr1[1] ; |
| wire \u_riscv_top.dcache_mem_addr1[2] ; |
| wire \u_riscv_top.dcache_mem_addr1[3] ; |
| wire \u_riscv_top.dcache_mem_addr1[4] ; |
| wire \u_riscv_top.dcache_mem_addr1[5] ; |
| wire \u_riscv_top.dcache_mem_addr1[6] ; |
| wire \u_riscv_top.dcache_mem_addr1[7] ; |
| wire \u_riscv_top.dcache_mem_addr1[8] ; |
| wire \u_riscv_top.dcache_mem_clk0 ; |
| wire \u_riscv_top.dcache_mem_clk1 ; |
| wire \u_riscv_top.dcache_mem_csb0 ; |
| wire \u_riscv_top.dcache_mem_csb1 ; |
| wire \u_riscv_top.dcache_mem_din0[0] ; |
| wire \u_riscv_top.dcache_mem_din0[10] ; |
| wire \u_riscv_top.dcache_mem_din0[11] ; |
| wire \u_riscv_top.dcache_mem_din0[12] ; |
| wire \u_riscv_top.dcache_mem_din0[13] ; |
| wire \u_riscv_top.dcache_mem_din0[14] ; |
| wire \u_riscv_top.dcache_mem_din0[15] ; |
| wire \u_riscv_top.dcache_mem_din0[16] ; |
| wire \u_riscv_top.dcache_mem_din0[17] ; |
| wire \u_riscv_top.dcache_mem_din0[18] ; |
| wire \u_riscv_top.dcache_mem_din0[19] ; |
| wire \u_riscv_top.dcache_mem_din0[1] ; |
| wire \u_riscv_top.dcache_mem_din0[20] ; |
| wire \u_riscv_top.dcache_mem_din0[21] ; |
| wire \u_riscv_top.dcache_mem_din0[22] ; |
| wire \u_riscv_top.dcache_mem_din0[23] ; |
| wire \u_riscv_top.dcache_mem_din0[24] ; |
| wire \u_riscv_top.dcache_mem_din0[25] ; |
| wire \u_riscv_top.dcache_mem_din0[26] ; |
| wire \u_riscv_top.dcache_mem_din0[27] ; |
| wire \u_riscv_top.dcache_mem_din0[28] ; |
| wire \u_riscv_top.dcache_mem_din0[29] ; |
| wire \u_riscv_top.dcache_mem_din0[2] ; |
| wire \u_riscv_top.dcache_mem_din0[30] ; |
| wire \u_riscv_top.dcache_mem_din0[31] ; |
| wire \u_riscv_top.dcache_mem_din0[3] ; |
| wire \u_riscv_top.dcache_mem_din0[4] ; |
| wire \u_riscv_top.dcache_mem_din0[5] ; |
| wire \u_riscv_top.dcache_mem_din0[6] ; |
| wire \u_riscv_top.dcache_mem_din0[7] ; |
| wire \u_riscv_top.dcache_mem_din0[8] ; |
| wire \u_riscv_top.dcache_mem_din0[9] ; |
| wire \u_riscv_top.dcache_mem_dout0[0] ; |
| wire \u_riscv_top.dcache_mem_dout0[10] ; |
| wire \u_riscv_top.dcache_mem_dout0[11] ; |
| wire \u_riscv_top.dcache_mem_dout0[12] ; |
| wire \u_riscv_top.dcache_mem_dout0[13] ; |
| wire \u_riscv_top.dcache_mem_dout0[14] ; |
| wire \u_riscv_top.dcache_mem_dout0[15] ; |
| wire \u_riscv_top.dcache_mem_dout0[16] ; |
| wire \u_riscv_top.dcache_mem_dout0[17] ; |
| wire \u_riscv_top.dcache_mem_dout0[18] ; |
| wire \u_riscv_top.dcache_mem_dout0[19] ; |
| wire \u_riscv_top.dcache_mem_dout0[1] ; |
| wire \u_riscv_top.dcache_mem_dout0[20] ; |
| wire \u_riscv_top.dcache_mem_dout0[21] ; |
| wire \u_riscv_top.dcache_mem_dout0[22] ; |
| wire \u_riscv_top.dcache_mem_dout0[23] ; |
| wire \u_riscv_top.dcache_mem_dout0[24] ; |
| wire \u_riscv_top.dcache_mem_dout0[25] ; |
| wire \u_riscv_top.dcache_mem_dout0[26] ; |
| wire \u_riscv_top.dcache_mem_dout0[27] ; |
| wire \u_riscv_top.dcache_mem_dout0[28] ; |
| wire \u_riscv_top.dcache_mem_dout0[29] ; |
| wire \u_riscv_top.dcache_mem_dout0[2] ; |
| wire \u_riscv_top.dcache_mem_dout0[30] ; |
| wire \u_riscv_top.dcache_mem_dout0[31] ; |
| wire \u_riscv_top.dcache_mem_dout0[3] ; |
| wire \u_riscv_top.dcache_mem_dout0[4] ; |
| wire \u_riscv_top.dcache_mem_dout0[5] ; |
| wire \u_riscv_top.dcache_mem_dout0[6] ; |
| wire \u_riscv_top.dcache_mem_dout0[7] ; |
| wire \u_riscv_top.dcache_mem_dout0[8] ; |
| wire \u_riscv_top.dcache_mem_dout0[9] ; |
| wire \u_riscv_top.dcache_mem_dout1[0] ; |
| wire \u_riscv_top.dcache_mem_dout1[10] ; |
| wire \u_riscv_top.dcache_mem_dout1[11] ; |
| wire \u_riscv_top.dcache_mem_dout1[12] ; |
| wire \u_riscv_top.dcache_mem_dout1[13] ; |
| wire \u_riscv_top.dcache_mem_dout1[14] ; |
| wire \u_riscv_top.dcache_mem_dout1[15] ; |
| wire \u_riscv_top.dcache_mem_dout1[16] ; |
| wire \u_riscv_top.dcache_mem_dout1[17] ; |
| wire \u_riscv_top.dcache_mem_dout1[18] ; |
| wire \u_riscv_top.dcache_mem_dout1[19] ; |
| wire \u_riscv_top.dcache_mem_dout1[1] ; |
| wire \u_riscv_top.dcache_mem_dout1[20] ; |
| wire \u_riscv_top.dcache_mem_dout1[21] ; |
| wire \u_riscv_top.dcache_mem_dout1[22] ; |
| wire \u_riscv_top.dcache_mem_dout1[23] ; |
| wire \u_riscv_top.dcache_mem_dout1[24] ; |
| wire \u_riscv_top.dcache_mem_dout1[25] ; |
| wire \u_riscv_top.dcache_mem_dout1[26] ; |
| wire \u_riscv_top.dcache_mem_dout1[27] ; |
| wire \u_riscv_top.dcache_mem_dout1[28] ; |
| wire \u_riscv_top.dcache_mem_dout1[29] ; |
| wire \u_riscv_top.dcache_mem_dout1[2] ; |
| wire \u_riscv_top.dcache_mem_dout1[30] ; |
| wire \u_riscv_top.dcache_mem_dout1[31] ; |
| wire \u_riscv_top.dcache_mem_dout1[3] ; |
| wire \u_riscv_top.dcache_mem_dout1[4] ; |
| wire \u_riscv_top.dcache_mem_dout1[5] ; |
| wire \u_riscv_top.dcache_mem_dout1[6] ; |
| wire \u_riscv_top.dcache_mem_dout1[7] ; |
| wire \u_riscv_top.dcache_mem_dout1[8] ; |
| wire \u_riscv_top.dcache_mem_dout1[9] ; |
| wire \u_riscv_top.dcache_mem_web0 ; |
| wire \u_riscv_top.dcache_mem_wmask0[0] ; |
| wire \u_riscv_top.dcache_mem_wmask0[1] ; |
| wire \u_riscv_top.dcache_mem_wmask0[2] ; |
| wire \u_riscv_top.dcache_mem_wmask0[3] ; |
| wire \u_riscv_top.fpu_dmem_addr[0] ; |
| wire \u_riscv_top.fpu_dmem_addr[1] ; |
| wire \u_riscv_top.fpu_dmem_addr[2] ; |
| wire \u_riscv_top.fpu_dmem_addr[3] ; |
| wire \u_riscv_top.fpu_dmem_addr[4] ; |
| wire \u_riscv_top.fpu_dmem_cmd ; |
| wire \u_riscv_top.fpu_dmem_rdata[0] ; |
| wire \u_riscv_top.fpu_dmem_rdata[10] ; |
| wire \u_riscv_top.fpu_dmem_rdata[11] ; |
| wire \u_riscv_top.fpu_dmem_rdata[12] ; |
| wire \u_riscv_top.fpu_dmem_rdata[13] ; |
| wire \u_riscv_top.fpu_dmem_rdata[14] ; |
| wire \u_riscv_top.fpu_dmem_rdata[15] ; |
| wire \u_riscv_top.fpu_dmem_rdata[16] ; |
| wire \u_riscv_top.fpu_dmem_rdata[17] ; |
| wire \u_riscv_top.fpu_dmem_rdata[18] ; |
| wire \u_riscv_top.fpu_dmem_rdata[19] ; |
| wire \u_riscv_top.fpu_dmem_rdata[1] ; |
| wire \u_riscv_top.fpu_dmem_rdata[20] ; |
| wire \u_riscv_top.fpu_dmem_rdata[21] ; |
| wire \u_riscv_top.fpu_dmem_rdata[22] ; |
| wire \u_riscv_top.fpu_dmem_rdata[23] ; |
| wire \u_riscv_top.fpu_dmem_rdata[24] ; |
| wire \u_riscv_top.fpu_dmem_rdata[25] ; |
| wire \u_riscv_top.fpu_dmem_rdata[26] ; |
| wire \u_riscv_top.fpu_dmem_rdata[27] ; |
| wire \u_riscv_top.fpu_dmem_rdata[28] ; |
| wire \u_riscv_top.fpu_dmem_rdata[29] ; |
| wire \u_riscv_top.fpu_dmem_rdata[2] ; |
| wire \u_riscv_top.fpu_dmem_rdata[30] ; |
| wire \u_riscv_top.fpu_dmem_rdata[31] ; |
| wire \u_riscv_top.fpu_dmem_rdata[3] ; |
| wire \u_riscv_top.fpu_dmem_rdata[4] ; |
| wire \u_riscv_top.fpu_dmem_rdata[5] ; |
| wire \u_riscv_top.fpu_dmem_rdata[6] ; |
| wire \u_riscv_top.fpu_dmem_rdata[7] ; |
| wire \u_riscv_top.fpu_dmem_rdata[8] ; |
| wire \u_riscv_top.fpu_dmem_rdata[9] ; |
| wire \u_riscv_top.fpu_dmem_req ; |
| wire \u_riscv_top.fpu_dmem_req_ack ; |
| wire \u_riscv_top.fpu_dmem_resp[0] ; |
| wire \u_riscv_top.fpu_dmem_resp[1] ; |
| wire \u_riscv_top.fpu_dmem_wdata[0] ; |
| wire \u_riscv_top.fpu_dmem_wdata[10] ; |
| wire \u_riscv_top.fpu_dmem_wdata[11] ; |
| wire \u_riscv_top.fpu_dmem_wdata[12] ; |
| wire \u_riscv_top.fpu_dmem_wdata[13] ; |
| wire \u_riscv_top.fpu_dmem_wdata[14] ; |
| wire \u_riscv_top.fpu_dmem_wdata[15] ; |
| wire \u_riscv_top.fpu_dmem_wdata[16] ; |
| wire \u_riscv_top.fpu_dmem_wdata[17] ; |
| wire \u_riscv_top.fpu_dmem_wdata[18] ; |
| wire \u_riscv_top.fpu_dmem_wdata[19] ; |
| wire \u_riscv_top.fpu_dmem_wdata[1] ; |
| wire \u_riscv_top.fpu_dmem_wdata[20] ; |
| wire \u_riscv_top.fpu_dmem_wdata[21] ; |
| wire \u_riscv_top.fpu_dmem_wdata[22] ; |
| wire \u_riscv_top.fpu_dmem_wdata[23] ; |
| wire \u_riscv_top.fpu_dmem_wdata[24] ; |
| wire \u_riscv_top.fpu_dmem_wdata[25] ; |
| wire \u_riscv_top.fpu_dmem_wdata[26] ; |
| wire \u_riscv_top.fpu_dmem_wdata[27] ; |
| wire \u_riscv_top.fpu_dmem_wdata[28] ; |
| wire \u_riscv_top.fpu_dmem_wdata[29] ; |
| wire \u_riscv_top.fpu_dmem_wdata[2] ; |
| wire \u_riscv_top.fpu_dmem_wdata[30] ; |
| wire \u_riscv_top.fpu_dmem_wdata[31] ; |
| wire \u_riscv_top.fpu_dmem_wdata[3] ; |
| wire \u_riscv_top.fpu_dmem_wdata[4] ; |
| wire \u_riscv_top.fpu_dmem_wdata[5] ; |
| wire \u_riscv_top.fpu_dmem_wdata[6] ; |
| wire \u_riscv_top.fpu_dmem_wdata[7] ; |
| wire \u_riscv_top.fpu_dmem_wdata[8] ; |
| wire \u_riscv_top.fpu_dmem_wdata[9] ; |
| wire \u_riscv_top.fpu_dmem_width[0] ; |
| wire \u_riscv_top.fpu_dmem_width[1] ; |
| wire \u_riscv_top.icache_mem_addr0[0] ; |
| wire \u_riscv_top.icache_mem_addr0[1] ; |
| wire \u_riscv_top.icache_mem_addr0[2] ; |
| wire \u_riscv_top.icache_mem_addr0[3] ; |
| wire \u_riscv_top.icache_mem_addr0[4] ; |
| wire \u_riscv_top.icache_mem_addr0[5] ; |
| wire \u_riscv_top.icache_mem_addr0[6] ; |
| wire \u_riscv_top.icache_mem_addr0[7] ; |
| wire \u_riscv_top.icache_mem_addr0[8] ; |
| wire \u_riscv_top.icache_mem_addr1[0] ; |
| wire \u_riscv_top.icache_mem_addr1[1] ; |
| wire \u_riscv_top.icache_mem_addr1[2] ; |
| wire \u_riscv_top.icache_mem_addr1[3] ; |
| wire \u_riscv_top.icache_mem_addr1[4] ; |
| wire \u_riscv_top.icache_mem_addr1[5] ; |
| wire \u_riscv_top.icache_mem_addr1[6] ; |
| wire \u_riscv_top.icache_mem_addr1[7] ; |
| wire \u_riscv_top.icache_mem_addr1[8] ; |
| wire \u_riscv_top.icache_mem_clk0 ; |
| wire \u_riscv_top.icache_mem_clk1 ; |
| wire \u_riscv_top.icache_mem_csb0 ; |
| wire \u_riscv_top.icache_mem_csb1 ; |
| wire \u_riscv_top.icache_mem_din0[0] ; |
| wire \u_riscv_top.icache_mem_din0[10] ; |
| wire \u_riscv_top.icache_mem_din0[11] ; |
| wire \u_riscv_top.icache_mem_din0[12] ; |
| wire \u_riscv_top.icache_mem_din0[13] ; |
| wire \u_riscv_top.icache_mem_din0[14] ; |
| wire \u_riscv_top.icache_mem_din0[15] ; |
| wire \u_riscv_top.icache_mem_din0[16] ; |
| wire \u_riscv_top.icache_mem_din0[17] ; |
| wire \u_riscv_top.icache_mem_din0[18] ; |
| wire \u_riscv_top.icache_mem_din0[19] ; |
| wire \u_riscv_top.icache_mem_din0[1] ; |
| wire \u_riscv_top.icache_mem_din0[20] ; |
| wire \u_riscv_top.icache_mem_din0[21] ; |
| wire \u_riscv_top.icache_mem_din0[22] ; |
| wire \u_riscv_top.icache_mem_din0[23] ; |
| wire \u_riscv_top.icache_mem_din0[24] ; |
| wire \u_riscv_top.icache_mem_din0[25] ; |
| wire \u_riscv_top.icache_mem_din0[26] ; |
| wire \u_riscv_top.icache_mem_din0[27] ; |
| wire \u_riscv_top.icache_mem_din0[28] ; |
| wire \u_riscv_top.icache_mem_din0[29] ; |
| wire \u_riscv_top.icache_mem_din0[2] ; |
| wire \u_riscv_top.icache_mem_din0[30] ; |
| wire \u_riscv_top.icache_mem_din0[31] ; |
| wire \u_riscv_top.icache_mem_din0[3] ; |
| wire \u_riscv_top.icache_mem_din0[4] ; |
| wire \u_riscv_top.icache_mem_din0[5] ; |
| wire \u_riscv_top.icache_mem_din0[6] ; |
| wire \u_riscv_top.icache_mem_din0[7] ; |
| wire \u_riscv_top.icache_mem_din0[8] ; |
| wire \u_riscv_top.icache_mem_din0[9] ; |
| wire \u_riscv_top.icache_mem_dout1[0] ; |
| wire \u_riscv_top.icache_mem_dout1[10] ; |
| wire \u_riscv_top.icache_mem_dout1[11] ; |
| wire \u_riscv_top.icache_mem_dout1[12] ; |
| wire \u_riscv_top.icache_mem_dout1[13] ; |
| wire \u_riscv_top.icache_mem_dout1[14] ; |
| wire \u_riscv_top.icache_mem_dout1[15] ; |
| wire \u_riscv_top.icache_mem_dout1[16] ; |
| wire \u_riscv_top.icache_mem_dout1[17] ; |
| wire \u_riscv_top.icache_mem_dout1[18] ; |
| wire \u_riscv_top.icache_mem_dout1[19] ; |
| wire \u_riscv_top.icache_mem_dout1[1] ; |
| wire \u_riscv_top.icache_mem_dout1[20] ; |
| wire \u_riscv_top.icache_mem_dout1[21] ; |
| wire \u_riscv_top.icache_mem_dout1[22] ; |
| wire \u_riscv_top.icache_mem_dout1[23] ; |
| wire \u_riscv_top.icache_mem_dout1[24] ; |
| wire \u_riscv_top.icache_mem_dout1[25] ; |
| wire \u_riscv_top.icache_mem_dout1[26] ; |
| wire \u_riscv_top.icache_mem_dout1[27] ; |
| wire \u_riscv_top.icache_mem_dout1[28] ; |
| wire \u_riscv_top.icache_mem_dout1[29] ; |
| wire \u_riscv_top.icache_mem_dout1[2] ; |
| wire \u_riscv_top.icache_mem_dout1[30] ; |
| wire \u_riscv_top.icache_mem_dout1[31] ; |
| wire \u_riscv_top.icache_mem_dout1[3] ; |
| wire \u_riscv_top.icache_mem_dout1[4] ; |
| wire \u_riscv_top.icache_mem_dout1[5] ; |
| wire \u_riscv_top.icache_mem_dout1[6] ; |
| wire \u_riscv_top.icache_mem_dout1[7] ; |
| wire \u_riscv_top.icache_mem_dout1[8] ; |
| wire \u_riscv_top.icache_mem_dout1[9] ; |
| wire \u_riscv_top.icache_mem_web0 ; |
| wire \u_riscv_top.icache_mem_wmask0[0] ; |
| wire \u_riscv_top.icache_mem_wmask0[1] ; |
| wire \u_riscv_top.icache_mem_wmask0[2] ; |
| wire \u_riscv_top.icache_mem_wmask0[3] ; |
| wire \u_riscv_top.irq_lines[0] ; |
| wire \u_riscv_top.irq_lines[10] ; |
| wire \u_riscv_top.irq_lines[11] ; |
| wire \u_riscv_top.irq_lines[12] ; |
| wire \u_riscv_top.irq_lines[13] ; |
| wire \u_riscv_top.irq_lines[14] ; |
| wire \u_riscv_top.irq_lines[15] ; |
| wire \u_riscv_top.irq_lines[16] ; |
| wire \u_riscv_top.irq_lines[17] ; |
| wire \u_riscv_top.irq_lines[18] ; |
| wire \u_riscv_top.irq_lines[19] ; |
| wire \u_riscv_top.irq_lines[1] ; |
| wire \u_riscv_top.irq_lines[20] ; |
| wire \u_riscv_top.irq_lines[21] ; |
| wire \u_riscv_top.irq_lines[22] ; |
| wire \u_riscv_top.irq_lines[23] ; |
| wire \u_riscv_top.irq_lines[24] ; |
| wire \u_riscv_top.irq_lines[25] ; |
| wire \u_riscv_top.irq_lines[26] ; |
| wire \u_riscv_top.irq_lines[27] ; |
| wire \u_riscv_top.irq_lines[28] ; |
| wire \u_riscv_top.irq_lines[29] ; |
| wire \u_riscv_top.irq_lines[2] ; |
| wire \u_riscv_top.irq_lines[30] ; |
| wire \u_riscv_top.irq_lines[31] ; |
| wire \u_riscv_top.irq_lines[3] ; |
| wire \u_riscv_top.irq_lines[4] ; |
| wire \u_riscv_top.irq_lines[5] ; |
| wire \u_riscv_top.irq_lines[6] ; |
| wire \u_riscv_top.irq_lines[7] ; |
| wire \u_riscv_top.irq_lines[8] ; |
| wire \u_riscv_top.irq_lines[9] ; |
| wire \u_riscv_top.pwrup_rst_n ; |
| wire \u_riscv_top.riscv_debug[0] ; |
| wire \u_riscv_top.riscv_debug[10] ; |
| wire \u_riscv_top.riscv_debug[11] ; |
| wire \u_riscv_top.riscv_debug[12] ; |
| wire \u_riscv_top.riscv_debug[13] ; |
| wire \u_riscv_top.riscv_debug[14] ; |
| wire \u_riscv_top.riscv_debug[15] ; |
| wire \u_riscv_top.riscv_debug[16] ; |
| wire \u_riscv_top.riscv_debug[17] ; |
| wire \u_riscv_top.riscv_debug[18] ; |
| wire \u_riscv_top.riscv_debug[19] ; |
| wire \u_riscv_top.riscv_debug[1] ; |
| wire \u_riscv_top.riscv_debug[20] ; |
| wire \u_riscv_top.riscv_debug[21] ; |
| wire \u_riscv_top.riscv_debug[22] ; |
| wire \u_riscv_top.riscv_debug[23] ; |
| wire \u_riscv_top.riscv_debug[24] ; |
| wire \u_riscv_top.riscv_debug[25] ; |
| wire \u_riscv_top.riscv_debug[26] ; |
| wire \u_riscv_top.riscv_debug[27] ; |
| wire \u_riscv_top.riscv_debug[28] ; |
| wire \u_riscv_top.riscv_debug[29] ; |
| wire \u_riscv_top.riscv_debug[2] ; |
| wire \u_riscv_top.riscv_debug[30] ; |
| wire \u_riscv_top.riscv_debug[31] ; |
| wire \u_riscv_top.riscv_debug[32] ; |
| wire \u_riscv_top.riscv_debug[33] ; |
| wire \u_riscv_top.riscv_debug[34] ; |
| wire \u_riscv_top.riscv_debug[35] ; |
| wire \u_riscv_top.riscv_debug[36] ; |
| wire \u_riscv_top.riscv_debug[37] ; |
| wire \u_riscv_top.riscv_debug[38] ; |
| wire \u_riscv_top.riscv_debug[39] ; |
| wire \u_riscv_top.riscv_debug[3] ; |
| wire \u_riscv_top.riscv_debug[40] ; |
| wire \u_riscv_top.riscv_debug[41] ; |
| wire \u_riscv_top.riscv_debug[42] ; |
| wire \u_riscv_top.riscv_debug[43] ; |
| wire \u_riscv_top.riscv_debug[44] ; |
| wire \u_riscv_top.riscv_debug[45] ; |
| wire \u_riscv_top.riscv_debug[46] ; |
| wire \u_riscv_top.riscv_debug[47] ; |
| wire \u_riscv_top.riscv_debug[48] ; |
| wire \u_riscv_top.riscv_debug[49] ; |
| wire \u_riscv_top.riscv_debug[4] ; |
| wire \u_riscv_top.riscv_debug[50] ; |
| wire \u_riscv_top.riscv_debug[51] ; |
| wire \u_riscv_top.riscv_debug[52] ; |
| wire \u_riscv_top.riscv_debug[53] ; |
| wire \u_riscv_top.riscv_debug[54] ; |
| wire \u_riscv_top.riscv_debug[55] ; |
| wire \u_riscv_top.riscv_debug[56] ; |
| wire \u_riscv_top.riscv_debug[57] ; |
| wire \u_riscv_top.riscv_debug[58] ; |
| wire \u_riscv_top.riscv_debug[59] ; |
| wire \u_riscv_top.riscv_debug[5] ; |
| wire \u_riscv_top.riscv_debug[60] ; |
| wire \u_riscv_top.riscv_debug[61] ; |
| wire \u_riscv_top.riscv_debug[62] ; |
| wire \u_riscv_top.riscv_debug[63] ; |
| wire \u_riscv_top.riscv_debug[6] ; |
| wire \u_riscv_top.riscv_debug[7] ; |
| wire \u_riscv_top.riscv_debug[8] ; |
| wire \u_riscv_top.riscv_debug[9] ; |
| wire \u_riscv_top.rtc_clk ; |
| wire \u_riscv_top.soft_irq ; |
| wire \u_riscv_top.sram0_addr0[0] ; |
| wire \u_riscv_top.sram0_addr0[1] ; |
| wire \u_riscv_top.sram0_addr0[2] ; |
| wire \u_riscv_top.sram0_addr0[3] ; |
| wire \u_riscv_top.sram0_addr0[4] ; |
| wire \u_riscv_top.sram0_addr0[5] ; |
| wire \u_riscv_top.sram0_addr0[6] ; |
| wire \u_riscv_top.sram0_addr0[7] ; |
| wire \u_riscv_top.sram0_addr0[8] ; |
| wire \u_riscv_top.sram0_addr1[0] ; |
| wire \u_riscv_top.sram0_addr1[1] ; |
| wire \u_riscv_top.sram0_addr1[2] ; |
| wire \u_riscv_top.sram0_addr1[3] ; |
| wire \u_riscv_top.sram0_addr1[4] ; |
| wire \u_riscv_top.sram0_addr1[5] ; |
| wire \u_riscv_top.sram0_addr1[6] ; |
| wire \u_riscv_top.sram0_addr1[7] ; |
| wire \u_riscv_top.sram0_addr1[8] ; |
| wire \u_riscv_top.sram0_clk0 ; |
| wire \u_riscv_top.sram0_clk1 ; |
| wire \u_riscv_top.sram0_csb0 ; |
| wire \u_riscv_top.sram0_csb1 ; |
| wire \u_riscv_top.sram0_din0[0] ; |
| wire \u_riscv_top.sram0_din0[10] ; |
| wire \u_riscv_top.sram0_din0[11] ; |
| wire \u_riscv_top.sram0_din0[12] ; |
| wire \u_riscv_top.sram0_din0[13] ; |
| wire \u_riscv_top.sram0_din0[14] ; |
| wire \u_riscv_top.sram0_din0[15] ; |
| wire \u_riscv_top.sram0_din0[16] ; |
| wire \u_riscv_top.sram0_din0[17] ; |
| wire \u_riscv_top.sram0_din0[18] ; |
| wire \u_riscv_top.sram0_din0[19] ; |
| wire \u_riscv_top.sram0_din0[1] ; |
| wire \u_riscv_top.sram0_din0[20] ; |
| wire \u_riscv_top.sram0_din0[21] ; |
| wire \u_riscv_top.sram0_din0[22] ; |
| wire \u_riscv_top.sram0_din0[23] ; |
| wire \u_riscv_top.sram0_din0[24] ; |
| wire \u_riscv_top.sram0_din0[25] ; |
| wire \u_riscv_top.sram0_din0[26] ; |
| wire \u_riscv_top.sram0_din0[27] ; |
| wire \u_riscv_top.sram0_din0[28] ; |
| wire \u_riscv_top.sram0_din0[29] ; |
| wire \u_riscv_top.sram0_din0[2] ; |
| wire \u_riscv_top.sram0_din0[30] ; |
| wire \u_riscv_top.sram0_din0[31] ; |
| wire \u_riscv_top.sram0_din0[3] ; |
| wire \u_riscv_top.sram0_din0[4] ; |
| wire \u_riscv_top.sram0_din0[5] ; |
| wire \u_riscv_top.sram0_din0[6] ; |
| wire \u_riscv_top.sram0_din0[7] ; |
| wire \u_riscv_top.sram0_din0[8] ; |
| wire \u_riscv_top.sram0_din0[9] ; |
| wire \u_riscv_top.sram0_dout0[0] ; |
| wire \u_riscv_top.sram0_dout0[10] ; |
| wire \u_riscv_top.sram0_dout0[11] ; |
| wire \u_riscv_top.sram0_dout0[12] ; |
| wire \u_riscv_top.sram0_dout0[13] ; |
| wire \u_riscv_top.sram0_dout0[14] ; |
| wire \u_riscv_top.sram0_dout0[15] ; |
| wire \u_riscv_top.sram0_dout0[16] ; |
| wire \u_riscv_top.sram0_dout0[17] ; |
| wire \u_riscv_top.sram0_dout0[18] ; |
| wire \u_riscv_top.sram0_dout0[19] ; |
| wire \u_riscv_top.sram0_dout0[1] ; |
| wire \u_riscv_top.sram0_dout0[20] ; |
| wire \u_riscv_top.sram0_dout0[21] ; |
| wire \u_riscv_top.sram0_dout0[22] ; |
| wire \u_riscv_top.sram0_dout0[23] ; |
| wire \u_riscv_top.sram0_dout0[24] ; |
| wire \u_riscv_top.sram0_dout0[25] ; |
| wire \u_riscv_top.sram0_dout0[26] ; |
| wire \u_riscv_top.sram0_dout0[27] ; |
| wire \u_riscv_top.sram0_dout0[28] ; |
| wire \u_riscv_top.sram0_dout0[29] ; |
| wire \u_riscv_top.sram0_dout0[2] ; |
| wire \u_riscv_top.sram0_dout0[30] ; |
| wire \u_riscv_top.sram0_dout0[31] ; |
| wire \u_riscv_top.sram0_dout0[3] ; |
| wire \u_riscv_top.sram0_dout0[4] ; |
| wire \u_riscv_top.sram0_dout0[5] ; |
| wire \u_riscv_top.sram0_dout0[6] ; |
| wire \u_riscv_top.sram0_dout0[7] ; |
| wire \u_riscv_top.sram0_dout0[8] ; |
| wire \u_riscv_top.sram0_dout0[9] ; |
| wire \u_riscv_top.sram0_dout1[0] ; |
| wire \u_riscv_top.sram0_dout1[10] ; |
| wire \u_riscv_top.sram0_dout1[11] ; |
| wire \u_riscv_top.sram0_dout1[12] ; |
| wire \u_riscv_top.sram0_dout1[13] ; |
| wire \u_riscv_top.sram0_dout1[14] ; |
| wire \u_riscv_top.sram0_dout1[15] ; |
| wire \u_riscv_top.sram0_dout1[16] ; |
| wire \u_riscv_top.sram0_dout1[17] ; |
| wire \u_riscv_top.sram0_dout1[18] ; |
| wire \u_riscv_top.sram0_dout1[19] ; |
| wire \u_riscv_top.sram0_dout1[1] ; |
| wire \u_riscv_top.sram0_dout1[20] ; |
| wire \u_riscv_top.sram0_dout1[21] ; |
| wire \u_riscv_top.sram0_dout1[22] ; |
| wire \u_riscv_top.sram0_dout1[23] ; |
| wire \u_riscv_top.sram0_dout1[24] ; |
| wire \u_riscv_top.sram0_dout1[25] ; |
| wire \u_riscv_top.sram0_dout1[26] ; |
| wire \u_riscv_top.sram0_dout1[27] ; |
| wire \u_riscv_top.sram0_dout1[28] ; |
| wire \u_riscv_top.sram0_dout1[29] ; |
| wire \u_riscv_top.sram0_dout1[2] ; |
| wire \u_riscv_top.sram0_dout1[30] ; |
| wire \u_riscv_top.sram0_dout1[31] ; |
| wire \u_riscv_top.sram0_dout1[3] ; |
| wire \u_riscv_top.sram0_dout1[4] ; |
| wire \u_riscv_top.sram0_dout1[5] ; |
| wire \u_riscv_top.sram0_dout1[6] ; |
| wire \u_riscv_top.sram0_dout1[7] ; |
| wire \u_riscv_top.sram0_dout1[8] ; |
| wire \u_riscv_top.sram0_dout1[9] ; |
| wire \u_riscv_top.sram0_web0 ; |
| wire \u_riscv_top.sram0_wmask0[0] ; |
| wire \u_riscv_top.sram0_wmask0[1] ; |
| wire \u_riscv_top.sram0_wmask0[2] ; |
| wire \u_riscv_top.sram0_wmask0[3] ; |
| wire \u_riscv_top.wb_clk ; |
| wire \u_riscv_top.wb_dcache_ack_i ; |
| wire \u_riscv_top.wb_dcache_adr_o[0] ; |
| wire \u_riscv_top.wb_dcache_adr_o[10] ; |
| wire \u_riscv_top.wb_dcache_adr_o[11] ; |
| wire \u_riscv_top.wb_dcache_adr_o[12] ; |
| wire \u_riscv_top.wb_dcache_adr_o[13] ; |
| wire \u_riscv_top.wb_dcache_adr_o[14] ; |
| wire \u_riscv_top.wb_dcache_adr_o[15] ; |
| wire \u_riscv_top.wb_dcache_adr_o[16] ; |
| wire \u_riscv_top.wb_dcache_adr_o[17] ; |
| wire \u_riscv_top.wb_dcache_adr_o[18] ; |
| wire \u_riscv_top.wb_dcache_adr_o[19] ; |
| wire \u_riscv_top.wb_dcache_adr_o[1] ; |
| wire \u_riscv_top.wb_dcache_adr_o[20] ; |
| wire \u_riscv_top.wb_dcache_adr_o[21] ; |
| wire \u_riscv_top.wb_dcache_adr_o[22] ; |
| wire \u_riscv_top.wb_dcache_adr_o[23] ; |
| wire \u_riscv_top.wb_dcache_adr_o[24] ; |
| wire \u_riscv_top.wb_dcache_adr_o[25] ; |
| wire \u_riscv_top.wb_dcache_adr_o[26] ; |
| wire \u_riscv_top.wb_dcache_adr_o[27] ; |
| wire \u_riscv_top.wb_dcache_adr_o[28] ; |
| wire \u_riscv_top.wb_dcache_adr_o[29] ; |
| wire \u_riscv_top.wb_dcache_adr_o[2] ; |
| wire \u_riscv_top.wb_dcache_adr_o[30] ; |
| wire \u_riscv_top.wb_dcache_adr_o[31] ; |
| wire \u_riscv_top.wb_dcache_adr_o[3] ; |
| wire \u_riscv_top.wb_dcache_adr_o[4] ; |
| wire \u_riscv_top.wb_dcache_adr_o[5] ; |
| wire \u_riscv_top.wb_dcache_adr_o[6] ; |
| wire \u_riscv_top.wb_dcache_adr_o[7] ; |
| wire \u_riscv_top.wb_dcache_adr_o[8] ; |
| wire \u_riscv_top.wb_dcache_adr_o[9] ; |
| wire \u_riscv_top.wb_dcache_bl_o[0] ; |
| wire \u_riscv_top.wb_dcache_bl_o[1] ; |
| wire \u_riscv_top.wb_dcache_bl_o[2] ; |
| wire \u_riscv_top.wb_dcache_bl_o[3] ; |
| wire \u_riscv_top.wb_dcache_bl_o[4] ; |
| wire \u_riscv_top.wb_dcache_bl_o[5] ; |
| wire \u_riscv_top.wb_dcache_bl_o[6] ; |
| wire \u_riscv_top.wb_dcache_bl_o[7] ; |
| wire \u_riscv_top.wb_dcache_bl_o[8] ; |
| wire \u_riscv_top.wb_dcache_bl_o[9] ; |
| wire \u_riscv_top.wb_dcache_bry_o ; |
| wire \u_riscv_top.wb_dcache_dat_i[0] ; |
| wire \u_riscv_top.wb_dcache_dat_i[10] ; |
| wire \u_riscv_top.wb_dcache_dat_i[11] ; |
| wire \u_riscv_top.wb_dcache_dat_i[12] ; |
| wire \u_riscv_top.wb_dcache_dat_i[13] ; |
| wire \u_riscv_top.wb_dcache_dat_i[14] ; |
| wire \u_riscv_top.wb_dcache_dat_i[15] ; |
| wire \u_riscv_top.wb_dcache_dat_i[16] ; |
| wire \u_riscv_top.wb_dcache_dat_i[17] ; |
| wire \u_riscv_top.wb_dcache_dat_i[18] ; |
| wire \u_riscv_top.wb_dcache_dat_i[19] ; |
| wire \u_riscv_top.wb_dcache_dat_i[1] ; |
| wire \u_riscv_top.wb_dcache_dat_i[20] ; |
| wire \u_riscv_top.wb_dcache_dat_i[21] ; |
| wire \u_riscv_top.wb_dcache_dat_i[22] ; |
| wire \u_riscv_top.wb_dcache_dat_i[23] ; |
| wire \u_riscv_top.wb_dcache_dat_i[24] ; |
| wire \u_riscv_top.wb_dcache_dat_i[25] ; |
| wire \u_riscv_top.wb_dcache_dat_i[26] ; |
| wire \u_riscv_top.wb_dcache_dat_i[27] ; |
| wire \u_riscv_top.wb_dcache_dat_i[28] ; |
| wire \u_riscv_top.wb_dcache_dat_i[29] ; |
| wire \u_riscv_top.wb_dcache_dat_i[2] ; |
| wire \u_riscv_top.wb_dcache_dat_i[30] ; |
| wire \u_riscv_top.wb_dcache_dat_i[31] ; |
| wire \u_riscv_top.wb_dcache_dat_i[3] ; |
| wire \u_riscv_top.wb_dcache_dat_i[4] ; |
| wire \u_riscv_top.wb_dcache_dat_i[5] ; |
| wire \u_riscv_top.wb_dcache_dat_i[6] ; |
| wire \u_riscv_top.wb_dcache_dat_i[7] ; |
| wire \u_riscv_top.wb_dcache_dat_i[8] ; |
| wire \u_riscv_top.wb_dcache_dat_i[9] ; |
| wire \u_riscv_top.wb_dcache_dat_o[0] ; |
| wire \u_riscv_top.wb_dcache_dat_o[10] ; |
| wire \u_riscv_top.wb_dcache_dat_o[11] ; |
| wire \u_riscv_top.wb_dcache_dat_o[12] ; |
| wire \u_riscv_top.wb_dcache_dat_o[13] ; |
| wire \u_riscv_top.wb_dcache_dat_o[14] ; |
| wire \u_riscv_top.wb_dcache_dat_o[15] ; |
| wire \u_riscv_top.wb_dcache_dat_o[16] ; |
| wire \u_riscv_top.wb_dcache_dat_o[17] ; |
| wire \u_riscv_top.wb_dcache_dat_o[18] ; |
| wire \u_riscv_top.wb_dcache_dat_o[19] ; |
| wire \u_riscv_top.wb_dcache_dat_o[1] ; |
| wire \u_riscv_top.wb_dcache_dat_o[20] ; |
| wire \u_riscv_top.wb_dcache_dat_o[21] ; |
| wire \u_riscv_top.wb_dcache_dat_o[22] ; |
| wire \u_riscv_top.wb_dcache_dat_o[23] ; |
| wire \u_riscv_top.wb_dcache_dat_o[24] ; |
| wire \u_riscv_top.wb_dcache_dat_o[25] ; |
| wire \u_riscv_top.wb_dcache_dat_o[26] ; |
| wire \u_riscv_top.wb_dcache_dat_o[27] ; |
| wire \u_riscv_top.wb_dcache_dat_o[28] ; |
| wire \u_riscv_top.wb_dcache_dat_o[29] ; |
| wire \u_riscv_top.wb_dcache_dat_o[2] ; |
| wire \u_riscv_top.wb_dcache_dat_o[30] ; |
| wire \u_riscv_top.wb_dcache_dat_o[31] ; |
| wire \u_riscv_top.wb_dcache_dat_o[3] ; |
| wire \u_riscv_top.wb_dcache_dat_o[4] ; |
| wire \u_riscv_top.wb_dcache_dat_o[5] ; |
| wire \u_riscv_top.wb_dcache_dat_o[6] ; |
| wire \u_riscv_top.wb_dcache_dat_o[7] ; |
| wire \u_riscv_top.wb_dcache_dat_o[8] ; |
| wire \u_riscv_top.wb_dcache_dat_o[9] ; |
| wire \u_riscv_top.wb_dcache_err_i ; |
| wire \u_riscv_top.wb_dcache_lack_i ; |
| wire \u_riscv_top.wb_dcache_sel_o[0] ; |
| wire \u_riscv_top.wb_dcache_sel_o[1] ; |
| wire \u_riscv_top.wb_dcache_sel_o[2] ; |
| wire \u_riscv_top.wb_dcache_sel_o[3] ; |
| wire \u_riscv_top.wb_dcache_stb_o ; |
| wire \u_riscv_top.wb_dcache_we_o ; |
| wire \u_riscv_top.wb_icache_ack_i ; |
| wire \u_riscv_top.wb_icache_adr_o[0] ; |
| wire \u_riscv_top.wb_icache_adr_o[10] ; |
| wire \u_riscv_top.wb_icache_adr_o[11] ; |
| wire \u_riscv_top.wb_icache_adr_o[12] ; |
| wire \u_riscv_top.wb_icache_adr_o[13] ; |
| wire \u_riscv_top.wb_icache_adr_o[14] ; |
| wire \u_riscv_top.wb_icache_adr_o[15] ; |
| wire \u_riscv_top.wb_icache_adr_o[16] ; |
| wire \u_riscv_top.wb_icache_adr_o[17] ; |
| wire \u_riscv_top.wb_icache_adr_o[18] ; |
| wire \u_riscv_top.wb_icache_adr_o[19] ; |
| wire \u_riscv_top.wb_icache_adr_o[1] ; |
| wire \u_riscv_top.wb_icache_adr_o[20] ; |
| wire \u_riscv_top.wb_icache_adr_o[21] ; |
| wire \u_riscv_top.wb_icache_adr_o[22] ; |
| wire \u_riscv_top.wb_icache_adr_o[23] ; |
| wire \u_riscv_top.wb_icache_adr_o[24] ; |
| wire \u_riscv_top.wb_icache_adr_o[25] ; |
| wire \u_riscv_top.wb_icache_adr_o[26] ; |
| wire \u_riscv_top.wb_icache_adr_o[27] ; |
| wire \u_riscv_top.wb_icache_adr_o[28] ; |
| wire \u_riscv_top.wb_icache_adr_o[29] ; |
| wire \u_riscv_top.wb_icache_adr_o[2] ; |
| wire \u_riscv_top.wb_icache_adr_o[30] ; |
| wire \u_riscv_top.wb_icache_adr_o[31] ; |
| wire \u_riscv_top.wb_icache_adr_o[3] ; |
| wire \u_riscv_top.wb_icache_adr_o[4] ; |
| wire \u_riscv_top.wb_icache_adr_o[5] ; |
| wire \u_riscv_top.wb_icache_adr_o[6] ; |
| wire \u_riscv_top.wb_icache_adr_o[7] ; |
| wire \u_riscv_top.wb_icache_adr_o[8] ; |
| wire \u_riscv_top.wb_icache_adr_o[9] ; |
| wire \u_riscv_top.wb_icache_bl_o[0] ; |
| wire \u_riscv_top.wb_icache_bl_o[1] ; |
| wire \u_riscv_top.wb_icache_bl_o[2] ; |
| wire \u_riscv_top.wb_icache_bl_o[3] ; |
| wire \u_riscv_top.wb_icache_bl_o[4] ; |
| wire \u_riscv_top.wb_icache_bl_o[5] ; |
| wire \u_riscv_top.wb_icache_bl_o[6] ; |
| wire \u_riscv_top.wb_icache_bl_o[7] ; |
| wire \u_riscv_top.wb_icache_bl_o[8] ; |
| wire \u_riscv_top.wb_icache_bl_o[9] ; |
| wire \u_riscv_top.wb_icache_bry_o ; |
| wire \u_riscv_top.wb_icache_dat_i[0] ; |
| wire \u_riscv_top.wb_icache_dat_i[10] ; |
| wire \u_riscv_top.wb_icache_dat_i[11] ; |
| wire \u_riscv_top.wb_icache_dat_i[12] ; |
| wire \u_riscv_top.wb_icache_dat_i[13] ; |
| wire \u_riscv_top.wb_icache_dat_i[14] ; |
| wire \u_riscv_top.wb_icache_dat_i[15] ; |
| wire \u_riscv_top.wb_icache_dat_i[16] ; |
| wire \u_riscv_top.wb_icache_dat_i[17] ; |
| wire \u_riscv_top.wb_icache_dat_i[18] ; |
| wire \u_riscv_top.wb_icache_dat_i[19] ; |
| wire \u_riscv_top.wb_icache_dat_i[1] ; |
| wire \u_riscv_top.wb_icache_dat_i[20] ; |
| wire \u_riscv_top.wb_icache_dat_i[21] ; |
| wire \u_riscv_top.wb_icache_dat_i[22] ; |
| wire \u_riscv_top.wb_icache_dat_i[23] ; |
| wire \u_riscv_top.wb_icache_dat_i[24] ; |
| wire \u_riscv_top.wb_icache_dat_i[25] ; |
| wire \u_riscv_top.wb_icache_dat_i[26] ; |
| wire \u_riscv_top.wb_icache_dat_i[27] ; |
| wire \u_riscv_top.wb_icache_dat_i[28] ; |
| wire \u_riscv_top.wb_icache_dat_i[29] ; |
| wire \u_riscv_top.wb_icache_dat_i[2] ; |
| wire \u_riscv_top.wb_icache_dat_i[30] ; |
| wire \u_riscv_top.wb_icache_dat_i[31] ; |
| wire \u_riscv_top.wb_icache_dat_i[3] ; |
| wire \u_riscv_top.wb_icache_dat_i[4] ; |
| wire \u_riscv_top.wb_icache_dat_i[5] ; |
| wire \u_riscv_top.wb_icache_dat_i[6] ; |
| wire \u_riscv_top.wb_icache_dat_i[7] ; |
| wire \u_riscv_top.wb_icache_dat_i[8] ; |
| wire \u_riscv_top.wb_icache_dat_i[9] ; |
| wire \u_riscv_top.wb_icache_err_i ; |
| wire \u_riscv_top.wb_icache_lack_i ; |
| wire \u_riscv_top.wb_icache_sel_o[0] ; |
| wire \u_riscv_top.wb_icache_sel_o[1] ; |
| wire \u_riscv_top.wb_icache_sel_o[2] ; |
| wire \u_riscv_top.wb_icache_sel_o[3] ; |
| wire \u_riscv_top.wb_icache_stb_o ; |
| wire \u_riscv_top.wb_icache_we_o ; |
| wire \u_riscv_top.wbd_clk_int ; |
| wire \u_riscv_top.wbd_dmem_ack_i ; |
| wire \u_riscv_top.wbd_dmem_adr_o[0] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[10] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[11] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[12] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[13] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[14] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[15] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[16] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[17] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[18] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[19] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[1] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[20] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[21] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[22] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[23] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[24] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[25] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[26] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[27] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[28] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[29] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[2] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[30] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[31] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[3] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[4] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[5] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[6] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[7] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[8] ; |
| wire \u_riscv_top.wbd_dmem_adr_o[9] ; |
| wire \u_riscv_top.wbd_dmem_bl_o[0] ; |
| wire \u_riscv_top.wbd_dmem_bl_o[1] ; |
| wire \u_riscv_top.wbd_dmem_bl_o[2] ; |
| wire \u_riscv_top.wbd_dmem_bry_o ; |
| wire \u_riscv_top.wbd_dmem_dat_i[0] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[10] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[11] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[12] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[13] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[14] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[15] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[16] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[17] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[18] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[19] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[1] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[20] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[21] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[22] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[23] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[24] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[25] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[26] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[27] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[28] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[29] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[2] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[30] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[31] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[3] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[4] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[5] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[6] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[7] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[8] ; |
| wire \u_riscv_top.wbd_dmem_dat_i[9] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[0] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[10] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[11] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[12] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[13] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[14] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[15] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[16] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[17] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[18] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[19] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[1] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[20] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[21] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[22] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[23] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[24] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[25] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[26] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[27] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[28] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[29] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[2] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[30] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[31] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[3] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[4] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[5] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[6] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[7] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[8] ; |
| wire \u_riscv_top.wbd_dmem_dat_o[9] ; |
| wire \u_riscv_top.wbd_dmem_err_i ; |
| wire \u_riscv_top.wbd_dmem_lack_i ; |
| wire \u_riscv_top.wbd_dmem_sel_o[0] ; |
| wire \u_riscv_top.wbd_dmem_sel_o[1] ; |
| wire \u_riscv_top.wbd_dmem_sel_o[2] ; |
| wire \u_riscv_top.wbd_dmem_sel_o[3] ; |
| wire \u_riscv_top.wbd_dmem_stb_o ; |
| wire \u_riscv_top.wbd_dmem_we_o ; |
| wire \uart_rst_n[0] ; |
| wire \uart_rst_n[1] ; |
| wire \uart_rxd[0] ; |
| wire \uart_rxd[1] ; |
| wire \uart_txd[0] ; |
| wire \uart_txd[1] ; |
| wire uartm_rxd; |
| wire uartm_txd; |
| wire usb_clk; |
| wire usb_dn_i; |
| wire usb_dn_o; |
| wire usb_dp_i; |
| wire usb_dp_o; |
| wire usb_intr_o; |
| wire usb_oen; |
| wire usb_rst_n; |
| wire wbd_clk_int; |
| wire wbd_clk_peri_rp; |
| wire wbd_clk_peri_skew; |
| wire wbd_clk_pinmux_rp; |
| wire wbd_clk_pinmux_skew; |
| wire wbd_clk_qspi_rp; |
| wire wbd_clk_spi; |
| wire wbd_clk_uart_rp; |
| wire wbd_clk_uart_skew; |
| wire wbd_clk_wh; |
| wire wbd_clk_wi_skew; |
| wire wbd_glbl_ack_i; |
| wire \wbd_glbl_adr_o[0] ; |
| wire \wbd_glbl_adr_o[10] ; |
| wire \wbd_glbl_adr_o[1] ; |
| wire \wbd_glbl_adr_o[2] ; |
| wire \wbd_glbl_adr_o[3] ; |
| wire \wbd_glbl_adr_o[4] ; |
| wire \wbd_glbl_adr_o[5] ; |
| wire \wbd_glbl_adr_o[6] ; |
| wire \wbd_glbl_adr_o[7] ; |
| wire \wbd_glbl_adr_o[8] ; |
| wire \wbd_glbl_adr_o[9] ; |
| wire wbd_glbl_cyc_o; |
| wire \wbd_glbl_dat_i[0] ; |
| wire \wbd_glbl_dat_i[10] ; |
| wire \wbd_glbl_dat_i[11] ; |
| wire \wbd_glbl_dat_i[12] ; |
| wire \wbd_glbl_dat_i[13] ; |
| wire \wbd_glbl_dat_i[14] ; |
| wire \wbd_glbl_dat_i[15] ; |
| wire \wbd_glbl_dat_i[16] ; |
| wire \wbd_glbl_dat_i[17] ; |
| wire \wbd_glbl_dat_i[18] ; |
| wire \wbd_glbl_dat_i[19] ; |
| wire \wbd_glbl_dat_i[1] ; |
| wire \wbd_glbl_dat_i[20] ; |
| wire \wbd_glbl_dat_i[21] ; |
| wire \wbd_glbl_dat_i[22] ; |
| wire \wbd_glbl_dat_i[23] ; |
| wire \wbd_glbl_dat_i[24] ; |
| wire \wbd_glbl_dat_i[25] ; |
| wire \wbd_glbl_dat_i[26] ; |
| wire \wbd_glbl_dat_i[27] ; |
| wire \wbd_glbl_dat_i[28] ; |
| wire \wbd_glbl_dat_i[29] ; |
| wire \wbd_glbl_dat_i[2] ; |
| wire \wbd_glbl_dat_i[30] ; |
| wire \wbd_glbl_dat_i[31] ; |
| wire \wbd_glbl_dat_i[3] ; |
| wire \wbd_glbl_dat_i[4] ; |
| wire \wbd_glbl_dat_i[5] ; |
| wire \wbd_glbl_dat_i[6] ; |
| wire \wbd_glbl_dat_i[7] ; |
| wire \wbd_glbl_dat_i[8] ; |
| wire \wbd_glbl_dat_i[9] ; |
| wire \wbd_glbl_dat_o[0] ; |
| wire \wbd_glbl_dat_o[10] ; |
| wire \wbd_glbl_dat_o[11] ; |
| wire \wbd_glbl_dat_o[12] ; |
| wire \wbd_glbl_dat_o[13] ; |
| wire \wbd_glbl_dat_o[14] ; |
| wire \wbd_glbl_dat_o[15] ; |
| wire \wbd_glbl_dat_o[16] ; |
| wire \wbd_glbl_dat_o[17] ; |
| wire \wbd_glbl_dat_o[18] ; |
| wire \wbd_glbl_dat_o[19] ; |
| wire \wbd_glbl_dat_o[1] ; |
| wire \wbd_glbl_dat_o[20] ; |
| wire \wbd_glbl_dat_o[21] ; |
| wire \wbd_glbl_dat_o[22] ; |
| wire \wbd_glbl_dat_o[23] ; |
| wire \wbd_glbl_dat_o[24] ; |
| wire \wbd_glbl_dat_o[25] ; |
| wire \wbd_glbl_dat_o[26] ; |
| wire \wbd_glbl_dat_o[27] ; |
| wire \wbd_glbl_dat_o[28] ; |
| wire \wbd_glbl_dat_o[29] ; |
| wire \wbd_glbl_dat_o[2] ; |
| wire \wbd_glbl_dat_o[30] ; |
| wire \wbd_glbl_dat_o[31] ; |
| wire \wbd_glbl_dat_o[3] ; |
| wire \wbd_glbl_dat_o[4] ; |
| wire \wbd_glbl_dat_o[5] ; |
| wire \wbd_glbl_dat_o[6] ; |
| wire \wbd_glbl_dat_o[7] ; |
| wire \wbd_glbl_dat_o[8] ; |
| wire \wbd_glbl_dat_o[9] ; |
| wire \wbd_glbl_sel_o[0] ; |
| wire \wbd_glbl_sel_o[1] ; |
| wire \wbd_glbl_sel_o[2] ; |
| wire \wbd_glbl_sel_o[3] ; |
| wire wbd_glbl_stb_o; |
| wire wbd_glbl_we_o; |
| wire wbd_int_ack_o; |
| wire \wbd_int_adr_i[0] ; |
| wire \wbd_int_adr_i[10] ; |
| wire \wbd_int_adr_i[11] ; |
| wire \wbd_int_adr_i[12] ; |
| wire \wbd_int_adr_i[13] ; |
| wire \wbd_int_adr_i[14] ; |
| wire \wbd_int_adr_i[15] ; |
| wire \wbd_int_adr_i[16] ; |
| wire \wbd_int_adr_i[17] ; |
| wire \wbd_int_adr_i[18] ; |
| wire \wbd_int_adr_i[19] ; |
| wire \wbd_int_adr_i[1] ; |
| wire \wbd_int_adr_i[20] ; |
| wire \wbd_int_adr_i[21] ; |
| wire \wbd_int_adr_i[22] ; |
| wire \wbd_int_adr_i[23] ; |
| wire \wbd_int_adr_i[24] ; |
| wire \wbd_int_adr_i[25] ; |
| wire \wbd_int_adr_i[26] ; |
| wire \wbd_int_adr_i[27] ; |
| wire \wbd_int_adr_i[28] ; |
| wire \wbd_int_adr_i[29] ; |
| wire \wbd_int_adr_i[2] ; |
| wire \wbd_int_adr_i[30] ; |
| wire \wbd_int_adr_i[31] ; |
| wire \wbd_int_adr_i[3] ; |
| wire \wbd_int_adr_i[4] ; |
| wire \wbd_int_adr_i[5] ; |
| wire \wbd_int_adr_i[6] ; |
| wire \wbd_int_adr_i[7] ; |
| wire \wbd_int_adr_i[8] ; |
| wire \wbd_int_adr_i[9] ; |
| wire wbd_int_cyc_i; |
| wire \wbd_int_dat_i[0] ; |
| wire \wbd_int_dat_i[10] ; |
| wire \wbd_int_dat_i[11] ; |
| wire \wbd_int_dat_i[12] ; |
| wire \wbd_int_dat_i[13] ; |
| wire \wbd_int_dat_i[14] ; |
| wire \wbd_int_dat_i[15] ; |
| wire \wbd_int_dat_i[16] ; |
| wire \wbd_int_dat_i[17] ; |
| wire \wbd_int_dat_i[18] ; |
| wire \wbd_int_dat_i[19] ; |
| wire \wbd_int_dat_i[1] ; |
| wire \wbd_int_dat_i[20] ; |
| wire \wbd_int_dat_i[21] ; |
| wire \wbd_int_dat_i[22] ; |
| wire \wbd_int_dat_i[23] ; |
| wire \wbd_int_dat_i[24] ; |
| wire \wbd_int_dat_i[25] ; |
| wire \wbd_int_dat_i[26] ; |
| wire \wbd_int_dat_i[27] ; |
| wire \wbd_int_dat_i[28] ; |
| wire \wbd_int_dat_i[29] ; |
| wire \wbd_int_dat_i[2] ; |
| wire \wbd_int_dat_i[30] ; |
| wire \wbd_int_dat_i[31] ; |
| wire \wbd_int_dat_i[3] ; |
| wire \wbd_int_dat_i[4] ; |
| wire \wbd_int_dat_i[5] ; |
| wire \wbd_int_dat_i[6] ; |
| wire \wbd_int_dat_i[7] ; |
| wire \wbd_int_dat_i[8] ; |
| wire \wbd_int_dat_i[9] ; |
| wire \wbd_int_dat_o[0] ; |
| wire \wbd_int_dat_o[10] ; |
| wire \wbd_int_dat_o[11] ; |
| wire \wbd_int_dat_o[12] ; |
| wire \wbd_int_dat_o[13] ; |
| wire \wbd_int_dat_o[14] ; |
| wire \wbd_int_dat_o[15] ; |
| wire \wbd_int_dat_o[16] ; |
| wire \wbd_int_dat_o[17] ; |
| wire \wbd_int_dat_o[18] ; |
| wire \wbd_int_dat_o[19] ; |
| wire \wbd_int_dat_o[1] ; |
| wire \wbd_int_dat_o[20] ; |
| wire \wbd_int_dat_o[21] ; |
| wire \wbd_int_dat_o[22] ; |
| wire \wbd_int_dat_o[23] ; |
| wire \wbd_int_dat_o[24] ; |
| wire \wbd_int_dat_o[25] ; |
| wire \wbd_int_dat_o[26] ; |
| wire \wbd_int_dat_o[27] ; |
| wire \wbd_int_dat_o[28] ; |
| wire \wbd_int_dat_o[29] ; |
| wire \wbd_int_dat_o[2] ; |
| wire \wbd_int_dat_o[30] ; |
| wire \wbd_int_dat_o[31] ; |
| wire \wbd_int_dat_o[3] ; |
| wire \wbd_int_dat_o[4] ; |
| wire \wbd_int_dat_o[5] ; |
| wire \wbd_int_dat_o[6] ; |
| wire \wbd_int_dat_o[7] ; |
| wire \wbd_int_dat_o[8] ; |
| wire \wbd_int_dat_o[9] ; |
| wire wbd_int_err_o; |
| wire \wbd_int_sel_i[0] ; |
| wire \wbd_int_sel_i[1] ; |
| wire \wbd_int_sel_i[2] ; |
| wire \wbd_int_sel_i[3] ; |
| wire wbd_int_stb_i; |
| wire wbd_int_we_i; |
| wire wbd_pll_rst_n; |
| wire wbd_spim_ack_i; |
| wire \wbd_spim_adr_o[0] ; |
| wire \wbd_spim_adr_o[10] ; |
| wire \wbd_spim_adr_o[11] ; |
| wire \wbd_spim_adr_o[12] ; |
| wire \wbd_spim_adr_o[13] ; |
| wire \wbd_spim_adr_o[14] ; |
| wire \wbd_spim_adr_o[15] ; |
| wire \wbd_spim_adr_o[16] ; |
| wire \wbd_spim_adr_o[17] ; |
| wire \wbd_spim_adr_o[18] ; |
| wire \wbd_spim_adr_o[19] ; |
| wire \wbd_spim_adr_o[1] ; |
| wire \wbd_spim_adr_o[20] ; |
| wire \wbd_spim_adr_o[21] ; |
| wire \wbd_spim_adr_o[22] ; |
| wire \wbd_spim_adr_o[23] ; |
| wire \wbd_spim_adr_o[24] ; |
| wire \wbd_spim_adr_o[25] ; |
| wire \wbd_spim_adr_o[26] ; |
| wire \wbd_spim_adr_o[27] ; |
| wire \wbd_spim_adr_o[28] ; |
| wire \wbd_spim_adr_o[29] ; |
| wire \wbd_spim_adr_o[2] ; |
| wire \wbd_spim_adr_o[30] ; |
| wire \wbd_spim_adr_o[31] ; |
| wire \wbd_spim_adr_o[3] ; |
| wire \wbd_spim_adr_o[4] ; |
| wire \wbd_spim_adr_o[5] ; |
| wire \wbd_spim_adr_o[6] ; |
| wire \wbd_spim_adr_o[7] ; |
| wire \wbd_spim_adr_o[8] ; |
| wire \wbd_spim_adr_o[9] ; |
| wire \wbd_spim_bl_o[0] ; |
| wire \wbd_spim_bl_o[1] ; |
| wire \wbd_spim_bl_o[2] ; |
| wire \wbd_spim_bl_o[3] ; |
| wire \wbd_spim_bl_o[4] ; |
| wire \wbd_spim_bl_o[5] ; |
| wire \wbd_spim_bl_o[6] ; |
| wire \wbd_spim_bl_o[7] ; |
| wire \wbd_spim_bl_o[8] ; |
| wire \wbd_spim_bl_o[9] ; |
| wire wbd_spim_bry_o; |
| wire wbd_spim_cyc_o; |
| wire \wbd_spim_dat_i[0] ; |
| wire \wbd_spim_dat_i[10] ; |
| wire \wbd_spim_dat_i[11] ; |
| wire \wbd_spim_dat_i[12] ; |
| wire \wbd_spim_dat_i[13] ; |
| wire \wbd_spim_dat_i[14] ; |
| wire \wbd_spim_dat_i[15] ; |
| wire \wbd_spim_dat_i[16] ; |
| wire \wbd_spim_dat_i[17] ; |
| wire \wbd_spim_dat_i[18] ; |
| wire \wbd_spim_dat_i[19] ; |
| wire \wbd_spim_dat_i[1] ; |
| wire \wbd_spim_dat_i[20] ; |
| wire \wbd_spim_dat_i[21] ; |
| wire \wbd_spim_dat_i[22] ; |
| wire \wbd_spim_dat_i[23] ; |
| wire \wbd_spim_dat_i[24] ; |
| wire \wbd_spim_dat_i[25] ; |
| wire \wbd_spim_dat_i[26] ; |
| wire \wbd_spim_dat_i[27] ; |
| wire \wbd_spim_dat_i[28] ; |
| wire \wbd_spim_dat_i[29] ; |
| wire \wbd_spim_dat_i[2] ; |
| wire \wbd_spim_dat_i[30] ; |
| wire \wbd_spim_dat_i[31] ; |
| wire \wbd_spim_dat_i[3] ; |
| wire \wbd_spim_dat_i[4] ; |
| wire \wbd_spim_dat_i[5] ; |
| wire \wbd_spim_dat_i[6] ; |
| wire \wbd_spim_dat_i[7] ; |
| wire \wbd_spim_dat_i[8] ; |
| wire \wbd_spim_dat_i[9] ; |
| wire \wbd_spim_dat_o[0] ; |
| wire \wbd_spim_dat_o[10] ; |
| wire \wbd_spim_dat_o[11] ; |
| wire \wbd_spim_dat_o[12] ; |
| wire \wbd_spim_dat_o[13] ; |
| wire \wbd_spim_dat_o[14] ; |
| wire \wbd_spim_dat_o[15] ; |
| wire \wbd_spim_dat_o[16] ; |
| wire \wbd_spim_dat_o[17] ; |
| wire \wbd_spim_dat_o[18] ; |
| wire \wbd_spim_dat_o[19] ; |
| wire \wbd_spim_dat_o[1] ; |
| wire \wbd_spim_dat_o[20] ; |
| wire \wbd_spim_dat_o[21] ; |
| wire \wbd_spim_dat_o[22] ; |
| wire \wbd_spim_dat_o[23] ; |
| wire \wbd_spim_dat_o[24] ; |
| wire \wbd_spim_dat_o[25] ; |
| wire \wbd_spim_dat_o[26] ; |
| wire \wbd_spim_dat_o[27] ; |
| wire \wbd_spim_dat_o[28] ; |
| wire \wbd_spim_dat_o[29] ; |
| wire \wbd_spim_dat_o[2] ; |
| wire \wbd_spim_dat_o[30] ; |
| wire \wbd_spim_dat_o[31] ; |
| wire \wbd_spim_dat_o[3] ; |
| wire \wbd_spim_dat_o[4] ; |
| wire \wbd_spim_dat_o[5] ; |
| wire \wbd_spim_dat_o[6] ; |
| wire \wbd_spim_dat_o[7] ; |
| wire \wbd_spim_dat_o[8] ; |
| wire \wbd_spim_dat_o[9] ; |
| wire wbd_spim_err_i; |
| wire wbd_spim_lack_i; |
| wire \wbd_spim_sel_o[0] ; |
| wire \wbd_spim_sel_o[1] ; |
| wire \wbd_spim_sel_o[2] ; |
| wire \wbd_spim_sel_o[3] ; |
| wire wbd_spim_stb_o; |
| wire wbd_spim_we_o; |
| wire wbd_uart_ack_i; |
| wire \wbd_uart_adr_o[0] ; |
| wire \wbd_uart_adr_o[1] ; |
| wire \wbd_uart_adr_o[2] ; |
| wire \wbd_uart_adr_o[3] ; |
| wire \wbd_uart_adr_o[4] ; |
| wire \wbd_uart_adr_o[5] ; |
| wire \wbd_uart_adr_o[6] ; |
| wire \wbd_uart_adr_o[7] ; |
| wire \wbd_uart_adr_o[8] ; |
| wire wbd_uart_cyc_o; |
| wire \wbd_uart_dat_i[0] ; |
| wire \wbd_uart_dat_i[10] ; |
| wire \wbd_uart_dat_i[11] ; |
| wire \wbd_uart_dat_i[12] ; |
| wire \wbd_uart_dat_i[13] ; |
| wire \wbd_uart_dat_i[14] ; |
| wire \wbd_uart_dat_i[15] ; |
| wire \wbd_uart_dat_i[16] ; |
| wire \wbd_uart_dat_i[17] ; |
| wire \wbd_uart_dat_i[18] ; |
| wire \wbd_uart_dat_i[19] ; |
| wire \wbd_uart_dat_i[1] ; |
| wire \wbd_uart_dat_i[20] ; |
| wire \wbd_uart_dat_i[21] ; |
| wire \wbd_uart_dat_i[22] ; |
| wire \wbd_uart_dat_i[23] ; |
| wire \wbd_uart_dat_i[24] ; |
| wire \wbd_uart_dat_i[25] ; |
| wire \wbd_uart_dat_i[26] ; |
| wire \wbd_uart_dat_i[27] ; |
| wire \wbd_uart_dat_i[28] ; |
| wire \wbd_uart_dat_i[29] ; |
| wire \wbd_uart_dat_i[2] ; |
| wire \wbd_uart_dat_i[30] ; |
| wire \wbd_uart_dat_i[31] ; |
| wire \wbd_uart_dat_i[3] ; |
| wire \wbd_uart_dat_i[4] ; |
| wire \wbd_uart_dat_i[5] ; |
| wire \wbd_uart_dat_i[6] ; |
| wire \wbd_uart_dat_i[7] ; |
| wire \wbd_uart_dat_i[8] ; |
| wire \wbd_uart_dat_i[9] ; |
| wire \wbd_uart_dat_o[0] ; |
| wire \wbd_uart_dat_o[10] ; |
| wire \wbd_uart_dat_o[11] ; |
| wire \wbd_uart_dat_o[12] ; |
| wire \wbd_uart_dat_o[13] ; |
| wire \wbd_uart_dat_o[14] ; |
| wire \wbd_uart_dat_o[15] ; |
| wire \wbd_uart_dat_o[16] ; |
| wire \wbd_uart_dat_o[17] ; |
| wire \wbd_uart_dat_o[18] ; |
| wire \wbd_uart_dat_o[19] ; |
| wire \wbd_uart_dat_o[1] ; |
| wire \wbd_uart_dat_o[20] ; |
| wire \wbd_uart_dat_o[21] ; |
| wire \wbd_uart_dat_o[22] ; |
| wire \wbd_uart_dat_o[23] ; |
| wire \wbd_uart_dat_o[24] ; |
| wire \wbd_uart_dat_o[25] ; |
| wire \wbd_uart_dat_o[26] ; |
| wire \wbd_uart_dat_o[27] ; |
| wire \wbd_uart_dat_o[28] ; |
| wire \wbd_uart_dat_o[29] ; |
| wire \wbd_uart_dat_o[2] ; |
| wire \wbd_uart_dat_o[30] ; |
| wire \wbd_uart_dat_o[31] ; |
| wire \wbd_uart_dat_o[3] ; |
| wire \wbd_uart_dat_o[4] ; |
| wire \wbd_uart_dat_o[5] ; |
| wire \wbd_uart_dat_o[6] ; |
| wire \wbd_uart_dat_o[7] ; |
| wire \wbd_uart_dat_o[8] ; |
| wire \wbd_uart_dat_o[9] ; |
| wire \wbd_uart_sel_o[0] ; |
| wire \wbd_uart_sel_o[1] ; |
| wire \wbd_uart_sel_o[2] ; |
| wire \wbd_uart_sel_o[3] ; |
| wire wbd_uart_stb_o; |
| wire wbd_uart_we_o; |
| wire wbs_ack_int_o; |
| wire \wbs_dat_int_o[0] ; |
| wire \wbs_dat_int_o[10] ; |
| wire \wbs_dat_int_o[11] ; |
| wire \wbs_dat_int_o[12] ; |
| wire \wbs_dat_int_o[13] ; |
| wire \wbs_dat_int_o[14] ; |
| wire \wbs_dat_int_o[15] ; |
| wire \wbs_dat_int_o[16] ; |
| wire \wbs_dat_int_o[17] ; |
| wire \wbs_dat_int_o[18] ; |
| wire \wbs_dat_int_o[19] ; |
| wire \wbs_dat_int_o[1] ; |
| wire \wbs_dat_int_o[20] ; |
| wire \wbs_dat_int_o[21] ; |
| wire \wbs_dat_int_o[22] ; |
| wire \wbs_dat_int_o[23] ; |
| wire \wbs_dat_int_o[24] ; |
| wire \wbs_dat_int_o[25] ; |
| wire \wbs_dat_int_o[26] ; |
| wire \wbs_dat_int_o[27] ; |
| wire \wbs_dat_int_o[28] ; |
| wire \wbs_dat_int_o[29] ; |
| wire \wbs_dat_int_o[2] ; |
| wire \wbs_dat_int_o[30] ; |
| wire \wbs_dat_int_o[31] ; |
| wire \wbs_dat_int_o[3] ; |
| wire \wbs_dat_int_o[4] ; |
| wire \wbs_dat_int_o[5] ; |
| wire \wbs_dat_int_o[6] ; |
| wire \wbs_dat_int_o[7] ; |
| wire \wbs_dat_int_o[8] ; |
| wire \wbs_dat_int_o[9] ; |
| wire xtal_clk; |
| |
| dac_top u_4x8bit_dac (.Vout0(analog_io[15]), |
| .Vout1(analog_io[16]), |
| .Vout2(analog_io[17]), |
| .Vout3(analog_io[18]), |
| .Vref(analog_io[23]), |
| .vccd1(vdda1), |
| .vssd1(vssa1), |
| .DIn0({\cfg_dac0_mux_sel[7] , |
| \cfg_dac0_mux_sel[6] , |
| \cfg_dac0_mux_sel[5] , |
| \cfg_dac0_mux_sel[4] , |
| \cfg_dac0_mux_sel[3] , |
| \cfg_dac0_mux_sel[2] , |
| \cfg_dac0_mux_sel[1] , |
| \cfg_dac0_mux_sel[0] }), |
| .DIn1({\cfg_dac1_mux_sel[7] , |
| \cfg_dac1_mux_sel[6] , |
| \cfg_dac1_mux_sel[5] , |
| \cfg_dac1_mux_sel[4] , |
| \cfg_dac1_mux_sel[3] , |
| \cfg_dac1_mux_sel[2] , |
| \cfg_dac1_mux_sel[1] , |
| \cfg_dac1_mux_sel[0] }), |
| .DIn2({\cfg_dac2_mux_sel[7] , |
| \cfg_dac2_mux_sel[6] , |
| \cfg_dac2_mux_sel[5] , |
| \cfg_dac2_mux_sel[4] , |
| \cfg_dac2_mux_sel[3] , |
| \cfg_dac2_mux_sel[2] , |
| \cfg_dac2_mux_sel[1] , |
| \cfg_dac2_mux_sel[0] }), |
| .DIn3({\cfg_dac3_mux_sel[7] , |
| \cfg_dac3_mux_sel[6] , |
| \cfg_dac3_mux_sel[5] , |
| \cfg_dac3_mux_sel[4] , |
| \cfg_dac3_mux_sel[3] , |
| \cfg_dac3_mux_sel[2] , |
| \cfg_dac3_mux_sel[1] , |
| \cfg_dac3_mux_sel[0] })); |
| aes_top u_aes (.dmem_cmd(\u_riscv_top.aes_dmem_cmd ), |
| .dmem_req(\u_riscv_top.aes_dmem_req ), |
| .dmem_req_ack(\u_riscv_top.aes_dmem_req_ack ), |
| .mclk(cpu_clk_aes_skew), |
| .rst_n(\u_riscv_top.cpu_intf_rst_n ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(\u_riscv_top.cpu_clk_aes ), |
| .wbd_clk_out(cpu_clk_aes_skew), |
| .cfg_cska({\cfg_ccska_aes_rp[3] , |
| \cfg_ccska_aes_rp[2] , |
| \cfg_ccska_aes_rp[1] , |
| \cfg_ccska_aes_rp[0] }), |
| .dmem_addr({\u_riscv_top.aes_dmem_addr[6] , |
| \u_riscv_top.aes_dmem_addr[5] , |
| \u_riscv_top.aes_dmem_addr[4] , |
| \u_riscv_top.aes_dmem_addr[3] , |
| \u_riscv_top.aes_dmem_addr[2] , |
| \u_riscv_top.aes_dmem_addr[1] , |
| \u_riscv_top.aes_dmem_addr[0] }), |
| .dmem_rdata({\u_riscv_top.aes_dmem_rdata[31] , |
| \u_riscv_top.aes_dmem_rdata[30] , |
| \u_riscv_top.aes_dmem_rdata[29] , |
| \u_riscv_top.aes_dmem_rdata[28] , |
| \u_riscv_top.aes_dmem_rdata[27] , |
| \u_riscv_top.aes_dmem_rdata[26] , |
| \u_riscv_top.aes_dmem_rdata[25] , |
| \u_riscv_top.aes_dmem_rdata[24] , |
| \u_riscv_top.aes_dmem_rdata[23] , |
| \u_riscv_top.aes_dmem_rdata[22] , |
| \u_riscv_top.aes_dmem_rdata[21] , |
| \u_riscv_top.aes_dmem_rdata[20] , |
| \u_riscv_top.aes_dmem_rdata[19] , |
| \u_riscv_top.aes_dmem_rdata[18] , |
| \u_riscv_top.aes_dmem_rdata[17] , |
| \u_riscv_top.aes_dmem_rdata[16] , |
| \u_riscv_top.aes_dmem_rdata[15] , |
| \u_riscv_top.aes_dmem_rdata[14] , |
| \u_riscv_top.aes_dmem_rdata[13] , |
| \u_riscv_top.aes_dmem_rdata[12] , |
| \u_riscv_top.aes_dmem_rdata[11] , |
| \u_riscv_top.aes_dmem_rdata[10] , |
| \u_riscv_top.aes_dmem_rdata[9] , |
| \u_riscv_top.aes_dmem_rdata[8] , |
| \u_riscv_top.aes_dmem_rdata[7] , |
| \u_riscv_top.aes_dmem_rdata[6] , |
| \u_riscv_top.aes_dmem_rdata[5] , |
| \u_riscv_top.aes_dmem_rdata[4] , |
| \u_riscv_top.aes_dmem_rdata[3] , |
| \u_riscv_top.aes_dmem_rdata[2] , |
| \u_riscv_top.aes_dmem_rdata[1] , |
| \u_riscv_top.aes_dmem_rdata[0] }), |
| .dmem_resp({\u_riscv_top.aes_dmem_resp[1] , |
| \u_riscv_top.aes_dmem_resp[0] }), |
| .dmem_wdata({\u_riscv_top.aes_dmem_wdata[31] , |
| \u_riscv_top.aes_dmem_wdata[30] , |
| \u_riscv_top.aes_dmem_wdata[29] , |
| \u_riscv_top.aes_dmem_wdata[28] , |
| \u_riscv_top.aes_dmem_wdata[27] , |
| \u_riscv_top.aes_dmem_wdata[26] , |
| \u_riscv_top.aes_dmem_wdata[25] , |
| \u_riscv_top.aes_dmem_wdata[24] , |
| \u_riscv_top.aes_dmem_wdata[23] , |
| \u_riscv_top.aes_dmem_wdata[22] , |
| \u_riscv_top.aes_dmem_wdata[21] , |
| \u_riscv_top.aes_dmem_wdata[20] , |
| \u_riscv_top.aes_dmem_wdata[19] , |
| \u_riscv_top.aes_dmem_wdata[18] , |
| \u_riscv_top.aes_dmem_wdata[17] , |
| \u_riscv_top.aes_dmem_wdata[16] , |
| \u_riscv_top.aes_dmem_wdata[15] , |
| \u_riscv_top.aes_dmem_wdata[14] , |
| \u_riscv_top.aes_dmem_wdata[13] , |
| \u_riscv_top.aes_dmem_wdata[12] , |
| \u_riscv_top.aes_dmem_wdata[11] , |
| \u_riscv_top.aes_dmem_wdata[10] , |
| \u_riscv_top.aes_dmem_wdata[9] , |
| \u_riscv_top.aes_dmem_wdata[8] , |
| \u_riscv_top.aes_dmem_wdata[7] , |
| \u_riscv_top.aes_dmem_wdata[6] , |
| \u_riscv_top.aes_dmem_wdata[5] , |
| \u_riscv_top.aes_dmem_wdata[4] , |
| \u_riscv_top.aes_dmem_wdata[3] , |
| \u_riscv_top.aes_dmem_wdata[2] , |
| \u_riscv_top.aes_dmem_wdata[1] , |
| \u_riscv_top.aes_dmem_wdata[0] }), |
| .dmem_width({\u_riscv_top.aes_dmem_width[1] , |
| \u_riscv_top.aes_dmem_width[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb (.csb0(\u_riscv_top.dcache_mem_csb0 ), |
| .csb1(\u_riscv_top.dcache_mem_csb1 ), |
| .web0(\u_riscv_top.dcache_mem_web0 ), |
| .clk0(\u_riscv_top.dcache_mem_clk0 ), |
| .clk1(\u_riscv_top.dcache_mem_clk1 ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\u_riscv_top.dcache_mem_addr0[8] , |
| \u_riscv_top.dcache_mem_addr0[7] , |
| \u_riscv_top.dcache_mem_addr0[6] , |
| \u_riscv_top.dcache_mem_addr0[5] , |
| \u_riscv_top.dcache_mem_addr0[4] , |
| \u_riscv_top.dcache_mem_addr0[3] , |
| \u_riscv_top.dcache_mem_addr0[2] , |
| \u_riscv_top.dcache_mem_addr0[1] , |
| \u_riscv_top.dcache_mem_addr0[0] }), |
| .addr1({\u_riscv_top.dcache_mem_addr1[8] , |
| \u_riscv_top.dcache_mem_addr1[7] , |
| \u_riscv_top.dcache_mem_addr1[6] , |
| \u_riscv_top.dcache_mem_addr1[5] , |
| \u_riscv_top.dcache_mem_addr1[4] , |
| \u_riscv_top.dcache_mem_addr1[3] , |
| \u_riscv_top.dcache_mem_addr1[2] , |
| \u_riscv_top.dcache_mem_addr1[1] , |
| \u_riscv_top.dcache_mem_addr1[0] }), |
| .din0({\u_riscv_top.dcache_mem_din0[31] , |
| \u_riscv_top.dcache_mem_din0[30] , |
| \u_riscv_top.dcache_mem_din0[29] , |
| \u_riscv_top.dcache_mem_din0[28] , |
| \u_riscv_top.dcache_mem_din0[27] , |
| \u_riscv_top.dcache_mem_din0[26] , |
| \u_riscv_top.dcache_mem_din0[25] , |
| \u_riscv_top.dcache_mem_din0[24] , |
| \u_riscv_top.dcache_mem_din0[23] , |
| \u_riscv_top.dcache_mem_din0[22] , |
| \u_riscv_top.dcache_mem_din0[21] , |
| \u_riscv_top.dcache_mem_din0[20] , |
| \u_riscv_top.dcache_mem_din0[19] , |
| \u_riscv_top.dcache_mem_din0[18] , |
| \u_riscv_top.dcache_mem_din0[17] , |
| \u_riscv_top.dcache_mem_din0[16] , |
| \u_riscv_top.dcache_mem_din0[15] , |
| \u_riscv_top.dcache_mem_din0[14] , |
| \u_riscv_top.dcache_mem_din0[13] , |
| \u_riscv_top.dcache_mem_din0[12] , |
| \u_riscv_top.dcache_mem_din0[11] , |
| \u_riscv_top.dcache_mem_din0[10] , |
| \u_riscv_top.dcache_mem_din0[9] , |
| \u_riscv_top.dcache_mem_din0[8] , |
| \u_riscv_top.dcache_mem_din0[7] , |
| \u_riscv_top.dcache_mem_din0[6] , |
| \u_riscv_top.dcache_mem_din0[5] , |
| \u_riscv_top.dcache_mem_din0[4] , |
| \u_riscv_top.dcache_mem_din0[3] , |
| \u_riscv_top.dcache_mem_din0[2] , |
| \u_riscv_top.dcache_mem_din0[1] , |
| \u_riscv_top.dcache_mem_din0[0] }), |
| .dout0({\u_riscv_top.dcache_mem_dout0[31] , |
| \u_riscv_top.dcache_mem_dout0[30] , |
| \u_riscv_top.dcache_mem_dout0[29] , |
| \u_riscv_top.dcache_mem_dout0[28] , |
| \u_riscv_top.dcache_mem_dout0[27] , |
| \u_riscv_top.dcache_mem_dout0[26] , |
| \u_riscv_top.dcache_mem_dout0[25] , |
| \u_riscv_top.dcache_mem_dout0[24] , |
| \u_riscv_top.dcache_mem_dout0[23] , |
| \u_riscv_top.dcache_mem_dout0[22] , |
| \u_riscv_top.dcache_mem_dout0[21] , |
| \u_riscv_top.dcache_mem_dout0[20] , |
| \u_riscv_top.dcache_mem_dout0[19] , |
| \u_riscv_top.dcache_mem_dout0[18] , |
| \u_riscv_top.dcache_mem_dout0[17] , |
| \u_riscv_top.dcache_mem_dout0[16] , |
| \u_riscv_top.dcache_mem_dout0[15] , |
| \u_riscv_top.dcache_mem_dout0[14] , |
| \u_riscv_top.dcache_mem_dout0[13] , |
| \u_riscv_top.dcache_mem_dout0[12] , |
| \u_riscv_top.dcache_mem_dout0[11] , |
| \u_riscv_top.dcache_mem_dout0[10] , |
| \u_riscv_top.dcache_mem_dout0[9] , |
| \u_riscv_top.dcache_mem_dout0[8] , |
| \u_riscv_top.dcache_mem_dout0[7] , |
| \u_riscv_top.dcache_mem_dout0[6] , |
| \u_riscv_top.dcache_mem_dout0[5] , |
| \u_riscv_top.dcache_mem_dout0[4] , |
| \u_riscv_top.dcache_mem_dout0[3] , |
| \u_riscv_top.dcache_mem_dout0[2] , |
| \u_riscv_top.dcache_mem_dout0[1] , |
| \u_riscv_top.dcache_mem_dout0[0] }), |
| .dout1({\u_riscv_top.dcache_mem_dout1[31] , |
| \u_riscv_top.dcache_mem_dout1[30] , |
| \u_riscv_top.dcache_mem_dout1[29] , |
| \u_riscv_top.dcache_mem_dout1[28] , |
| \u_riscv_top.dcache_mem_dout1[27] , |
| \u_riscv_top.dcache_mem_dout1[26] , |
| \u_riscv_top.dcache_mem_dout1[25] , |
| \u_riscv_top.dcache_mem_dout1[24] , |
| \u_riscv_top.dcache_mem_dout1[23] , |
| \u_riscv_top.dcache_mem_dout1[22] , |
| \u_riscv_top.dcache_mem_dout1[21] , |
| \u_riscv_top.dcache_mem_dout1[20] , |
| \u_riscv_top.dcache_mem_dout1[19] , |
| \u_riscv_top.dcache_mem_dout1[18] , |
| \u_riscv_top.dcache_mem_dout1[17] , |
| \u_riscv_top.dcache_mem_dout1[16] , |
| \u_riscv_top.dcache_mem_dout1[15] , |
| \u_riscv_top.dcache_mem_dout1[14] , |
| \u_riscv_top.dcache_mem_dout1[13] , |
| \u_riscv_top.dcache_mem_dout1[12] , |
| \u_riscv_top.dcache_mem_dout1[11] , |
| \u_riscv_top.dcache_mem_dout1[10] , |
| \u_riscv_top.dcache_mem_dout1[9] , |
| \u_riscv_top.dcache_mem_dout1[8] , |
| \u_riscv_top.dcache_mem_dout1[7] , |
| \u_riscv_top.dcache_mem_dout1[6] , |
| \u_riscv_top.dcache_mem_dout1[5] , |
| \u_riscv_top.dcache_mem_dout1[4] , |
| \u_riscv_top.dcache_mem_dout1[3] , |
| \u_riscv_top.dcache_mem_dout1[2] , |
| \u_riscv_top.dcache_mem_dout1[1] , |
| \u_riscv_top.dcache_mem_dout1[0] }), |
| .wmask0({\u_riscv_top.dcache_mem_wmask0[3] , |
| \u_riscv_top.dcache_mem_wmask0[2] , |
| \u_riscv_top.dcache_mem_wmask0[1] , |
| \u_riscv_top.dcache_mem_wmask0[0] })); |
| fpu_wrapper u_fpu (.dmem_cmd(\u_riscv_top.fpu_dmem_cmd ), |
| .dmem_req(\u_riscv_top.fpu_dmem_req ), |
| .dmem_req_ack(\u_riscv_top.fpu_dmem_req_ack ), |
| .mclk(cpu_clk_fpu_skew), |
| .rst_n(\u_riscv_top.cpu_intf_rst_n ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(\u_riscv_top.cpu_clk_fpu ), |
| .wbd_clk_out(cpu_clk_fpu_skew), |
| .cfg_cska({\cfg_ccska_fpu_rp[3] , |
| \cfg_ccska_fpu_rp[2] , |
| \cfg_ccska_fpu_rp[1] , |
| \cfg_ccska_fpu_rp[0] }), |
| .dmem_addr({\u_riscv_top.fpu_dmem_addr[4] , |
| \u_riscv_top.fpu_dmem_addr[3] , |
| \u_riscv_top.fpu_dmem_addr[2] , |
| \u_riscv_top.fpu_dmem_addr[1] , |
| \u_riscv_top.fpu_dmem_addr[0] }), |
| .dmem_rdata({\u_riscv_top.fpu_dmem_rdata[31] , |
| \u_riscv_top.fpu_dmem_rdata[30] , |
| \u_riscv_top.fpu_dmem_rdata[29] , |
| \u_riscv_top.fpu_dmem_rdata[28] , |
| \u_riscv_top.fpu_dmem_rdata[27] , |
| \u_riscv_top.fpu_dmem_rdata[26] , |
| \u_riscv_top.fpu_dmem_rdata[25] , |
| \u_riscv_top.fpu_dmem_rdata[24] , |
| \u_riscv_top.fpu_dmem_rdata[23] , |
| \u_riscv_top.fpu_dmem_rdata[22] , |
| \u_riscv_top.fpu_dmem_rdata[21] , |
| \u_riscv_top.fpu_dmem_rdata[20] , |
| \u_riscv_top.fpu_dmem_rdata[19] , |
| \u_riscv_top.fpu_dmem_rdata[18] , |
| \u_riscv_top.fpu_dmem_rdata[17] , |
| \u_riscv_top.fpu_dmem_rdata[16] , |
| \u_riscv_top.fpu_dmem_rdata[15] , |
| \u_riscv_top.fpu_dmem_rdata[14] , |
| \u_riscv_top.fpu_dmem_rdata[13] , |
| \u_riscv_top.fpu_dmem_rdata[12] , |
| \u_riscv_top.fpu_dmem_rdata[11] , |
| \u_riscv_top.fpu_dmem_rdata[10] , |
| \u_riscv_top.fpu_dmem_rdata[9] , |
| \u_riscv_top.fpu_dmem_rdata[8] , |
| \u_riscv_top.fpu_dmem_rdata[7] , |
| \u_riscv_top.fpu_dmem_rdata[6] , |
| \u_riscv_top.fpu_dmem_rdata[5] , |
| \u_riscv_top.fpu_dmem_rdata[4] , |
| \u_riscv_top.fpu_dmem_rdata[3] , |
| \u_riscv_top.fpu_dmem_rdata[2] , |
| \u_riscv_top.fpu_dmem_rdata[1] , |
| \u_riscv_top.fpu_dmem_rdata[0] }), |
| .dmem_resp({\u_riscv_top.fpu_dmem_resp[1] , |
| \u_riscv_top.fpu_dmem_resp[0] }), |
| .dmem_wdata({\u_riscv_top.fpu_dmem_wdata[31] , |
| \u_riscv_top.fpu_dmem_wdata[30] , |
| \u_riscv_top.fpu_dmem_wdata[29] , |
| \u_riscv_top.fpu_dmem_wdata[28] , |
| \u_riscv_top.fpu_dmem_wdata[27] , |
| \u_riscv_top.fpu_dmem_wdata[26] , |
| \u_riscv_top.fpu_dmem_wdata[25] , |
| \u_riscv_top.fpu_dmem_wdata[24] , |
| \u_riscv_top.fpu_dmem_wdata[23] , |
| \u_riscv_top.fpu_dmem_wdata[22] , |
| \u_riscv_top.fpu_dmem_wdata[21] , |
| \u_riscv_top.fpu_dmem_wdata[20] , |
| \u_riscv_top.fpu_dmem_wdata[19] , |
| \u_riscv_top.fpu_dmem_wdata[18] , |
| \u_riscv_top.fpu_dmem_wdata[17] , |
| \u_riscv_top.fpu_dmem_wdata[16] , |
| \u_riscv_top.fpu_dmem_wdata[15] , |
| \u_riscv_top.fpu_dmem_wdata[14] , |
| \u_riscv_top.fpu_dmem_wdata[13] , |
| \u_riscv_top.fpu_dmem_wdata[12] , |
| \u_riscv_top.fpu_dmem_wdata[11] , |
| \u_riscv_top.fpu_dmem_wdata[10] , |
| \u_riscv_top.fpu_dmem_wdata[9] , |
| \u_riscv_top.fpu_dmem_wdata[8] , |
| \u_riscv_top.fpu_dmem_wdata[7] , |
| \u_riscv_top.fpu_dmem_wdata[6] , |
| \u_riscv_top.fpu_dmem_wdata[5] , |
| \u_riscv_top.fpu_dmem_wdata[4] , |
| \u_riscv_top.fpu_dmem_wdata[3] , |
| \u_riscv_top.fpu_dmem_wdata[2] , |
| \u_riscv_top.fpu_dmem_wdata[1] , |
| \u_riscv_top.fpu_dmem_wdata[0] }), |
| .dmem_width({\u_riscv_top.fpu_dmem_width[1] , |
| \u_riscv_top.fpu_dmem_width[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb (.csb0(\u_riscv_top.icache_mem_csb0 ), |
| .csb1(\u_riscv_top.icache_mem_csb1 ), |
| .web0(\u_riscv_top.icache_mem_web0 ), |
| .clk0(\u_riscv_top.icache_mem_clk0 ), |
| .clk1(\u_riscv_top.icache_mem_clk1 ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\u_riscv_top.icache_mem_addr0[8] , |
| \u_riscv_top.icache_mem_addr0[7] , |
| \u_riscv_top.icache_mem_addr0[6] , |
| \u_riscv_top.icache_mem_addr0[5] , |
| \u_riscv_top.icache_mem_addr0[4] , |
| \u_riscv_top.icache_mem_addr0[3] , |
| \u_riscv_top.icache_mem_addr0[2] , |
| \u_riscv_top.icache_mem_addr0[1] , |
| \u_riscv_top.icache_mem_addr0[0] }), |
| .addr1({\u_riscv_top.icache_mem_addr1[8] , |
| \u_riscv_top.icache_mem_addr1[7] , |
| \u_riscv_top.icache_mem_addr1[6] , |
| \u_riscv_top.icache_mem_addr1[5] , |
| \u_riscv_top.icache_mem_addr1[4] , |
| \u_riscv_top.icache_mem_addr1[3] , |
| \u_riscv_top.icache_mem_addr1[2] , |
| \u_riscv_top.icache_mem_addr1[1] , |
| \u_riscv_top.icache_mem_addr1[0] }), |
| .din0({\u_riscv_top.icache_mem_din0[31] , |
| \u_riscv_top.icache_mem_din0[30] , |
| \u_riscv_top.icache_mem_din0[29] , |
| \u_riscv_top.icache_mem_din0[28] , |
| \u_riscv_top.icache_mem_din0[27] , |
| \u_riscv_top.icache_mem_din0[26] , |
| \u_riscv_top.icache_mem_din0[25] , |
| \u_riscv_top.icache_mem_din0[24] , |
| \u_riscv_top.icache_mem_din0[23] , |
| \u_riscv_top.icache_mem_din0[22] , |
| \u_riscv_top.icache_mem_din0[21] , |
| \u_riscv_top.icache_mem_din0[20] , |
| \u_riscv_top.icache_mem_din0[19] , |
| \u_riscv_top.icache_mem_din0[18] , |
| \u_riscv_top.icache_mem_din0[17] , |
| \u_riscv_top.icache_mem_din0[16] , |
| \u_riscv_top.icache_mem_din0[15] , |
| \u_riscv_top.icache_mem_din0[14] , |
| \u_riscv_top.icache_mem_din0[13] , |
| \u_riscv_top.icache_mem_din0[12] , |
| \u_riscv_top.icache_mem_din0[11] , |
| \u_riscv_top.icache_mem_din0[10] , |
| \u_riscv_top.icache_mem_din0[9] , |
| \u_riscv_top.icache_mem_din0[8] , |
| \u_riscv_top.icache_mem_din0[7] , |
| \u_riscv_top.icache_mem_din0[6] , |
| \u_riscv_top.icache_mem_din0[5] , |
| \u_riscv_top.icache_mem_din0[4] , |
| \u_riscv_top.icache_mem_din0[3] , |
| \u_riscv_top.icache_mem_din0[2] , |
| \u_riscv_top.icache_mem_din0[1] , |
| \u_riscv_top.icache_mem_din0[0] }), |
| .dout0({_NC1, |
| _NC2, |
| _NC3, |
| _NC4, |
| _NC5, |
| _NC6, |
| _NC7, |
| _NC8, |
| _NC9, |
| _NC10, |
| _NC11, |
| _NC12, |
| _NC13, |
| _NC14, |
| _NC15, |
| _NC16, |
| _NC17, |
| _NC18, |
| _NC19, |
| _NC20, |
| _NC21, |
| _NC22, |
| _NC23, |
| _NC24, |
| _NC25, |
| _NC26, |
| _NC27, |
| _NC28, |
| _NC29, |
| _NC30, |
| _NC31, |
| _NC32}), |
| .dout1({\u_riscv_top.icache_mem_dout1[31] , |
| \u_riscv_top.icache_mem_dout1[30] , |
| \u_riscv_top.icache_mem_dout1[29] , |
| \u_riscv_top.icache_mem_dout1[28] , |
| \u_riscv_top.icache_mem_dout1[27] , |
| \u_riscv_top.icache_mem_dout1[26] , |
| \u_riscv_top.icache_mem_dout1[25] , |
| \u_riscv_top.icache_mem_dout1[24] , |
| \u_riscv_top.icache_mem_dout1[23] , |
| \u_riscv_top.icache_mem_dout1[22] , |
| \u_riscv_top.icache_mem_dout1[21] , |
| \u_riscv_top.icache_mem_dout1[20] , |
| \u_riscv_top.icache_mem_dout1[19] , |
| \u_riscv_top.icache_mem_dout1[18] , |
| \u_riscv_top.icache_mem_dout1[17] , |
| \u_riscv_top.icache_mem_dout1[16] , |
| \u_riscv_top.icache_mem_dout1[15] , |
| \u_riscv_top.icache_mem_dout1[14] , |
| \u_riscv_top.icache_mem_dout1[13] , |
| \u_riscv_top.icache_mem_dout1[12] , |
| \u_riscv_top.icache_mem_dout1[11] , |
| \u_riscv_top.icache_mem_dout1[10] , |
| \u_riscv_top.icache_mem_dout1[9] , |
| \u_riscv_top.icache_mem_dout1[8] , |
| \u_riscv_top.icache_mem_dout1[7] , |
| \u_riscv_top.icache_mem_dout1[6] , |
| \u_riscv_top.icache_mem_dout1[5] , |
| \u_riscv_top.icache_mem_dout1[4] , |
| \u_riscv_top.icache_mem_dout1[3] , |
| \u_riscv_top.icache_mem_dout1[2] , |
| \u_riscv_top.icache_mem_dout1[1] , |
| \u_riscv_top.icache_mem_dout1[0] }), |
| .wmask0({\u_riscv_top.icache_mem_wmask0[3] , |
| \u_riscv_top.icache_mem_wmask0[2] , |
| \u_riscv_top.icache_mem_wmask0[1] , |
| \u_riscv_top.icache_mem_wmask0[0] })); |
| wb_interconnect u_intercon (.clk_i(wbd_clk_wi_skew), |
| .m0_wbd_ack_o(wbd_int_ack_o), |
| .m0_wbd_cyc_i(wbd_int_cyc_i), |
| .m0_wbd_err_o(wbd_int_err_o), |
| .m0_wbd_stb_i(wbd_int_stb_i), |
| .m0_wbd_we_i(wbd_int_we_i), |
| .m1_wbd_ack_o(\u_riscv_top.wbd_dmem_ack_i ), |
| .m1_wbd_bry_i(\u_riscv_top.wbd_dmem_bry_o ), |
| .m1_wbd_cyc_i(\u_riscv_top.wbd_dmem_stb_o ), |
| .m1_wbd_err_o(\u_riscv_top.wbd_dmem_err_i ), |
| .m1_wbd_lack_o(\u_riscv_top.wbd_dmem_lack_i ), |
| .m1_wbd_stb_i(\u_riscv_top.wbd_dmem_stb_o ), |
| .m1_wbd_we_i(\u_riscv_top.wbd_dmem_we_o ), |
| .m2_wbd_ack_o(\u_riscv_top.wb_dcache_ack_i ), |
| .m2_wbd_bry_i(\u_riscv_top.wb_dcache_bry_o ), |
| .m2_wbd_cyc_i(\u_riscv_top.wb_dcache_stb_o ), |
| .m2_wbd_err_o(\u_riscv_top.wb_dcache_err_i ), |
| .m2_wbd_lack_o(\u_riscv_top.wb_dcache_lack_i ), |
| .m2_wbd_stb_i(\u_riscv_top.wb_dcache_stb_o ), |
| .m2_wbd_we_i(\u_riscv_top.wb_dcache_we_o ), |
| .m3_wbd_ack_o(\u_riscv_top.wb_icache_ack_i ), |
| .m3_wbd_bry_i(\u_riscv_top.wb_icache_bry_o ), |
| .m3_wbd_cyc_i(\u_riscv_top.wb_icache_stb_o ), |
| .m3_wbd_err_o(\u_riscv_top.wb_icache_err_i ), |
| .m3_wbd_lack_o(\u_riscv_top.wb_icache_lack_i ), |
| .m3_wbd_stb_i(\u_riscv_top.wb_icache_stb_o ), |
| .m3_wbd_we_i(\u_riscv_top.wb_icache_we_o ), |
| .rst_n(\u_riscv_top.pwrup_rst_n ), |
| .s0_wbd_ack_i(wbd_spim_ack_i), |
| .s0_wbd_bry_o(wbd_spim_bry_o), |
| .s0_wbd_cyc_o(wbd_spim_cyc_o), |
| .s0_wbd_lack_i(wbd_spim_lack_i), |
| .s0_wbd_stb_o(wbd_spim_stb_o), |
| .s0_wbd_we_o(wbd_spim_we_o), |
| .s1_wbd_ack_i(wbd_uart_ack_i), |
| .s1_wbd_cyc_o(wbd_uart_cyc_o), |
| .s1_wbd_stb_o(wbd_uart_stb_o), |
| .s1_wbd_we_o(wbd_uart_we_o), |
| .s2_wbd_ack_i(wbd_glbl_ack_i), |
| .s2_wbd_cyc_o(wbd_glbl_cyc_o), |
| .s2_wbd_stb_o(wbd_glbl_stb_o), |
| .s2_wbd_we_o(wbd_glbl_we_o), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(wbd_clk_int), |
| .wbd_clk_wi(wbd_clk_wi_skew), |
| .cfg_cska_wi({\cfg_clk_skew_ctrl1[3] , |
| \cfg_clk_skew_ctrl1[2] , |
| \cfg_clk_skew_ctrl1[1] , |
| \cfg_clk_skew_ctrl1[0] }), |
| .ch_clk_in({cpu_clk, |
| cpu_clk, |
| cpu_clk, |
| wbd_clk_int, |
| wbd_clk_int, |
| wbd_clk_int, |
| wbd_clk_int, |
| wbd_clk_int}), |
| .ch_clk_out({\cpu_clk_rp[2] , |
| \u_riscv_top.core_clk_int[1] , |
| \u_riscv_top.core_clk_int[0] , |
| wbd_clk_peri_rp, |
| wbd_clk_pinmux_rp, |
| wbd_clk_uart_rp, |
| wbd_clk_qspi_rp, |
| \u_riscv_top.wbd_clk_int }), |
| .ch_data_in({\cfg_clk_skew_ctrl1[31] , |
| \cfg_clk_skew_ctrl1[30] , |
| \cfg_clk_skew_ctrl1[29] , |
| \cfg_clk_skew_ctrl1[28] , |
| \cfg_clk_skew_ctrl2[31] , |
| \cfg_clk_skew_ctrl2[30] , |
| \cfg_clk_skew_ctrl2[29] , |
| \cfg_clk_skew_ctrl2[28] , |
| \cfg_clk_skew_ctrl2[27] , |
| \cfg_clk_skew_ctrl2[26] , |
| \cfg_clk_skew_ctrl2[25] , |
| \cfg_clk_skew_ctrl2[24] , |
| \strap_sticky[31] , |
| \strap_sticky[30] , |
| \strap_sticky[29] , |
| \strap_sticky[28] , |
| \strap_sticky[27] , |
| \strap_sticky[26] , |
| \strap_sticky[25] , |
| \strap_sticky[24] , |
| \strap_sticky[23] , |
| \strap_sticky[22] , |
| \strap_sticky[21] , |
| \strap_sticky[20] , |
| \strap_sticky[19] , |
| \strap_sticky[18] , |
| \strap_sticky[17] , |
| \strap_sticky[16] , |
| \strap_sticky[15] , |
| \strap_sticky[14] , |
| \strap_sticky[13] , |
| \strap_sticky[12] , |
| \strap_sticky[11] , |
| \strap_sticky[10] , |
| \strap_sticky[9] , |
| \strap_sticky[8] , |
| \strap_sticky[7] , |
| \strap_sticky[6] , |
| \strap_sticky[5] , |
| \strap_sticky[4] , |
| \strap_sticky[3] , |
| \strap_sticky[2] , |
| \strap_sticky[1] , |
| \strap_sticky[0] , |
| \strap_uartm[1] , |
| \strap_uartm[0] , |
| \system_strap[31] , |
| \system_strap[30] , |
| \system_strap[29] , |
| \system_strap[28] , |
| \system_strap[27] , |
| \system_strap[26] , |
| \system_strap[25] , |
| \system_strap[24] , |
| \system_strap[23] , |
| \system_strap[22] , |
| \system_strap[21] , |
| \system_strap[20] , |
| \system_strap[19] , |
| \system_strap[18] , |
| \system_strap[17] , |
| \system_strap[16] , |
| \system_strap[15] , |
| \system_strap[14] , |
| \system_strap[13] , |
| \system_strap[12] , |
| \system_strap[11] , |
| \system_strap[10] , |
| \system_strap[9] , |
| \system_strap[8] , |
| \system_strap[7] , |
| \system_strap[6] , |
| \system_strap[5] , |
| \system_strap[4] , |
| \system_strap[3] , |
| \system_strap[2] , |
| \system_strap[1] , |
| \system_strap[0] , |
| p_reset_n, |
| e_reset_n, |
| cfg_strap_pad_ctrl, |
| soft_irq, |
| \irq_lines[31] , |
| \irq_lines[30] , |
| \irq_lines[29] , |
| \irq_lines[28] , |
| \irq_lines[27] , |
| \irq_lines[26] , |
| \irq_lines[25] , |
| \irq_lines[24] , |
| \irq_lines[23] , |
| \irq_lines[22] , |
| \irq_lines[21] , |
| \irq_lines[20] , |
| \irq_lines[19] , |
| \irq_lines[18] , |
| \irq_lines[17] , |
| \irq_lines[16] , |
| \irq_lines[15] , |
| \irq_lines[14] , |
| \irq_lines[13] , |
| \irq_lines[12] , |
| \irq_lines[11] , |
| \irq_lines[10] , |
| \irq_lines[9] , |
| \irq_lines[8] , |
| \irq_lines[7] , |
| \irq_lines[6] , |
| \irq_lines[5] , |
| \irq_lines[4] , |
| \irq_lines[3] , |
| \irq_lines[2] , |
| \irq_lines[1] , |
| \irq_lines[0] , |
| \cfg_clk_skew_ctrl2[23] , |
| \cfg_clk_skew_ctrl2[22] , |
| \cfg_clk_skew_ctrl2[21] , |
| \cfg_clk_skew_ctrl2[20] , |
| \cfg_clk_skew_ctrl2[19] , |
| \cfg_clk_skew_ctrl2[18] , |
| \cfg_clk_skew_ctrl2[17] , |
| \cfg_clk_skew_ctrl2[16] , |
| \cfg_clk_skew_ctrl2[15] , |
| \cfg_clk_skew_ctrl2[14] , |
| \cfg_clk_skew_ctrl2[13] , |
| \cfg_clk_skew_ctrl2[12] , |
| \cfg_clk_skew_ctrl2[11] , |
| \cfg_clk_skew_ctrl2[10] , |
| \cfg_clk_skew_ctrl2[9] , |
| \cfg_clk_skew_ctrl2[8] , |
| \cfg_clk_skew_ctrl2[7] , |
| \cfg_clk_skew_ctrl2[6] , |
| \cfg_clk_skew_ctrl2[5] , |
| \cfg_clk_skew_ctrl2[4] , |
| \cfg_clk_skew_ctrl2[3] , |
| \cfg_clk_skew_ctrl2[2] , |
| \cfg_clk_skew_ctrl2[1] , |
| \cfg_clk_skew_ctrl2[0] , |
| \cfg_clk_skew_ctrl1[27] , |
| \cfg_clk_skew_ctrl1[26] , |
| \cfg_clk_skew_ctrl1[25] , |
| \cfg_clk_skew_ctrl1[24] , |
| \cfg_clk_skew_ctrl1[23] , |
| \cfg_clk_skew_ctrl1[22] , |
| \cfg_clk_skew_ctrl1[21] , |
| \cfg_clk_skew_ctrl1[20] , |
| \cfg_clk_skew_ctrl1[19] , |
| \cfg_clk_skew_ctrl1[18] , |
| \cfg_clk_skew_ctrl1[17] , |
| \cfg_clk_skew_ctrl1[16] , |
| \cfg_clk_skew_ctrl1[15] , |
| \cfg_clk_skew_ctrl1[14] , |
| \cfg_clk_skew_ctrl1[13] , |
| \cfg_clk_skew_ctrl1[12] , |
| \cfg_clk_skew_ctrl1[11] , |
| \cfg_clk_skew_ctrl1[10] , |
| \cfg_clk_skew_ctrl1[9] , |
| \cfg_clk_skew_ctrl1[8] }), |
| .ch_data_out({\cfg_wcska_peri_rp[3] , |
| \cfg_wcska_peri_rp[2] , |
| \cfg_wcska_peri_rp[1] , |
| \cfg_wcska_peri_rp[0] , |
| \cfg_ccska_fpu_rp[3] , |
| \cfg_ccska_fpu_rp[2] , |
| \cfg_ccska_fpu_rp[1] , |
| \cfg_ccska_fpu_rp[0] , |
| \cfg_ccska_aes_rp[3] , |
| \cfg_ccska_aes_rp[2] , |
| \cfg_ccska_aes_rp[1] , |
| \cfg_ccska_aes_rp[0] , |
| \strap_sticky_rp[31] , |
| \strap_sticky_rp[30] , |
| \strap_sticky_rp[29] , |
| \strap_sticky_rp[28] , |
| \strap_sticky_rp[27] , |
| \strap_sticky_rp[26] , |
| \strap_sticky_rp[25] , |
| \strap_sticky_rp[24] , |
| \strap_sticky_rp[23] , |
| \strap_sticky_rp[22] , |
| \strap_sticky_rp[21] , |
| \strap_sticky_rp[20] , |
| \strap_sticky_rp[19] , |
| \strap_sticky_rp[18] , |
| \strap_sticky_rp[17] , |
| \strap_sticky_rp[16] , |
| \strap_sticky_rp[15] , |
| \strap_sticky_rp[14] , |
| \strap_sticky_rp[13] , |
| \strap_sticky_rp[12] , |
| \strap_sticky_rp[11] , |
| \strap_sticky_rp[10] , |
| \strap_sticky_rp[9] , |
| \strap_sticky_rp[8] , |
| \strap_sticky_rp[7] , |
| \strap_sticky_rp[6] , |
| \strap_sticky_rp[5] , |
| \strap_sticky_rp[4] , |
| \strap_sticky_rp[3] , |
| \strap_sticky_rp[2] , |
| \strap_sticky_rp[1] , |
| \strap_sticky_rp[0] , |
| \strap_uartm_rp[1] , |
| \strap_uartm_rp[0] , |
| \system_strap_rp[31] , |
| \system_strap_rp[30] , |
| \system_strap_rp[29] , |
| \system_strap_rp[28] , |
| \system_strap_rp[27] , |
| \system_strap_rp[26] , |
| \system_strap_rp[25] , |
| \system_strap_rp[24] , |
| \system_strap_rp[23] , |
| \system_strap_rp[22] , |
| \system_strap_rp[21] , |
| \system_strap_rp[20] , |
| \system_strap_rp[19] , |
| \system_strap_rp[18] , |
| \system_strap_rp[17] , |
| \system_strap_rp[16] , |
| \system_strap_rp[15] , |
| \system_strap_rp[14] , |
| \system_strap_rp[13] , |
| \system_strap_rp[12] , |
| \system_strap_rp[11] , |
| \system_strap_rp[10] , |
| \system_strap_rp[9] , |
| \system_strap_rp[8] , |
| \system_strap_rp[7] , |
| \system_strap_rp[6] , |
| \system_strap_rp[5] , |
| \system_strap_rp[4] , |
| \system_strap_rp[3] , |
| \system_strap_rp[2] , |
| \system_strap_rp[1] , |
| \system_strap_rp[0] , |
| p_reset_n_rp, |
| e_reset_n_rp, |
| cfg_strap_pad_ctrl_rp, |
| \u_riscv_top.soft_irq , |
| \u_riscv_top.irq_lines[31] , |
| \u_riscv_top.irq_lines[30] , |
| \u_riscv_top.irq_lines[29] , |
| \u_riscv_top.irq_lines[28] , |
| \u_riscv_top.irq_lines[27] , |
| \u_riscv_top.irq_lines[26] , |
| \u_riscv_top.irq_lines[25] , |
| \u_riscv_top.irq_lines[24] , |
| \u_riscv_top.irq_lines[23] , |
| \u_riscv_top.irq_lines[22] , |
| \u_riscv_top.irq_lines[21] , |
| \u_riscv_top.irq_lines[20] , |
| \u_riscv_top.irq_lines[19] , |
| \u_riscv_top.irq_lines[18] , |
| \u_riscv_top.irq_lines[17] , |
| \u_riscv_top.irq_lines[16] , |
| \u_riscv_top.irq_lines[15] , |
| \u_riscv_top.irq_lines[14] , |
| \u_riscv_top.irq_lines[13] , |
| \u_riscv_top.irq_lines[12] , |
| \u_riscv_top.irq_lines[11] , |
| \u_riscv_top.irq_lines[10] , |
| \u_riscv_top.irq_lines[9] , |
| \u_riscv_top.irq_lines[8] , |
| \u_riscv_top.irq_lines[7] , |
| \u_riscv_top.irq_lines[6] , |
| \u_riscv_top.irq_lines[5] , |
| \u_riscv_top.irq_lines[4] , |
| \u_riscv_top.irq_lines[3] , |
| \u_riscv_top.irq_lines[2] , |
| \u_riscv_top.irq_lines[1] , |
| \u_riscv_top.irq_lines[0] , |
| \cfg_ccska_riscv_core3_rp[3] , |
| \cfg_ccska_riscv_core3_rp[2] , |
| \cfg_ccska_riscv_core3_rp[1] , |
| \cfg_ccska_riscv_core3_rp[0] , |
| \cfg_ccska_riscv_core2_rp[3] , |
| \cfg_ccska_riscv_core2_rp[2] , |
| \cfg_ccska_riscv_core2_rp[1] , |
| \cfg_ccska_riscv_core2_rp[0] , |
| \u_riscv_top.cfg_ccska_riscv_core1[3] , |
| \u_riscv_top.cfg_ccska_riscv_core1[2] , |
| \u_riscv_top.cfg_ccska_riscv_core1[1] , |
| \u_riscv_top.cfg_ccska_riscv_core1[0] , |
| \u_riscv_top.cfg_ccska_riscv_core0[3] , |
| \u_riscv_top.cfg_ccska_riscv_core0[2] , |
| \u_riscv_top.cfg_ccska_riscv_core0[1] , |
| \u_riscv_top.cfg_ccska_riscv_core0[0] , |
| \u_riscv_top.cfg_ccska_riscv_icon[3] , |
| \u_riscv_top.cfg_ccska_riscv_icon[2] , |
| \u_riscv_top.cfg_ccska_riscv_icon[1] , |
| \u_riscv_top.cfg_ccska_riscv_icon[0] , |
| \u_riscv_top.cfg_ccska_riscv_intf[3] , |
| \u_riscv_top.cfg_ccska_riscv_intf[2] , |
| \u_riscv_top.cfg_ccska_riscv_intf[1] , |
| \u_riscv_top.cfg_ccska_riscv_intf[0] , |
| \cfg_wcska_qspi_co_rp[3] , |
| \cfg_wcska_qspi_co_rp[2] , |
| \cfg_wcska_qspi_co_rp[1] , |
| \cfg_wcska_qspi_co_rp[0] , |
| \cfg_wcska_pinmux_rp[3] , |
| \cfg_wcska_pinmux_rp[2] , |
| \cfg_wcska_pinmux_rp[1] , |
| \cfg_wcska_pinmux_rp[0] , |
| \cfg_wcska_uart_rp[3] , |
| \cfg_wcska_uart_rp[2] , |
| \cfg_wcska_uart_rp[1] , |
| \cfg_wcska_uart_rp[0] , |
| \cfg_wcska_qspi_rp[3] , |
| \cfg_wcska_qspi_rp[2] , |
| \cfg_wcska_qspi_rp[1] , |
| \cfg_wcska_qspi_rp[0] , |
| \u_riscv_top.cfg_wcska_riscv_intf[3] , |
| \u_riscv_top.cfg_wcska_riscv_intf[2] , |
| \u_riscv_top.cfg_wcska_riscv_intf[1] , |
| \u_riscv_top.cfg_wcska_riscv_intf[0] }), |
| .m0_wbd_adr_i({\wbd_int_adr_i[31] , |
| \wbd_int_adr_i[30] , |
| \wbd_int_adr_i[29] , |
| \wbd_int_adr_i[28] , |
| \wbd_int_adr_i[27] , |
| \wbd_int_adr_i[26] , |
| \wbd_int_adr_i[25] , |
| \wbd_int_adr_i[24] , |
| \wbd_int_adr_i[23] , |
| \wbd_int_adr_i[22] , |
| \wbd_int_adr_i[21] , |
| \wbd_int_adr_i[20] , |
| \wbd_int_adr_i[19] , |
| \wbd_int_adr_i[18] , |
| \wbd_int_adr_i[17] , |
| \wbd_int_adr_i[16] , |
| \wbd_int_adr_i[15] , |
| \wbd_int_adr_i[14] , |
| \wbd_int_adr_i[13] , |
| \wbd_int_adr_i[12] , |
| \wbd_int_adr_i[11] , |
| \wbd_int_adr_i[10] , |
| \wbd_int_adr_i[9] , |
| \wbd_int_adr_i[8] , |
| \wbd_int_adr_i[7] , |
| \wbd_int_adr_i[6] , |
| \wbd_int_adr_i[5] , |
| \wbd_int_adr_i[4] , |
| \wbd_int_adr_i[3] , |
| \wbd_int_adr_i[2] , |
| \wbd_int_adr_i[1] , |
| \wbd_int_adr_i[0] }), |
| .m0_wbd_dat_i({\wbd_int_dat_i[31] , |
| \wbd_int_dat_i[30] , |
| \wbd_int_dat_i[29] , |
| \wbd_int_dat_i[28] , |
| \wbd_int_dat_i[27] , |
| \wbd_int_dat_i[26] , |
| \wbd_int_dat_i[25] , |
| \wbd_int_dat_i[24] , |
| \wbd_int_dat_i[23] , |
| \wbd_int_dat_i[22] , |
| \wbd_int_dat_i[21] , |
| \wbd_int_dat_i[20] , |
| \wbd_int_dat_i[19] , |
| \wbd_int_dat_i[18] , |
| \wbd_int_dat_i[17] , |
| \wbd_int_dat_i[16] , |
| \wbd_int_dat_i[15] , |
| \wbd_int_dat_i[14] , |
| \wbd_int_dat_i[13] , |
| \wbd_int_dat_i[12] , |
| \wbd_int_dat_i[11] , |
| \wbd_int_dat_i[10] , |
| \wbd_int_dat_i[9] , |
| \wbd_int_dat_i[8] , |
| \wbd_int_dat_i[7] , |
| \wbd_int_dat_i[6] , |
| \wbd_int_dat_i[5] , |
| \wbd_int_dat_i[4] , |
| \wbd_int_dat_i[3] , |
| \wbd_int_dat_i[2] , |
| \wbd_int_dat_i[1] , |
| \wbd_int_dat_i[0] }), |
| .m0_wbd_dat_o({\wbd_int_dat_o[31] , |
| \wbd_int_dat_o[30] , |
| \wbd_int_dat_o[29] , |
| \wbd_int_dat_o[28] , |
| \wbd_int_dat_o[27] , |
| \wbd_int_dat_o[26] , |
| \wbd_int_dat_o[25] , |
| \wbd_int_dat_o[24] , |
| \wbd_int_dat_o[23] , |
| \wbd_int_dat_o[22] , |
| \wbd_int_dat_o[21] , |
| \wbd_int_dat_o[20] , |
| \wbd_int_dat_o[19] , |
| \wbd_int_dat_o[18] , |
| \wbd_int_dat_o[17] , |
| \wbd_int_dat_o[16] , |
| \wbd_int_dat_o[15] , |
| \wbd_int_dat_o[14] , |
| \wbd_int_dat_o[13] , |
| \wbd_int_dat_o[12] , |
| \wbd_int_dat_o[11] , |
| \wbd_int_dat_o[10] , |
| \wbd_int_dat_o[9] , |
| \wbd_int_dat_o[8] , |
| \wbd_int_dat_o[7] , |
| \wbd_int_dat_o[6] , |
| \wbd_int_dat_o[5] , |
| \wbd_int_dat_o[4] , |
| \wbd_int_dat_o[3] , |
| \wbd_int_dat_o[2] , |
| \wbd_int_dat_o[1] , |
| \wbd_int_dat_o[0] }), |
| .m0_wbd_sel_i({\wbd_int_sel_i[3] , |
| \wbd_int_sel_i[2] , |
| \wbd_int_sel_i[1] , |
| \wbd_int_sel_i[0] }), |
| .m1_wbd_adr_i({\u_riscv_top.wbd_dmem_adr_o[31] , |
| \u_riscv_top.wbd_dmem_adr_o[30] , |
| \u_riscv_top.wbd_dmem_adr_o[29] , |
| \u_riscv_top.wbd_dmem_adr_o[28] , |
| \u_riscv_top.wbd_dmem_adr_o[27] , |
| \u_riscv_top.wbd_dmem_adr_o[26] , |
| \u_riscv_top.wbd_dmem_adr_o[25] , |
| \u_riscv_top.wbd_dmem_adr_o[24] , |
| \u_riscv_top.wbd_dmem_adr_o[23] , |
| \u_riscv_top.wbd_dmem_adr_o[22] , |
| \u_riscv_top.wbd_dmem_adr_o[21] , |
| \u_riscv_top.wbd_dmem_adr_o[20] , |
| \u_riscv_top.wbd_dmem_adr_o[19] , |
| \u_riscv_top.wbd_dmem_adr_o[18] , |
| \u_riscv_top.wbd_dmem_adr_o[17] , |
| \u_riscv_top.wbd_dmem_adr_o[16] , |
| \u_riscv_top.wbd_dmem_adr_o[15] , |
| \u_riscv_top.wbd_dmem_adr_o[14] , |
| \u_riscv_top.wbd_dmem_adr_o[13] , |
| \u_riscv_top.wbd_dmem_adr_o[12] , |
| \u_riscv_top.wbd_dmem_adr_o[11] , |
| \u_riscv_top.wbd_dmem_adr_o[10] , |
| \u_riscv_top.wbd_dmem_adr_o[9] , |
| \u_riscv_top.wbd_dmem_adr_o[8] , |
| \u_riscv_top.wbd_dmem_adr_o[7] , |
| \u_riscv_top.wbd_dmem_adr_o[6] , |
| \u_riscv_top.wbd_dmem_adr_o[5] , |
| \u_riscv_top.wbd_dmem_adr_o[4] , |
| \u_riscv_top.wbd_dmem_adr_o[3] , |
| \u_riscv_top.wbd_dmem_adr_o[2] , |
| \u_riscv_top.wbd_dmem_adr_o[1] , |
| \u_riscv_top.wbd_dmem_adr_o[0] }), |
| .m1_wbd_bl_i({\u_riscv_top.wbd_dmem_bl_o[2] , |
| \u_riscv_top.wbd_dmem_bl_o[1] , |
| \u_riscv_top.wbd_dmem_bl_o[0] }), |
| .m1_wbd_dat_i({\u_riscv_top.wbd_dmem_dat_o[31] , |
| \u_riscv_top.wbd_dmem_dat_o[30] , |
| \u_riscv_top.wbd_dmem_dat_o[29] , |
| \u_riscv_top.wbd_dmem_dat_o[28] , |
| \u_riscv_top.wbd_dmem_dat_o[27] , |
| \u_riscv_top.wbd_dmem_dat_o[26] , |
| \u_riscv_top.wbd_dmem_dat_o[25] , |
| \u_riscv_top.wbd_dmem_dat_o[24] , |
| \u_riscv_top.wbd_dmem_dat_o[23] , |
| \u_riscv_top.wbd_dmem_dat_o[22] , |
| \u_riscv_top.wbd_dmem_dat_o[21] , |
| \u_riscv_top.wbd_dmem_dat_o[20] , |
| \u_riscv_top.wbd_dmem_dat_o[19] , |
| \u_riscv_top.wbd_dmem_dat_o[18] , |
| \u_riscv_top.wbd_dmem_dat_o[17] , |
| \u_riscv_top.wbd_dmem_dat_o[16] , |
| \u_riscv_top.wbd_dmem_dat_o[15] , |
| \u_riscv_top.wbd_dmem_dat_o[14] , |
| \u_riscv_top.wbd_dmem_dat_o[13] , |
| \u_riscv_top.wbd_dmem_dat_o[12] , |
| \u_riscv_top.wbd_dmem_dat_o[11] , |
| \u_riscv_top.wbd_dmem_dat_o[10] , |
| \u_riscv_top.wbd_dmem_dat_o[9] , |
| \u_riscv_top.wbd_dmem_dat_o[8] , |
| \u_riscv_top.wbd_dmem_dat_o[7] , |
| \u_riscv_top.wbd_dmem_dat_o[6] , |
| \u_riscv_top.wbd_dmem_dat_o[5] , |
| \u_riscv_top.wbd_dmem_dat_o[4] , |
| \u_riscv_top.wbd_dmem_dat_o[3] , |
| \u_riscv_top.wbd_dmem_dat_o[2] , |
| \u_riscv_top.wbd_dmem_dat_o[1] , |
| \u_riscv_top.wbd_dmem_dat_o[0] }), |
| .m1_wbd_dat_o({\u_riscv_top.wbd_dmem_dat_i[31] , |
| \u_riscv_top.wbd_dmem_dat_i[30] , |
| \u_riscv_top.wbd_dmem_dat_i[29] , |
| \u_riscv_top.wbd_dmem_dat_i[28] , |
| \u_riscv_top.wbd_dmem_dat_i[27] , |
| \u_riscv_top.wbd_dmem_dat_i[26] , |
| \u_riscv_top.wbd_dmem_dat_i[25] , |
| \u_riscv_top.wbd_dmem_dat_i[24] , |
| \u_riscv_top.wbd_dmem_dat_i[23] , |
| \u_riscv_top.wbd_dmem_dat_i[22] , |
| \u_riscv_top.wbd_dmem_dat_i[21] , |
| \u_riscv_top.wbd_dmem_dat_i[20] , |
| \u_riscv_top.wbd_dmem_dat_i[19] , |
| \u_riscv_top.wbd_dmem_dat_i[18] , |
| \u_riscv_top.wbd_dmem_dat_i[17] , |
| \u_riscv_top.wbd_dmem_dat_i[16] , |
| \u_riscv_top.wbd_dmem_dat_i[15] , |
| \u_riscv_top.wbd_dmem_dat_i[14] , |
| \u_riscv_top.wbd_dmem_dat_i[13] , |
| \u_riscv_top.wbd_dmem_dat_i[12] , |
| \u_riscv_top.wbd_dmem_dat_i[11] , |
| \u_riscv_top.wbd_dmem_dat_i[10] , |
| \u_riscv_top.wbd_dmem_dat_i[9] , |
| \u_riscv_top.wbd_dmem_dat_i[8] , |
| \u_riscv_top.wbd_dmem_dat_i[7] , |
| \u_riscv_top.wbd_dmem_dat_i[6] , |
| \u_riscv_top.wbd_dmem_dat_i[5] , |
| \u_riscv_top.wbd_dmem_dat_i[4] , |
| \u_riscv_top.wbd_dmem_dat_i[3] , |
| \u_riscv_top.wbd_dmem_dat_i[2] , |
| \u_riscv_top.wbd_dmem_dat_i[1] , |
| \u_riscv_top.wbd_dmem_dat_i[0] }), |
| .m1_wbd_sel_i({\u_riscv_top.wbd_dmem_sel_o[3] , |
| \u_riscv_top.wbd_dmem_sel_o[2] , |
| \u_riscv_top.wbd_dmem_sel_o[1] , |
| \u_riscv_top.wbd_dmem_sel_o[0] }), |
| .m2_wbd_adr_i({\u_riscv_top.wb_dcache_adr_o[31] , |
| \u_riscv_top.wb_dcache_adr_o[30] , |
| \u_riscv_top.wb_dcache_adr_o[29] , |
| \u_riscv_top.wb_dcache_adr_o[28] , |
| \u_riscv_top.wb_dcache_adr_o[27] , |
| \u_riscv_top.wb_dcache_adr_o[26] , |
| \u_riscv_top.wb_dcache_adr_o[25] , |
| \u_riscv_top.wb_dcache_adr_o[24] , |
| \u_riscv_top.wb_dcache_adr_o[23] , |
| \u_riscv_top.wb_dcache_adr_o[22] , |
| \u_riscv_top.wb_dcache_adr_o[21] , |
| \u_riscv_top.wb_dcache_adr_o[20] , |
| \u_riscv_top.wb_dcache_adr_o[19] , |
| \u_riscv_top.wb_dcache_adr_o[18] , |
| \u_riscv_top.wb_dcache_adr_o[17] , |
| \u_riscv_top.wb_dcache_adr_o[16] , |
| \u_riscv_top.wb_dcache_adr_o[15] , |
| \u_riscv_top.wb_dcache_adr_o[14] , |
| \u_riscv_top.wb_dcache_adr_o[13] , |
| \u_riscv_top.wb_dcache_adr_o[12] , |
| \u_riscv_top.wb_dcache_adr_o[11] , |
| \u_riscv_top.wb_dcache_adr_o[10] , |
| \u_riscv_top.wb_dcache_adr_o[9] , |
| \u_riscv_top.wb_dcache_adr_o[8] , |
| \u_riscv_top.wb_dcache_adr_o[7] , |
| \u_riscv_top.wb_dcache_adr_o[6] , |
| \u_riscv_top.wb_dcache_adr_o[5] , |
| \u_riscv_top.wb_dcache_adr_o[4] , |
| \u_riscv_top.wb_dcache_adr_o[3] , |
| \u_riscv_top.wb_dcache_adr_o[2] , |
| \u_riscv_top.wb_dcache_adr_o[1] , |
| \u_riscv_top.wb_dcache_adr_o[0] }), |
| .m2_wbd_bl_i({\u_riscv_top.wb_dcache_bl_o[9] , |
| \u_riscv_top.wb_dcache_bl_o[8] , |
| \u_riscv_top.wb_dcache_bl_o[7] , |
| \u_riscv_top.wb_dcache_bl_o[6] , |
| \u_riscv_top.wb_dcache_bl_o[5] , |
| \u_riscv_top.wb_dcache_bl_o[4] , |
| \u_riscv_top.wb_dcache_bl_o[3] , |
| \u_riscv_top.wb_dcache_bl_o[2] , |
| \u_riscv_top.wb_dcache_bl_o[1] , |
| \u_riscv_top.wb_dcache_bl_o[0] }), |
| .m2_wbd_dat_i({\u_riscv_top.wb_dcache_dat_o[31] , |
| \u_riscv_top.wb_dcache_dat_o[30] , |
| \u_riscv_top.wb_dcache_dat_o[29] , |
| \u_riscv_top.wb_dcache_dat_o[28] , |
| \u_riscv_top.wb_dcache_dat_o[27] , |
| \u_riscv_top.wb_dcache_dat_o[26] , |
| \u_riscv_top.wb_dcache_dat_o[25] , |
| \u_riscv_top.wb_dcache_dat_o[24] , |
| \u_riscv_top.wb_dcache_dat_o[23] , |
| \u_riscv_top.wb_dcache_dat_o[22] , |
| \u_riscv_top.wb_dcache_dat_o[21] , |
| \u_riscv_top.wb_dcache_dat_o[20] , |
| \u_riscv_top.wb_dcache_dat_o[19] , |
| \u_riscv_top.wb_dcache_dat_o[18] , |
| \u_riscv_top.wb_dcache_dat_o[17] , |
| \u_riscv_top.wb_dcache_dat_o[16] , |
| \u_riscv_top.wb_dcache_dat_o[15] , |
| \u_riscv_top.wb_dcache_dat_o[14] , |
| \u_riscv_top.wb_dcache_dat_o[13] , |
| \u_riscv_top.wb_dcache_dat_o[12] , |
| \u_riscv_top.wb_dcache_dat_o[11] , |
| \u_riscv_top.wb_dcache_dat_o[10] , |
| \u_riscv_top.wb_dcache_dat_o[9] , |
| \u_riscv_top.wb_dcache_dat_o[8] , |
| \u_riscv_top.wb_dcache_dat_o[7] , |
| \u_riscv_top.wb_dcache_dat_o[6] , |
| \u_riscv_top.wb_dcache_dat_o[5] , |
| \u_riscv_top.wb_dcache_dat_o[4] , |
| \u_riscv_top.wb_dcache_dat_o[3] , |
| \u_riscv_top.wb_dcache_dat_o[2] , |
| \u_riscv_top.wb_dcache_dat_o[1] , |
| \u_riscv_top.wb_dcache_dat_o[0] }), |
| .m2_wbd_dat_o({\u_riscv_top.wb_dcache_dat_i[31] , |
| \u_riscv_top.wb_dcache_dat_i[30] , |
| \u_riscv_top.wb_dcache_dat_i[29] , |
| \u_riscv_top.wb_dcache_dat_i[28] , |
| \u_riscv_top.wb_dcache_dat_i[27] , |
| \u_riscv_top.wb_dcache_dat_i[26] , |
| \u_riscv_top.wb_dcache_dat_i[25] , |
| \u_riscv_top.wb_dcache_dat_i[24] , |
| \u_riscv_top.wb_dcache_dat_i[23] , |
| \u_riscv_top.wb_dcache_dat_i[22] , |
| \u_riscv_top.wb_dcache_dat_i[21] , |
| \u_riscv_top.wb_dcache_dat_i[20] , |
| \u_riscv_top.wb_dcache_dat_i[19] , |
| \u_riscv_top.wb_dcache_dat_i[18] , |
| \u_riscv_top.wb_dcache_dat_i[17] , |
| \u_riscv_top.wb_dcache_dat_i[16] , |
| \u_riscv_top.wb_dcache_dat_i[15] , |
| \u_riscv_top.wb_dcache_dat_i[14] , |
| \u_riscv_top.wb_dcache_dat_i[13] , |
| \u_riscv_top.wb_dcache_dat_i[12] , |
| \u_riscv_top.wb_dcache_dat_i[11] , |
| \u_riscv_top.wb_dcache_dat_i[10] , |
| \u_riscv_top.wb_dcache_dat_i[9] , |
| \u_riscv_top.wb_dcache_dat_i[8] , |
| \u_riscv_top.wb_dcache_dat_i[7] , |
| \u_riscv_top.wb_dcache_dat_i[6] , |
| \u_riscv_top.wb_dcache_dat_i[5] , |
| \u_riscv_top.wb_dcache_dat_i[4] , |
| \u_riscv_top.wb_dcache_dat_i[3] , |
| \u_riscv_top.wb_dcache_dat_i[2] , |
| \u_riscv_top.wb_dcache_dat_i[1] , |
| \u_riscv_top.wb_dcache_dat_i[0] }), |
| .m2_wbd_sel_i({\u_riscv_top.wb_dcache_sel_o[3] , |
| \u_riscv_top.wb_dcache_sel_o[2] , |
| \u_riscv_top.wb_dcache_sel_o[1] , |
| \u_riscv_top.wb_dcache_sel_o[0] }), |
| .m3_wbd_adr_i({\u_riscv_top.wb_icache_adr_o[31] , |
| \u_riscv_top.wb_icache_adr_o[30] , |
| \u_riscv_top.wb_icache_adr_o[29] , |
| \u_riscv_top.wb_icache_adr_o[28] , |
| \u_riscv_top.wb_icache_adr_o[27] , |
| \u_riscv_top.wb_icache_adr_o[26] , |
| \u_riscv_top.wb_icache_adr_o[25] , |
| \u_riscv_top.wb_icache_adr_o[24] , |
| \u_riscv_top.wb_icache_adr_o[23] , |
| \u_riscv_top.wb_icache_adr_o[22] , |
| \u_riscv_top.wb_icache_adr_o[21] , |
| \u_riscv_top.wb_icache_adr_o[20] , |
| \u_riscv_top.wb_icache_adr_o[19] , |
| \u_riscv_top.wb_icache_adr_o[18] , |
| \u_riscv_top.wb_icache_adr_o[17] , |
| \u_riscv_top.wb_icache_adr_o[16] , |
| \u_riscv_top.wb_icache_adr_o[15] , |
| \u_riscv_top.wb_icache_adr_o[14] , |
| \u_riscv_top.wb_icache_adr_o[13] , |
| \u_riscv_top.wb_icache_adr_o[12] , |
| \u_riscv_top.wb_icache_adr_o[11] , |
| \u_riscv_top.wb_icache_adr_o[10] , |
| \u_riscv_top.wb_icache_adr_o[9] , |
| \u_riscv_top.wb_icache_adr_o[8] , |
| \u_riscv_top.wb_icache_adr_o[7] , |
| \u_riscv_top.wb_icache_adr_o[6] , |
| \u_riscv_top.wb_icache_adr_o[5] , |
| \u_riscv_top.wb_icache_adr_o[4] , |
| \u_riscv_top.wb_icache_adr_o[3] , |
| \u_riscv_top.wb_icache_adr_o[2] , |
| \u_riscv_top.wb_icache_adr_o[1] , |
| \u_riscv_top.wb_icache_adr_o[0] }), |
| .m3_wbd_bl_i({\u_riscv_top.wb_icache_bl_o[9] , |
| \u_riscv_top.wb_icache_bl_o[8] , |
| \u_riscv_top.wb_icache_bl_o[7] , |
| \u_riscv_top.wb_icache_bl_o[6] , |
| \u_riscv_top.wb_icache_bl_o[5] , |
| \u_riscv_top.wb_icache_bl_o[4] , |
| \u_riscv_top.wb_icache_bl_o[3] , |
| \u_riscv_top.wb_icache_bl_o[2] , |
| \u_riscv_top.wb_icache_bl_o[1] , |
| \u_riscv_top.wb_icache_bl_o[0] }), |
| .m3_wbd_dat_o({\u_riscv_top.wb_icache_dat_i[31] , |
| \u_riscv_top.wb_icache_dat_i[30] , |
| \u_riscv_top.wb_icache_dat_i[29] , |
| \u_riscv_top.wb_icache_dat_i[28] , |
| \u_riscv_top.wb_icache_dat_i[27] , |
| \u_riscv_top.wb_icache_dat_i[26] , |
| \u_riscv_top.wb_icache_dat_i[25] , |
| \u_riscv_top.wb_icache_dat_i[24] , |
| \u_riscv_top.wb_icache_dat_i[23] , |
| \u_riscv_top.wb_icache_dat_i[22] , |
| \u_riscv_top.wb_icache_dat_i[21] , |
| \u_riscv_top.wb_icache_dat_i[20] , |
| \u_riscv_top.wb_icache_dat_i[19] , |
| \u_riscv_top.wb_icache_dat_i[18] , |
| \u_riscv_top.wb_icache_dat_i[17] , |
| \u_riscv_top.wb_icache_dat_i[16] , |
| \u_riscv_top.wb_icache_dat_i[15] , |
| \u_riscv_top.wb_icache_dat_i[14] , |
| \u_riscv_top.wb_icache_dat_i[13] , |
| \u_riscv_top.wb_icache_dat_i[12] , |
| \u_riscv_top.wb_icache_dat_i[11] , |
| \u_riscv_top.wb_icache_dat_i[10] , |
| \u_riscv_top.wb_icache_dat_i[9] , |
| \u_riscv_top.wb_icache_dat_i[8] , |
| \u_riscv_top.wb_icache_dat_i[7] , |
| \u_riscv_top.wb_icache_dat_i[6] , |
| \u_riscv_top.wb_icache_dat_i[5] , |
| \u_riscv_top.wb_icache_dat_i[4] , |
| \u_riscv_top.wb_icache_dat_i[3] , |
| \u_riscv_top.wb_icache_dat_i[2] , |
| \u_riscv_top.wb_icache_dat_i[1] , |
| \u_riscv_top.wb_icache_dat_i[0] }), |
| .m3_wbd_sel_i({\u_riscv_top.wb_icache_sel_o[3] , |
| \u_riscv_top.wb_icache_sel_o[2] , |
| \u_riscv_top.wb_icache_sel_o[1] , |
| \u_riscv_top.wb_icache_sel_o[0] }), |
| .s0_wbd_adr_o({\wbd_spim_adr_o[31] , |
| \wbd_spim_adr_o[30] , |
| \wbd_spim_adr_o[29] , |
| \wbd_spim_adr_o[28] , |
| \wbd_spim_adr_o[27] , |
| \wbd_spim_adr_o[26] , |
| \wbd_spim_adr_o[25] , |
| \wbd_spim_adr_o[24] , |
| \wbd_spim_adr_o[23] , |
| \wbd_spim_adr_o[22] , |
| \wbd_spim_adr_o[21] , |
| \wbd_spim_adr_o[20] , |
| \wbd_spim_adr_o[19] , |
| \wbd_spim_adr_o[18] , |
| \wbd_spim_adr_o[17] , |
| \wbd_spim_adr_o[16] , |
| \wbd_spim_adr_o[15] , |
| \wbd_spim_adr_o[14] , |
| \wbd_spim_adr_o[13] , |
| \wbd_spim_adr_o[12] , |
| \wbd_spim_adr_o[11] , |
| \wbd_spim_adr_o[10] , |
| \wbd_spim_adr_o[9] , |
| \wbd_spim_adr_o[8] , |
| \wbd_spim_adr_o[7] , |
| \wbd_spim_adr_o[6] , |
| \wbd_spim_adr_o[5] , |
| \wbd_spim_adr_o[4] , |
| \wbd_spim_adr_o[3] , |
| \wbd_spim_adr_o[2] , |
| \wbd_spim_adr_o[1] , |
| \wbd_spim_adr_o[0] }), |
| .s0_wbd_bl_o({\wbd_spim_bl_o[9] , |
| \wbd_spim_bl_o[8] , |
| \wbd_spim_bl_o[7] , |
| \wbd_spim_bl_o[6] , |
| \wbd_spim_bl_o[5] , |
| \wbd_spim_bl_o[4] , |
| \wbd_spim_bl_o[3] , |
| \wbd_spim_bl_o[2] , |
| \wbd_spim_bl_o[1] , |
| \wbd_spim_bl_o[0] }), |
| .s0_wbd_dat_i({\wbd_spim_dat_i[31] , |
| \wbd_spim_dat_i[30] , |
| \wbd_spim_dat_i[29] , |
| \wbd_spim_dat_i[28] , |
| \wbd_spim_dat_i[27] , |
| \wbd_spim_dat_i[26] , |
| \wbd_spim_dat_i[25] , |
| \wbd_spim_dat_i[24] , |
| \wbd_spim_dat_i[23] , |
| \wbd_spim_dat_i[22] , |
| \wbd_spim_dat_i[21] , |
| \wbd_spim_dat_i[20] , |
| \wbd_spim_dat_i[19] , |
| \wbd_spim_dat_i[18] , |
| \wbd_spim_dat_i[17] , |
| \wbd_spim_dat_i[16] , |
| \wbd_spim_dat_i[15] , |
| \wbd_spim_dat_i[14] , |
| \wbd_spim_dat_i[13] , |
| \wbd_spim_dat_i[12] , |
| \wbd_spim_dat_i[11] , |
| \wbd_spim_dat_i[10] , |
| \wbd_spim_dat_i[9] , |
| \wbd_spim_dat_i[8] , |
| \wbd_spim_dat_i[7] , |
| \wbd_spim_dat_i[6] , |
| \wbd_spim_dat_i[5] , |
| \wbd_spim_dat_i[4] , |
| \wbd_spim_dat_i[3] , |
| \wbd_spim_dat_i[2] , |
| \wbd_spim_dat_i[1] , |
| \wbd_spim_dat_i[0] }), |
| .s0_wbd_dat_o({\wbd_spim_dat_o[31] , |
| \wbd_spim_dat_o[30] , |
| \wbd_spim_dat_o[29] , |
| \wbd_spim_dat_o[28] , |
| \wbd_spim_dat_o[27] , |
| \wbd_spim_dat_o[26] , |
| \wbd_spim_dat_o[25] , |
| \wbd_spim_dat_o[24] , |
| \wbd_spim_dat_o[23] , |
| \wbd_spim_dat_o[22] , |
| \wbd_spim_dat_o[21] , |
| \wbd_spim_dat_o[20] , |
| \wbd_spim_dat_o[19] , |
| \wbd_spim_dat_o[18] , |
| \wbd_spim_dat_o[17] , |
| \wbd_spim_dat_o[16] , |
| \wbd_spim_dat_o[15] , |
| \wbd_spim_dat_o[14] , |
| \wbd_spim_dat_o[13] , |
| \wbd_spim_dat_o[12] , |
| \wbd_spim_dat_o[11] , |
| \wbd_spim_dat_o[10] , |
| \wbd_spim_dat_o[9] , |
| \wbd_spim_dat_o[8] , |
| \wbd_spim_dat_o[7] , |
| \wbd_spim_dat_o[6] , |
| \wbd_spim_dat_o[5] , |
| \wbd_spim_dat_o[4] , |
| \wbd_spim_dat_o[3] , |
| \wbd_spim_dat_o[2] , |
| \wbd_spim_dat_o[1] , |
| \wbd_spim_dat_o[0] }), |
| .s0_wbd_sel_o({\wbd_spim_sel_o[3] , |
| \wbd_spim_sel_o[2] , |
| \wbd_spim_sel_o[1] , |
| \wbd_spim_sel_o[0] }), |
| .s1_wbd_adr_o({\wbd_uart_adr_o[8] , |
| \wbd_uart_adr_o[7] , |
| \wbd_uart_adr_o[6] , |
| \wbd_uart_adr_o[5] , |
| \wbd_uart_adr_o[4] , |
| \wbd_uart_adr_o[3] , |
| \wbd_uart_adr_o[2] , |
| \wbd_uart_adr_o[1] , |
| \wbd_uart_adr_o[0] }), |
| .s1_wbd_dat_i({\wbd_uart_dat_i[31] , |
| \wbd_uart_dat_i[30] , |
| \wbd_uart_dat_i[29] , |
| \wbd_uart_dat_i[28] , |
| \wbd_uart_dat_i[27] , |
| \wbd_uart_dat_i[26] , |
| \wbd_uart_dat_i[25] , |
| \wbd_uart_dat_i[24] , |
| \wbd_uart_dat_i[23] , |
| \wbd_uart_dat_i[22] , |
| \wbd_uart_dat_i[21] , |
| \wbd_uart_dat_i[20] , |
| \wbd_uart_dat_i[19] , |
| \wbd_uart_dat_i[18] , |
| \wbd_uart_dat_i[17] , |
| \wbd_uart_dat_i[16] , |
| \wbd_uart_dat_i[15] , |
| \wbd_uart_dat_i[14] , |
| \wbd_uart_dat_i[13] , |
| \wbd_uart_dat_i[12] , |
| \wbd_uart_dat_i[11] , |
| \wbd_uart_dat_i[10] , |
| \wbd_uart_dat_i[9] , |
| \wbd_uart_dat_i[8] , |
| \wbd_uart_dat_i[7] , |
| \wbd_uart_dat_i[6] , |
| \wbd_uart_dat_i[5] , |
| \wbd_uart_dat_i[4] , |
| \wbd_uart_dat_i[3] , |
| \wbd_uart_dat_i[2] , |
| \wbd_uart_dat_i[1] , |
| \wbd_uart_dat_i[0] }), |
| .s1_wbd_dat_o({\wbd_uart_dat_o[31] , |
| \wbd_uart_dat_o[30] , |
| \wbd_uart_dat_o[29] , |
| \wbd_uart_dat_o[28] , |
| \wbd_uart_dat_o[27] , |
| \wbd_uart_dat_o[26] , |
| \wbd_uart_dat_o[25] , |
| \wbd_uart_dat_o[24] , |
| \wbd_uart_dat_o[23] , |
| \wbd_uart_dat_o[22] , |
| \wbd_uart_dat_o[21] , |
| \wbd_uart_dat_o[20] , |
| \wbd_uart_dat_o[19] , |
| \wbd_uart_dat_o[18] , |
| \wbd_uart_dat_o[17] , |
| \wbd_uart_dat_o[16] , |
| \wbd_uart_dat_o[15] , |
| \wbd_uart_dat_o[14] , |
| \wbd_uart_dat_o[13] , |
| \wbd_uart_dat_o[12] , |
| \wbd_uart_dat_o[11] , |
| \wbd_uart_dat_o[10] , |
| \wbd_uart_dat_o[9] , |
| \wbd_uart_dat_o[8] , |
| \wbd_uart_dat_o[7] , |
| \wbd_uart_dat_o[6] , |
| \wbd_uart_dat_o[5] , |
| \wbd_uart_dat_o[4] , |
| \wbd_uart_dat_o[3] , |
| \wbd_uart_dat_o[2] , |
| \wbd_uart_dat_o[1] , |
| \wbd_uart_dat_o[0] }), |
| .s1_wbd_sel_o({\wbd_uart_sel_o[3] , |
| \wbd_uart_sel_o[2] , |
| \wbd_uart_sel_o[1] , |
| \wbd_uart_sel_o[0] }), |
| .s2_wbd_adr_o({\wbd_glbl_adr_o[10] , |
| \wbd_glbl_adr_o[9] , |
| \wbd_glbl_adr_o[8] , |
| \wbd_glbl_adr_o[7] , |
| \wbd_glbl_adr_o[6] , |
| \wbd_glbl_adr_o[5] , |
| \wbd_glbl_adr_o[4] , |
| \wbd_glbl_adr_o[3] , |
| \wbd_glbl_adr_o[2] , |
| \wbd_glbl_adr_o[1] , |
| \wbd_glbl_adr_o[0] }), |
| .s2_wbd_dat_i({\wbd_glbl_dat_i[31] , |
| \wbd_glbl_dat_i[30] , |
| \wbd_glbl_dat_i[29] , |
| \wbd_glbl_dat_i[28] , |
| \wbd_glbl_dat_i[27] , |
| \wbd_glbl_dat_i[26] , |
| \wbd_glbl_dat_i[25] , |
| \wbd_glbl_dat_i[24] , |
| \wbd_glbl_dat_i[23] , |
| \wbd_glbl_dat_i[22] , |
| \wbd_glbl_dat_i[21] , |
| \wbd_glbl_dat_i[20] , |
| \wbd_glbl_dat_i[19] , |
| \wbd_glbl_dat_i[18] , |
| \wbd_glbl_dat_i[17] , |
| \wbd_glbl_dat_i[16] , |
| \wbd_glbl_dat_i[15] , |
| \wbd_glbl_dat_i[14] , |
| \wbd_glbl_dat_i[13] , |
| \wbd_glbl_dat_i[12] , |
| \wbd_glbl_dat_i[11] , |
| \wbd_glbl_dat_i[10] , |
| \wbd_glbl_dat_i[9] , |
| \wbd_glbl_dat_i[8] , |
| \wbd_glbl_dat_i[7] , |
| \wbd_glbl_dat_i[6] , |
| \wbd_glbl_dat_i[5] , |
| \wbd_glbl_dat_i[4] , |
| \wbd_glbl_dat_i[3] , |
| \wbd_glbl_dat_i[2] , |
| \wbd_glbl_dat_i[1] , |
| \wbd_glbl_dat_i[0] }), |
| .s2_wbd_dat_o({\wbd_glbl_dat_o[31] , |
| \wbd_glbl_dat_o[30] , |
| \wbd_glbl_dat_o[29] , |
| \wbd_glbl_dat_o[28] , |
| \wbd_glbl_dat_o[27] , |
| \wbd_glbl_dat_o[26] , |
| \wbd_glbl_dat_o[25] , |
| \wbd_glbl_dat_o[24] , |
| \wbd_glbl_dat_o[23] , |
| \wbd_glbl_dat_o[22] , |
| \wbd_glbl_dat_o[21] , |
| \wbd_glbl_dat_o[20] , |
| \wbd_glbl_dat_o[19] , |
| \wbd_glbl_dat_o[18] , |
| \wbd_glbl_dat_o[17] , |
| \wbd_glbl_dat_o[16] , |
| \wbd_glbl_dat_o[15] , |
| \wbd_glbl_dat_o[14] , |
| \wbd_glbl_dat_o[13] , |
| \wbd_glbl_dat_o[12] , |
| \wbd_glbl_dat_o[11] , |
| \wbd_glbl_dat_o[10] , |
| \wbd_glbl_dat_o[9] , |
| \wbd_glbl_dat_o[8] , |
| \wbd_glbl_dat_o[7] , |
| \wbd_glbl_dat_o[6] , |
| \wbd_glbl_dat_o[5] , |
| \wbd_glbl_dat_o[4] , |
| \wbd_glbl_dat_o[3] , |
| \wbd_glbl_dat_o[2] , |
| \wbd_glbl_dat_o[1] , |
| \wbd_glbl_dat_o[0] }), |
| .s2_wbd_sel_o({\wbd_glbl_sel_o[3] , |
| \wbd_glbl_sel_o[2] , |
| \wbd_glbl_sel_o[1] , |
| \wbd_glbl_sel_o[0] })); |
| peri_top u_peri (.ir_intr(ir_intr), |
| .ir_rx(ir_rx), |
| .ir_tx(ir_tx), |
| .mclk(wbd_clk_peri_skew), |
| .reg_ack(reg_peri_ack), |
| .reg_cs(reg_peri_cs), |
| .reg_wr(reg_peri_wr), |
| .rtc_clk(\u_riscv_top.rtc_clk ), |
| .rtc_intr(rtc_intr), |
| .s_reset_n(\u_riscv_top.pwrup_rst_n ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(wbd_clk_peri_rp), |
| .wbd_clk_peri(wbd_clk_peri_skew), |
| .cfg_cska_peri({\cfg_wcska_peri_rp[3] , |
| \cfg_wcska_peri_rp[2] , |
| \cfg_wcska_peri_rp[1] , |
| \cfg_wcska_peri_rp[0] }), |
| .cfg_dac0_mux_sel({\cfg_dac0_mux_sel[7] , |
| \cfg_dac0_mux_sel[6] , |
| \cfg_dac0_mux_sel[5] , |
| \cfg_dac0_mux_sel[4] , |
| \cfg_dac0_mux_sel[3] , |
| \cfg_dac0_mux_sel[2] , |
| \cfg_dac0_mux_sel[1] , |
| \cfg_dac0_mux_sel[0] }), |
| .cfg_dac1_mux_sel({\cfg_dac1_mux_sel[7] , |
| \cfg_dac1_mux_sel[6] , |
| \cfg_dac1_mux_sel[5] , |
| \cfg_dac1_mux_sel[4] , |
| \cfg_dac1_mux_sel[3] , |
| \cfg_dac1_mux_sel[2] , |
| \cfg_dac1_mux_sel[1] , |
| \cfg_dac1_mux_sel[0] }), |
| .cfg_dac2_mux_sel({\cfg_dac2_mux_sel[7] , |
| \cfg_dac2_mux_sel[6] , |
| \cfg_dac2_mux_sel[5] , |
| \cfg_dac2_mux_sel[4] , |
| \cfg_dac2_mux_sel[3] , |
| \cfg_dac2_mux_sel[2] , |
| \cfg_dac2_mux_sel[1] , |
| \cfg_dac2_mux_sel[0] }), |
| .cfg_dac3_mux_sel({\cfg_dac3_mux_sel[7] , |
| \cfg_dac3_mux_sel[6] , |
| \cfg_dac3_mux_sel[5] , |
| \cfg_dac3_mux_sel[4] , |
| \cfg_dac3_mux_sel[3] , |
| \cfg_dac3_mux_sel[2] , |
| \cfg_dac3_mux_sel[1] , |
| \cfg_dac3_mux_sel[0] }), |
| .reg_addr({\reg_peri_addr[10] , |
| \reg_peri_addr[9] , |
| \reg_peri_addr[8] , |
| \reg_peri_addr[7] , |
| \reg_peri_addr[6] , |
| \reg_peri_addr[5] , |
| \reg_peri_addr[4] , |
| \reg_peri_addr[3] , |
| \reg_peri_addr[2] , |
| \reg_peri_addr[1] , |
| \reg_peri_addr[0] }), |
| .reg_be({\reg_peri_be[3] , |
| \reg_peri_be[2] , |
| \reg_peri_be[1] , |
| \reg_peri_be[0] }), |
| .reg_rdata({\reg_peri_rdata[31] , |
| \reg_peri_rdata[30] , |
| \reg_peri_rdata[29] , |
| \reg_peri_rdata[28] , |
| \reg_peri_rdata[27] , |
| \reg_peri_rdata[26] , |
| \reg_peri_rdata[25] , |
| \reg_peri_rdata[24] , |
| \reg_peri_rdata[23] , |
| \reg_peri_rdata[22] , |
| \reg_peri_rdata[21] , |
| \reg_peri_rdata[20] , |
| \reg_peri_rdata[19] , |
| \reg_peri_rdata[18] , |
| \reg_peri_rdata[17] , |
| \reg_peri_rdata[16] , |
| \reg_peri_rdata[15] , |
| \reg_peri_rdata[14] , |
| \reg_peri_rdata[13] , |
| \reg_peri_rdata[12] , |
| \reg_peri_rdata[11] , |
| \reg_peri_rdata[10] , |
| \reg_peri_rdata[9] , |
| \reg_peri_rdata[8] , |
| \reg_peri_rdata[7] , |
| \reg_peri_rdata[6] , |
| \reg_peri_rdata[5] , |
| \reg_peri_rdata[4] , |
| \reg_peri_rdata[3] , |
| \reg_peri_rdata[2] , |
| \reg_peri_rdata[1] , |
| \reg_peri_rdata[0] }), |
| .reg_wdata({\reg_peri_wdata[31] , |
| \reg_peri_wdata[30] , |
| \reg_peri_wdata[29] , |
| \reg_peri_wdata[28] , |
| \reg_peri_wdata[27] , |
| \reg_peri_wdata[26] , |
| \reg_peri_wdata[25] , |
| \reg_peri_wdata[24] , |
| \reg_peri_wdata[23] , |
| \reg_peri_wdata[22] , |
| \reg_peri_wdata[21] , |
| \reg_peri_wdata[20] , |
| \reg_peri_wdata[19] , |
| \reg_peri_wdata[18] , |
| \reg_peri_wdata[17] , |
| \reg_peri_wdata[16] , |
| \reg_peri_wdata[15] , |
| \reg_peri_wdata[14] , |
| \reg_peri_wdata[13] , |
| \reg_peri_wdata[12] , |
| \reg_peri_wdata[11] , |
| \reg_peri_wdata[10] , |
| \reg_peri_wdata[9] , |
| \reg_peri_wdata[8] , |
| \reg_peri_wdata[7] , |
| \reg_peri_wdata[6] , |
| \reg_peri_wdata[5] , |
| \reg_peri_wdata[4] , |
| \reg_peri_wdata[3] , |
| \reg_peri_wdata[2] , |
| \reg_peri_wdata[1] , |
| \reg_peri_wdata[0] })); |
| pinmux_top u_pinmux (.cfg_dco_mode(cfg_dco_mode), |
| .cfg_pll_enb(cfg_pll_enb), |
| .cfg_strap_pad_ctrl(cfg_strap_pad_ctrl_rp), |
| .cpu_clk(\cpu_clk_rp[2] ), |
| .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ), |
| .e_reset_n(e_reset_n_rp), |
| .i2cm_clk_i(i2cm_clk_i), |
| .i2cm_clk_o(i2cm_clk_o), |
| .i2cm_clk_oen(i2cm_clk_oen), |
| .i2cm_data_i(i2cm_data_i), |
| .i2cm_data_o(i2cm_data_o), |
| .i2cm_data_oen(i2cm_data_oen), |
| .i2cm_intr(i2cm_intr_o), |
| .i2cm_rst_n(i2c_rst_n), |
| .int_pll_clock(\pll_clk_out[0] ), |
| .ir_intr(ir_intr), |
| .ir_rx(ir_rx), |
| .ir_tx(ir_tx), |
| .mclk(wbd_clk_pinmux_skew), |
| .p_reset_n(p_reset_n_rp), |
| .pll_ref_clk(pll_ref_clk), |
| .pulse1m_mclk(pulse1m_mclk), |
| .qspim_rst_n(qspim_rst_n), |
| .reg_ack(wbd_glbl_ack_i), |
| .reg_cs(wbd_glbl_stb_o), |
| .reg_peri_ack(reg_peri_ack), |
| .reg_peri_cs(reg_peri_cs), |
| .reg_peri_wr(reg_peri_wr), |
| .reg_wr(wbd_glbl_we_o), |
| .rtc_clk(\u_riscv_top.rtc_clk ), |
| .rtc_intr(rtc_intr), |
| .s_reset_n(\u_riscv_top.pwrup_rst_n ), |
| .sflash_sck(sflash_sck), |
| .soft_irq(soft_irq), |
| .spim_miso(sspim_so), |
| .spim_mosi(sspim_si), |
| .spim_sck(sspim_sck), |
| .spis_miso(sspis_so), |
| .spis_mosi(sspis_si), |
| .spis_sck(sspis_sck), |
| .spis_ssn(sspis_ssn), |
| .sspim_rst_n(sspim_rst_n), |
| .uartm_rxd(uartm_rxd), |
| .uartm_txd(uartm_txd), |
| .usb_clk(usb_clk), |
| .usb_dn_i(usb_dn_i), |
| .usb_dn_o(usb_dn_o), |
| .usb_dp_i(usb_dp_i), |
| .usb_dp_o(usb_dp_o), |
| .usb_intr(usb_intr_o), |
| .usb_oen(usb_oen), |
| .usb_rst_n(usb_rst_n), |
| .user_clock1(\ch_out_south[0] ), |
| .user_clock2(\ch_out_south[252] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(wbd_clk_pinmux_rp), |
| .wbd_clk_pinmux(wbd_clk_pinmux_skew), |
| .xtal_clk(xtal_clk), |
| .cfg_cska_pinmux({\cfg_wcska_pinmux_rp[3] , |
| \cfg_wcska_pinmux_rp[2] , |
| \cfg_wcska_pinmux_rp[1] , |
| \cfg_wcska_pinmux_rp[0] }), |
| .cfg_dc_trim({\cfg_dc_trim[25] , |
| \cfg_dc_trim[24] , |
| \cfg_dc_trim[23] , |
| \cfg_dc_trim[22] , |
| \cfg_dc_trim[21] , |
| \cfg_dc_trim[20] , |
| \cfg_dc_trim[19] , |
| \cfg_dc_trim[18] , |
| \cfg_dc_trim[17] , |
| \cfg_dc_trim[16] , |
| \cfg_dc_trim[15] , |
| \cfg_dc_trim[14] , |
| \cfg_dc_trim[13] , |
| \cfg_dc_trim[12] , |
| \cfg_dc_trim[11] , |
| \cfg_dc_trim[10] , |
| \cfg_dc_trim[9] , |
| \cfg_dc_trim[8] , |
| \cfg_dc_trim[7] , |
| \cfg_dc_trim[6] , |
| \cfg_dc_trim[5] , |
| \cfg_dc_trim[4] , |
| \cfg_dc_trim[3] , |
| \cfg_dc_trim[2] , |
| \cfg_dc_trim[1] , |
| \cfg_dc_trim[0] }), |
| .cfg_pll_fed_div({\cfg_pll_fed_div[4] , |
| \cfg_pll_fed_div[3] , |
| \cfg_pll_fed_div[2] , |
| \cfg_pll_fed_div[1] , |
| \cfg_pll_fed_div[0] }), |
| .cfg_riscv_ctrl({\cfg_riscv_ctrl[15] , |
| \cfg_riscv_ctrl[14] , |
| \cfg_riscv_ctrl[13] , |
| \cfg_riscv_ctrl[12] , |
| \cfg_riscv_ctrl[11] , |
| \cfg_riscv_ctrl[10] , |
| \cfg_riscv_ctrl[9] , |
| \cfg_riscv_ctrl[8] , |
| \cfg_riscv_ctrl[7] , |
| \cfg_riscv_ctrl[6] , |
| \cfg_riscv_ctrl[5] , |
| \cfg_riscv_ctrl[4] , |
| \cfg_riscv_ctrl[3] , |
| \cfg_riscv_ctrl[2] , |
| \cfg_riscv_ctrl[1] , |
| \cfg_riscv_ctrl[0] }), |
| .cpu_core_rst_n({\cpu_core_rst_n[3] , |
| \cpu_core_rst_n[2] , |
| \cpu_core_rst_n[1] , |
| \cpu_core_rst_n[0] }), |
| .digital_io_in({\buf_out_north[39] , |
| \buf_out_north[36] , |
| \buf_out_north[33] , |
| \buf_out_north[30] , |
| \buf_out_north[27] , |
| \buf_out_north[24] , |
| \buf_out_north[21] , |
| \buf_out_north[18] , |
| \buf_out_north[15] , |
| \buf_out_north[12] , |
| \buf_out_north[9] , |
| \buf_out_north[6] , |
| \buf_out_north[3] , |
| \buf_out_north[0] , |
| \ch_out_north[2] , |
| \ch_out_north[5] , |
| \ch_out_north[8] , |
| \ch_out_north[11] , |
| \ch_out_north[14] , |
| \ch_out_north[17] , |
| \ch_out_north[20] , |
| \ch_out_north[23] , |
| \ch_out_north[26] , |
| \ch_out_east[2] , |
| \ch_out_east[5] , |
| \ch_out_east[8] , |
| \ch_out_east[11] , |
| \ch_out_east[14] , |
| \ch_out_east[17] , |
| \ch_out_east[20] , |
| \ch_out_east[23] , |
| \ch_out_east[26] , |
| \ch_out_east[29] , |
| \ch_out_east[32] , |
| \ch_out_east[35] , |
| \ch_out_east[38] , |
| \ch_out_east[41] , |
| \ch_out_east[44] }), |
| .digital_io_oen({\io_oeb_int[37] , |
| \io_oeb_int[36] , |
| \io_oeb_int[35] , |
| \io_oeb_int[34] , |
| \io_oeb_int[33] , |
| \io_oeb_int[32] , |
| \io_oeb_int[31] , |
| \io_oeb_int[30] , |
| \io_oeb_int[29] , |
| \io_oeb_int[28] , |
| \io_oeb_int[27] , |
| \io_oeb_int[26] , |
| \io_oeb_int[25] , |
| \io_oeb_int[24] , |
| \io_oeb_int[23] , |
| \io_oeb_int[22] , |
| \io_oeb_int[21] , |
| \io_oeb_int[20] , |
| \io_oeb_int[19] , |
| \io_oeb_int[18] , |
| \io_oeb_int[17] , |
| \io_oeb_int[16] , |
| \io_oeb_int[15] , |
| \io_oeb_int[14] , |
| \io_oeb_int[13] , |
| \io_oeb_int[12] , |
| \io_oeb_int[11] , |
| \io_oeb_int[10] , |
| \io_oeb_int[9] , |
| \io_oeb_int[8] , |
| \io_oeb_int[7] , |
| \io_oeb_int[6] , |
| \io_oeb_int[5] , |
| \io_oeb_int[4] , |
| \io_oeb_int[3] , |
| \io_oeb_int[2] , |
| \io_oeb_int[1] , |
| \io_oeb_int[0] }), |
| .digital_io_out({\io_out_int[37] , |
| \io_out_int[36] , |
| \io_out_int[35] , |
| \io_out_int[34] , |
| \io_out_int[33] , |
| \io_out_int[32] , |
| \io_out_int[31] , |
| \io_out_int[30] , |
| \io_out_int[29] , |
| \io_out_int[28] , |
| \io_out_int[27] , |
| \io_out_int[26] , |
| \io_out_int[25] , |
| \io_out_int[24] , |
| \io_out_int[23] , |
| \io_out_int[22] , |
| \io_out_int[21] , |
| \io_out_int[20] , |
| \io_out_int[19] , |
| \io_out_int[18] , |
| \io_out_int[17] , |
| \io_out_int[16] , |
| \io_out_int[15] , |
| \io_out_int[14] , |
| \io_out_int[13] , |
| \io_out_int[12] , |
| \io_out_int[11] , |
| \io_out_int[10] , |
| \io_out_int[9] , |
| \io_out_int[8] , |
| \io_out_int[7] , |
| \io_out_int[6] , |
| \io_out_int[5] , |
| \io_out_int[4] , |
| \io_out_int[3] , |
| \io_out_int[2] , |
| \io_out_int[1] , |
| \io_out_int[0] }), |
| .irq_lines({\irq_lines[31] , |
| \irq_lines[30] , |
| \irq_lines[29] , |
| \irq_lines[28] , |
| \irq_lines[27] , |
| \irq_lines[26] , |
| \irq_lines[25] , |
| \irq_lines[24] , |
| \irq_lines[23] , |
| \irq_lines[22] , |
| \irq_lines[21] , |
| \irq_lines[20] , |
| \irq_lines[19] , |
| \irq_lines[18] , |
| \irq_lines[17] , |
| \irq_lines[16] , |
| \irq_lines[15] , |
| \irq_lines[14] , |
| \irq_lines[13] , |
| \irq_lines[12] , |
| \irq_lines[11] , |
| \irq_lines[10] , |
| \irq_lines[9] , |
| \irq_lines[8] , |
| \irq_lines[7] , |
| \irq_lines[6] , |
| \irq_lines[5] , |
| \irq_lines[4] , |
| \irq_lines[3] , |
| \irq_lines[2] , |
| \irq_lines[1] , |
| \irq_lines[0] }), |
| .pinmux_debug({\pinmux_debug[31] , |
| \pinmux_debug[30] , |
| \pinmux_debug[29] , |
| \pinmux_debug[28] , |
| \pinmux_debug[27] , |
| \pinmux_debug[26] , |
| \pinmux_debug[25] , |
| \pinmux_debug[24] , |
| \pinmux_debug[23] , |
| \pinmux_debug[22] , |
| \pinmux_debug[21] , |
| \pinmux_debug[20] , |
| \pinmux_debug[19] , |
| \pinmux_debug[18] , |
| \pinmux_debug[17] , |
| \pinmux_debug[16] , |
| \pinmux_debug[15] , |
| \pinmux_debug[14] , |
| \pinmux_debug[13] , |
| \pinmux_debug[12] , |
| \pinmux_debug[11] , |
| \pinmux_debug[10] , |
| \pinmux_debug[9] , |
| \pinmux_debug[8] , |
| \pinmux_debug[7] , |
| \pinmux_debug[6] , |
| \pinmux_debug[5] , |
| \pinmux_debug[4] , |
| \pinmux_debug[3] , |
| \pinmux_debug[2] , |
| \pinmux_debug[1] , |
| \pinmux_debug[0] }), |
| .reg_addr({\wbd_glbl_adr_o[10] , |
| \wbd_glbl_adr_o[9] , |
| \wbd_glbl_adr_o[8] , |
| \wbd_glbl_adr_o[7] , |
| \wbd_glbl_adr_o[6] , |
| \wbd_glbl_adr_o[5] , |
| \wbd_glbl_adr_o[4] , |
| \wbd_glbl_adr_o[3] , |
| \wbd_glbl_adr_o[2] , |
| \wbd_glbl_adr_o[1] , |
| \wbd_glbl_adr_o[0] }), |
| .reg_be({\wbd_glbl_sel_o[3] , |
| \wbd_glbl_sel_o[2] , |
| \wbd_glbl_sel_o[1] , |
| \wbd_glbl_sel_o[0] }), |
| .reg_peri_addr({\reg_peri_addr[10] , |
| \reg_peri_addr[9] , |
| \reg_peri_addr[8] , |
| \reg_peri_addr[7] , |
| \reg_peri_addr[6] , |
| \reg_peri_addr[5] , |
| \reg_peri_addr[4] , |
| \reg_peri_addr[3] , |
| \reg_peri_addr[2] , |
| \reg_peri_addr[1] , |
| \reg_peri_addr[0] }), |
| .reg_peri_be({\reg_peri_be[3] , |
| \reg_peri_be[2] , |
| \reg_peri_be[1] , |
| \reg_peri_be[0] }), |
| .reg_peri_rdata({\reg_peri_rdata[31] , |
| \reg_peri_rdata[30] , |
| \reg_peri_rdata[29] , |
| \reg_peri_rdata[28] , |
| \reg_peri_rdata[27] , |
| \reg_peri_rdata[26] , |
| \reg_peri_rdata[25] , |
| \reg_peri_rdata[24] , |
| \reg_peri_rdata[23] , |
| \reg_peri_rdata[22] , |
| \reg_peri_rdata[21] , |
| \reg_peri_rdata[20] , |
| \reg_peri_rdata[19] , |
| \reg_peri_rdata[18] , |
| \reg_peri_rdata[17] , |
| \reg_peri_rdata[16] , |
| \reg_peri_rdata[15] , |
| \reg_peri_rdata[14] , |
| \reg_peri_rdata[13] , |
| \reg_peri_rdata[12] , |
| \reg_peri_rdata[11] , |
| \reg_peri_rdata[10] , |
| \reg_peri_rdata[9] , |
| \reg_peri_rdata[8] , |
| \reg_peri_rdata[7] , |
| \reg_peri_rdata[6] , |
| \reg_peri_rdata[5] , |
| \reg_peri_rdata[4] , |
| \reg_peri_rdata[3] , |
| \reg_peri_rdata[2] , |
| \reg_peri_rdata[1] , |
| \reg_peri_rdata[0] }), |
| .reg_peri_wdata({\reg_peri_wdata[31] , |
| \reg_peri_wdata[30] , |
| \reg_peri_wdata[29] , |
| \reg_peri_wdata[28] , |
| \reg_peri_wdata[27] , |
| \reg_peri_wdata[26] , |
| \reg_peri_wdata[25] , |
| \reg_peri_wdata[24] , |
| \reg_peri_wdata[23] , |
| \reg_peri_wdata[22] , |
| \reg_peri_wdata[21] , |
| \reg_peri_wdata[20] , |
| \reg_peri_wdata[19] , |
| \reg_peri_wdata[18] , |
| \reg_peri_wdata[17] , |
| \reg_peri_wdata[16] , |
| \reg_peri_wdata[15] , |
| \reg_peri_wdata[14] , |
| \reg_peri_wdata[13] , |
| \reg_peri_wdata[12] , |
| \reg_peri_wdata[11] , |
| \reg_peri_wdata[10] , |
| \reg_peri_wdata[9] , |
| \reg_peri_wdata[8] , |
| \reg_peri_wdata[7] , |
| \reg_peri_wdata[6] , |
| \reg_peri_wdata[5] , |
| \reg_peri_wdata[4] , |
| \reg_peri_wdata[3] , |
| \reg_peri_wdata[2] , |
| \reg_peri_wdata[1] , |
| \reg_peri_wdata[0] }), |
| .reg_rdata({\wbd_glbl_dat_i[31] , |
| \wbd_glbl_dat_i[30] , |
| \wbd_glbl_dat_i[29] , |
| \wbd_glbl_dat_i[28] , |
| \wbd_glbl_dat_i[27] , |
| \wbd_glbl_dat_i[26] , |
| \wbd_glbl_dat_i[25] , |
| \wbd_glbl_dat_i[24] , |
| \wbd_glbl_dat_i[23] , |
| \wbd_glbl_dat_i[22] , |
| \wbd_glbl_dat_i[21] , |
| \wbd_glbl_dat_i[20] , |
| \wbd_glbl_dat_i[19] , |
| \wbd_glbl_dat_i[18] , |
| \wbd_glbl_dat_i[17] , |
| \wbd_glbl_dat_i[16] , |
| \wbd_glbl_dat_i[15] , |
| \wbd_glbl_dat_i[14] , |
| \wbd_glbl_dat_i[13] , |
| \wbd_glbl_dat_i[12] , |
| \wbd_glbl_dat_i[11] , |
| \wbd_glbl_dat_i[10] , |
| \wbd_glbl_dat_i[9] , |
| \wbd_glbl_dat_i[8] , |
| \wbd_glbl_dat_i[7] , |
| \wbd_glbl_dat_i[6] , |
| \wbd_glbl_dat_i[5] , |
| \wbd_glbl_dat_i[4] , |
| \wbd_glbl_dat_i[3] , |
| \wbd_glbl_dat_i[2] , |
| \wbd_glbl_dat_i[1] , |
| \wbd_glbl_dat_i[0] }), |
| .reg_wdata({\wbd_glbl_dat_o[31] , |
| \wbd_glbl_dat_o[30] , |
| \wbd_glbl_dat_o[29] , |
| \wbd_glbl_dat_o[28] , |
| \wbd_glbl_dat_o[27] , |
| \wbd_glbl_dat_o[26] , |
| \wbd_glbl_dat_o[25] , |
| \wbd_glbl_dat_o[24] , |
| \wbd_glbl_dat_o[23] , |
| \wbd_glbl_dat_o[22] , |
| \wbd_glbl_dat_o[21] , |
| \wbd_glbl_dat_o[20] , |
| \wbd_glbl_dat_o[19] , |
| \wbd_glbl_dat_o[18] , |
| \wbd_glbl_dat_o[17] , |
| \wbd_glbl_dat_o[16] , |
| \wbd_glbl_dat_o[15] , |
| \wbd_glbl_dat_o[14] , |
| \wbd_glbl_dat_o[13] , |
| \wbd_glbl_dat_o[12] , |
| \wbd_glbl_dat_o[11] , |
| \wbd_glbl_dat_o[10] , |
| \wbd_glbl_dat_o[9] , |
| \wbd_glbl_dat_o[8] , |
| \wbd_glbl_dat_o[7] , |
| \wbd_glbl_dat_o[6] , |
| \wbd_glbl_dat_o[5] , |
| \wbd_glbl_dat_o[4] , |
| \wbd_glbl_dat_o[3] , |
| \wbd_glbl_dat_o[2] , |
| \wbd_glbl_dat_o[1] , |
| \wbd_glbl_dat_o[0] }), |
| .sflash_di({\sflash_di[3] , |
| \sflash_di[2] , |
| \sflash_di[1] , |
| \sflash_di[0] }), |
| .sflash_do({\sflash_do[3] , |
| \sflash_do[2] , |
| \sflash_do[1] , |
| \sflash_do[0] }), |
| .sflash_oen({\sflash_oen[3] , |
| \sflash_oen[2] , |
| \sflash_oen[1] , |
| \sflash_oen[0] }), |
| .sflash_ss({\spi_csn[3] , |
| \spi_csn[2] , |
| \spi_csn[1] , |
| \spi_csn[0] }), |
| .spim_ssn({\sspim_ssn[3] , |
| \sspim_ssn[2] , |
| \sspim_ssn[1] , |
| \sspim_ssn[0] }), |
| .strap_sticky({\strap_sticky[31] , |
| \strap_sticky[30] , |
| \strap_sticky[29] , |
| \strap_sticky[28] , |
| \strap_sticky[27] , |
| \strap_sticky[26] , |
| \strap_sticky[25] , |
| \strap_sticky[24] , |
| \strap_sticky[23] , |
| \strap_sticky[22] , |
| \strap_sticky[21] , |
| \strap_sticky[20] , |
| \strap_sticky[19] , |
| \strap_sticky[18] , |
| \strap_sticky[17] , |
| \strap_sticky[16] , |
| \strap_sticky[15] , |
| \strap_sticky[14] , |
| \strap_sticky[13] , |
| \strap_sticky[12] , |
| \strap_sticky[11] , |
| \strap_sticky[10] , |
| \strap_sticky[9] , |
| \strap_sticky[8] , |
| \strap_sticky[7] , |
| \strap_sticky[6] , |
| \strap_sticky[5] , |
| \strap_sticky[4] , |
| \strap_sticky[3] , |
| \strap_sticky[2] , |
| \strap_sticky[1] , |
| \strap_sticky[0] }), |
| .strap_uartm({\strap_uartm[1] , |
| \strap_uartm[0] }), |
| .system_strap({\system_strap_rp[31] , |
| \system_strap_rp[30] , |
| \system_strap_rp[29] , |
| \system_strap_rp[28] , |
| \system_strap_rp[27] , |
| \system_strap_rp[26] , |
| \system_strap_rp[25] , |
| \system_strap_rp[24] , |
| \system_strap_rp[23] , |
| \system_strap_rp[22] , |
| \system_strap_rp[21] , |
| \system_strap_rp[20] , |
| \system_strap_rp[19] , |
| \system_strap_rp[18] , |
| \system_strap_rp[17] , |
| \system_strap_rp[16] , |
| \system_strap_rp[15] , |
| \system_strap_rp[14] , |
| \system_strap_rp[13] , |
| \system_strap_rp[12] , |
| \system_strap_rp[11] , |
| \system_strap_rp[10] , |
| \system_strap_rp[9] , |
| \system_strap_rp[8] , |
| \system_strap_rp[7] , |
| \system_strap_rp[6] , |
| \system_strap_rp[5] , |
| \system_strap_rp[4] , |
| \system_strap_rp[3] , |
| \system_strap_rp[2] , |
| \system_strap_rp[1] , |
| \system_strap_rp[0] }), |
| .uart_rst_n({\uart_rst_n[1] , |
| \uart_rst_n[0] }), |
| .uart_rxd({\uart_rxd[1] , |
| \uart_rxd[0] }), |
| .uart_txd({\uart_txd[1] , |
| \uart_txd[0] }), |
| .user_irq({user_irq[2], |
| user_irq[1], |
| user_irq[0]})); |
| dg_pll u_pll (.VGND(vssd1), |
| .VPWR(vccd1), |
| .dco(cfg_dco_mode), |
| .enable(cfg_pll_enb), |
| .osc(pll_ref_clk), |
| .resetb(wbd_pll_rst_n), |
| .clockp({\pll_clk_out[1] , |
| \pll_clk_out[0] }), |
| .div({\cfg_pll_fed_div[4] , |
| \cfg_pll_fed_div[3] , |
| \cfg_pll_fed_div[2] , |
| \cfg_pll_fed_div[1] , |
| \cfg_pll_fed_div[0] }), |
| .ext_trim({\cfg_dc_trim[25] , |
| \cfg_dc_trim[24] , |
| \cfg_dc_trim[23] , |
| \cfg_dc_trim[22] , |
| \cfg_dc_trim[21] , |
| \cfg_dc_trim[20] , |
| \cfg_dc_trim[19] , |
| \cfg_dc_trim[18] , |
| \cfg_dc_trim[17] , |
| \cfg_dc_trim[16] , |
| \cfg_dc_trim[15] , |
| \cfg_dc_trim[14] , |
| \cfg_dc_trim[13] , |
| \cfg_dc_trim[12] , |
| \cfg_dc_trim[11] , |
| \cfg_dc_trim[10] , |
| \cfg_dc_trim[9] , |
| \cfg_dc_trim[8] , |
| \cfg_dc_trim[7] , |
| \cfg_dc_trim[6] , |
| \cfg_dc_trim[5] , |
| \cfg_dc_trim[4] , |
| \cfg_dc_trim[3] , |
| \cfg_dc_trim[2] , |
| \cfg_dc_trim[1] , |
| \cfg_dc_trim[0] })); |
| qspim_top u_qspi_master (.cfg_init_bypass(\system_strap[30] ), |
| .mclk(wbd_clk_spi), |
| .rst_n(qspim_rst_n), |
| .spi_clk(sflash_sck), |
| .strap_pre_sram(\system_strap[15] ), |
| .strap_sram(\system_strap[9] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_ack_o(wbd_spim_ack_i), |
| .wbd_bry_i(wbd_spim_bry_o), |
| .wbd_clk_int(wbd_clk_qspi_rp), |
| .wbd_clk_spi(wbd_clk_spi), |
| .wbd_err_o(wbd_spim_err_i), |
| .wbd_lack_o(wbd_spim_lack_i), |
| .wbd_stb_i(wbd_spim_stb_o), |
| .wbd_we_i(wbd_spim_we_o), |
| .cfg_cska_sp_co({\cfg_wcska_qspi_co_rp[3] , |
| \cfg_wcska_qspi_co_rp[2] , |
| \cfg_wcska_qspi_co_rp[1] , |
| \cfg_wcska_qspi_co_rp[0] }), |
| .cfg_cska_spi({\cfg_wcska_qspi_rp[3] , |
| \cfg_wcska_qspi_rp[2] , |
| \cfg_wcska_qspi_rp[1] , |
| \cfg_wcska_qspi_rp[0] }), |
| .spi_csn({\spi_csn[3] , |
| \spi_csn[2] , |
| \spi_csn[1] , |
| \spi_csn[0] }), |
| .spi_debug({\spi_debug[31] , |
| \spi_debug[30] , |
| \spi_debug[29] , |
| \spi_debug[28] , |
| \spi_debug[27] , |
| \spi_debug[26] , |
| \spi_debug[25] , |
| \spi_debug[24] , |
| \spi_debug[23] , |
| \spi_debug[22] , |
| \spi_debug[21] , |
| \spi_debug[20] , |
| \spi_debug[19] , |
| \spi_debug[18] , |
| \spi_debug[17] , |
| \spi_debug[16] , |
| \spi_debug[15] , |
| \spi_debug[14] , |
| \spi_debug[13] , |
| \spi_debug[12] , |
| \spi_debug[11] , |
| \spi_debug[10] , |
| \spi_debug[9] , |
| \spi_debug[8] , |
| \spi_debug[7] , |
| \spi_debug[6] , |
| \spi_debug[5] , |
| \spi_debug[4] , |
| \spi_debug[3] , |
| \spi_debug[2] , |
| \spi_debug[1] , |
| \spi_debug[0] }), |
| .spi_oen({\sflash_oen[3] , |
| \sflash_oen[2] , |
| \sflash_oen[1] , |
| \sflash_oen[0] }), |
| .spi_sdi({\sflash_di[3] , |
| \sflash_di[2] , |
| \sflash_di[1] , |
| \sflash_di[0] }), |
| .spi_sdo({\sflash_do[3] , |
| \sflash_do[2] , |
| \sflash_do[1] , |
| \sflash_do[0] }), |
| .strap_flash({\system_strap[11] , |
| \system_strap[10] }), |
| .wbd_adr_i({\wbd_spim_adr_o[31] , |
| \wbd_spim_adr_o[30] , |
| \wbd_spim_adr_o[29] , |
| \wbd_spim_adr_o[28] , |
| \wbd_spim_adr_o[27] , |
| \wbd_spim_adr_o[26] , |
| \wbd_spim_adr_o[25] , |
| \wbd_spim_adr_o[24] , |
| \wbd_spim_adr_o[23] , |
| \wbd_spim_adr_o[22] , |
| \wbd_spim_adr_o[21] , |
| \wbd_spim_adr_o[20] , |
| \wbd_spim_adr_o[19] , |
| \wbd_spim_adr_o[18] , |
| \wbd_spim_adr_o[17] , |
| \wbd_spim_adr_o[16] , |
| \wbd_spim_adr_o[15] , |
| \wbd_spim_adr_o[14] , |
| \wbd_spim_adr_o[13] , |
| \wbd_spim_adr_o[12] , |
| \wbd_spim_adr_o[11] , |
| \wbd_spim_adr_o[10] , |
| \wbd_spim_adr_o[9] , |
| \wbd_spim_adr_o[8] , |
| \wbd_spim_adr_o[7] , |
| \wbd_spim_adr_o[6] , |
| \wbd_spim_adr_o[5] , |
| \wbd_spim_adr_o[4] , |
| \wbd_spim_adr_o[3] , |
| \wbd_spim_adr_o[2] , |
| \wbd_spim_adr_o[1] , |
| \wbd_spim_adr_o[0] }), |
| .wbd_bl_i({\wbd_spim_bl_o[9] , |
| \wbd_spim_bl_o[8] , |
| \wbd_spim_bl_o[7] , |
| \wbd_spim_bl_o[6] , |
| \wbd_spim_bl_o[5] , |
| \wbd_spim_bl_o[4] , |
| \wbd_spim_bl_o[3] , |
| \wbd_spim_bl_o[2] , |
| \wbd_spim_bl_o[1] , |
| \wbd_spim_bl_o[0] }), |
| .wbd_dat_i({\wbd_spim_dat_o[31] , |
| \wbd_spim_dat_o[30] , |
| \wbd_spim_dat_o[29] , |
| \wbd_spim_dat_o[28] , |
| \wbd_spim_dat_o[27] , |
| \wbd_spim_dat_o[26] , |
| \wbd_spim_dat_o[25] , |
| \wbd_spim_dat_o[24] , |
| \wbd_spim_dat_o[23] , |
| \wbd_spim_dat_o[22] , |
| \wbd_spim_dat_o[21] , |
| \wbd_spim_dat_o[20] , |
| \wbd_spim_dat_o[19] , |
| \wbd_spim_dat_o[18] , |
| \wbd_spim_dat_o[17] , |
| \wbd_spim_dat_o[16] , |
| \wbd_spim_dat_o[15] , |
| \wbd_spim_dat_o[14] , |
| \wbd_spim_dat_o[13] , |
| \wbd_spim_dat_o[12] , |
| \wbd_spim_dat_o[11] , |
| \wbd_spim_dat_o[10] , |
| \wbd_spim_dat_o[9] , |
| \wbd_spim_dat_o[8] , |
| \wbd_spim_dat_o[7] , |
| \wbd_spim_dat_o[6] , |
| \wbd_spim_dat_o[5] , |
| \wbd_spim_dat_o[4] , |
| \wbd_spim_dat_o[3] , |
| \wbd_spim_dat_o[2] , |
| \wbd_spim_dat_o[1] , |
| \wbd_spim_dat_o[0] }), |
| .wbd_dat_o({\wbd_spim_dat_i[31] , |
| \wbd_spim_dat_i[30] , |
| \wbd_spim_dat_i[29] , |
| \wbd_spim_dat_i[28] , |
| \wbd_spim_dat_i[27] , |
| \wbd_spim_dat_i[26] , |
| \wbd_spim_dat_i[25] , |
| \wbd_spim_dat_i[24] , |
| \wbd_spim_dat_i[23] , |
| \wbd_spim_dat_i[22] , |
| \wbd_spim_dat_i[21] , |
| \wbd_spim_dat_i[20] , |
| \wbd_spim_dat_i[19] , |
| \wbd_spim_dat_i[18] , |
| \wbd_spim_dat_i[17] , |
| \wbd_spim_dat_i[16] , |
| \wbd_spim_dat_i[15] , |
| \wbd_spim_dat_i[14] , |
| \wbd_spim_dat_i[13] , |
| \wbd_spim_dat_i[12] , |
| \wbd_spim_dat_i[11] , |
| \wbd_spim_dat_i[10] , |
| \wbd_spim_dat_i[9] , |
| \wbd_spim_dat_i[8] , |
| \wbd_spim_dat_i[7] , |
| \wbd_spim_dat_i[6] , |
| \wbd_spim_dat_i[5] , |
| \wbd_spim_dat_i[4] , |
| \wbd_spim_dat_i[3] , |
| \wbd_spim_dat_i[2] , |
| \wbd_spim_dat_i[1] , |
| \wbd_spim_dat_i[0] }), |
| .wbd_sel_i({\wbd_spim_sel_o[3] , |
| \wbd_spim_sel_o[2] , |
| \wbd_spim_sel_o[1] , |
| \wbd_spim_sel_o[0] })); |
| ycr_core_top \u_riscv_top.i_core_top_0 (.clk(\u_riscv_top.core_clk_core0_skew ), |
| .clk_o(\u_riscv_top.core_clk_out[0] ), |
| .core2dmem_cmd_o(\u_riscv_top.core0_dmem_cmd ), |
| .core2dmem_req_o(\u_riscv_top.core0_dmem_req ), |
| .core2imem_cmd_o(\u_riscv_top.core0_imem_cmd ), |
| .core2imem_req_o(\u_riscv_top.core0_imem_req ), |
| .core_clk_int(\u_riscv_top.core0_clk ), |
| .core_clk_skew(\u_riscv_top.core_clk_core0_skew ), |
| .core_irq_mtimer_i(\u_riscv_top.core0_timer_irq ), |
| .core_irq_soft_i(\u_riscv_top.core0_soft_irq ), |
| .cpu_rst_n(\cpu_core_rst_n[0] ), |
| .dmem2core_req_ack_i(\u_riscv_top.core0_dmem_req_ack ), |
| .imem2core_req_ack_i(\u_riscv_top.core0_imem_req_ack ), |
| .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ), |
| .rst_n(\u_riscv_top.pwrup_rst_n ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core0[3] , |
| \u_riscv_top.cfg_ccska_riscv_core0[2] , |
| \u_riscv_top.cfg_ccska_riscv_core0[1] , |
| \u_riscv_top.cfg_ccska_riscv_core0[0] }), |
| .core2dmem_addr_o({\u_riscv_top.core0_dmem_addr[31] , |
| \u_riscv_top.core0_dmem_addr[30] , |
| \u_riscv_top.core0_dmem_addr[29] , |
| \u_riscv_top.core0_dmem_addr[28] , |
| \u_riscv_top.core0_dmem_addr[27] , |
| \u_riscv_top.core0_dmem_addr[26] , |
| \u_riscv_top.core0_dmem_addr[25] , |
| \u_riscv_top.core0_dmem_addr[24] , |
| \u_riscv_top.core0_dmem_addr[23] , |
| \u_riscv_top.core0_dmem_addr[22] , |
| \u_riscv_top.core0_dmem_addr[21] , |
| \u_riscv_top.core0_dmem_addr[20] , |
| \u_riscv_top.core0_dmem_addr[19] , |
| \u_riscv_top.core0_dmem_addr[18] , |
| \u_riscv_top.core0_dmem_addr[17] , |
| \u_riscv_top.core0_dmem_addr[16] , |
| \u_riscv_top.core0_dmem_addr[15] , |
| \u_riscv_top.core0_dmem_addr[14] , |
| \u_riscv_top.core0_dmem_addr[13] , |
| \u_riscv_top.core0_dmem_addr[12] , |
| \u_riscv_top.core0_dmem_addr[11] , |
| \u_riscv_top.core0_dmem_addr[10] , |
| \u_riscv_top.core0_dmem_addr[9] , |
| \u_riscv_top.core0_dmem_addr[8] , |
| \u_riscv_top.core0_dmem_addr[7] , |
| \u_riscv_top.core0_dmem_addr[6] , |
| \u_riscv_top.core0_dmem_addr[5] , |
| \u_riscv_top.core0_dmem_addr[4] , |
| \u_riscv_top.core0_dmem_addr[3] , |
| \u_riscv_top.core0_dmem_addr[2] , |
| \u_riscv_top.core0_dmem_addr[1] , |
| \u_riscv_top.core0_dmem_addr[0] }), |
| .core2dmem_wdata_o({\u_riscv_top.core0_dmem_wdata[31] , |
| \u_riscv_top.core0_dmem_wdata[30] , |
| \u_riscv_top.core0_dmem_wdata[29] , |
| \u_riscv_top.core0_dmem_wdata[28] , |
| \u_riscv_top.core0_dmem_wdata[27] , |
| \u_riscv_top.core0_dmem_wdata[26] , |
| \u_riscv_top.core0_dmem_wdata[25] , |
| \u_riscv_top.core0_dmem_wdata[24] , |
| \u_riscv_top.core0_dmem_wdata[23] , |
| \u_riscv_top.core0_dmem_wdata[22] , |
| \u_riscv_top.core0_dmem_wdata[21] , |
| \u_riscv_top.core0_dmem_wdata[20] , |
| \u_riscv_top.core0_dmem_wdata[19] , |
| \u_riscv_top.core0_dmem_wdata[18] , |
| \u_riscv_top.core0_dmem_wdata[17] , |
| \u_riscv_top.core0_dmem_wdata[16] , |
| \u_riscv_top.core0_dmem_wdata[15] , |
| \u_riscv_top.core0_dmem_wdata[14] , |
| \u_riscv_top.core0_dmem_wdata[13] , |
| \u_riscv_top.core0_dmem_wdata[12] , |
| \u_riscv_top.core0_dmem_wdata[11] , |
| \u_riscv_top.core0_dmem_wdata[10] , |
| \u_riscv_top.core0_dmem_wdata[9] , |
| \u_riscv_top.core0_dmem_wdata[8] , |
| \u_riscv_top.core0_dmem_wdata[7] , |
| \u_riscv_top.core0_dmem_wdata[6] , |
| \u_riscv_top.core0_dmem_wdata[5] , |
| \u_riscv_top.core0_dmem_wdata[4] , |
| \u_riscv_top.core0_dmem_wdata[3] , |
| \u_riscv_top.core0_dmem_wdata[2] , |
| \u_riscv_top.core0_dmem_wdata[1] , |
| \u_riscv_top.core0_dmem_wdata[0] }), |
| .core2dmem_width_o({\u_riscv_top.core0_dmem_width[1] , |
| \u_riscv_top.core0_dmem_width[0] }), |
| .core2imem_addr_o({\u_riscv_top.core0_imem_addr[31] , |
| \u_riscv_top.core0_imem_addr[30] , |
| \u_riscv_top.core0_imem_addr[29] , |
| \u_riscv_top.core0_imem_addr[28] , |
| \u_riscv_top.core0_imem_addr[27] , |
| \u_riscv_top.core0_imem_addr[26] , |
| \u_riscv_top.core0_imem_addr[25] , |
| \u_riscv_top.core0_imem_addr[24] , |
| \u_riscv_top.core0_imem_addr[23] , |
| \u_riscv_top.core0_imem_addr[22] , |
| \u_riscv_top.core0_imem_addr[21] , |
| \u_riscv_top.core0_imem_addr[20] , |
| \u_riscv_top.core0_imem_addr[19] , |
| \u_riscv_top.core0_imem_addr[18] , |
| \u_riscv_top.core0_imem_addr[17] , |
| \u_riscv_top.core0_imem_addr[16] , |
| \u_riscv_top.core0_imem_addr[15] , |
| \u_riscv_top.core0_imem_addr[14] , |
| \u_riscv_top.core0_imem_addr[13] , |
| \u_riscv_top.core0_imem_addr[12] , |
| \u_riscv_top.core0_imem_addr[11] , |
| \u_riscv_top.core0_imem_addr[10] , |
| \u_riscv_top.core0_imem_addr[9] , |
| \u_riscv_top.core0_imem_addr[8] , |
| \u_riscv_top.core0_imem_addr[7] , |
| \u_riscv_top.core0_imem_addr[6] , |
| \u_riscv_top.core0_imem_addr[5] , |
| \u_riscv_top.core0_imem_addr[4] , |
| \u_riscv_top.core0_imem_addr[3] , |
| \u_riscv_top.core0_imem_addr[2] , |
| \u_riscv_top.core0_imem_addr[1] , |
| \u_riscv_top.core0_imem_addr[0] }), |
| .core2imem_bl_o({\u_riscv_top.core0_imem_bl[2] , |
| \u_riscv_top.core0_imem_bl[1] , |
| \u_riscv_top.core0_imem_bl[0] }), |
| .core_debug({\u_riscv_top.core0_debug[48] , |
| \u_riscv_top.core0_debug[47] , |
| \u_riscv_top.core0_debug[46] , |
| \u_riscv_top.core0_debug[45] , |
| \u_riscv_top.core0_debug[44] , |
| \u_riscv_top.core0_debug[43] , |
| \u_riscv_top.core0_debug[42] , |
| \u_riscv_top.core0_debug[41] , |
| \u_riscv_top.core0_debug[40] , |
| \u_riscv_top.core0_debug[39] , |
| \u_riscv_top.core0_debug[38] , |
| \u_riscv_top.core0_debug[37] , |
| \u_riscv_top.core0_debug[36] , |
| \u_riscv_top.core0_debug[35] , |
| \u_riscv_top.core0_debug[34] , |
| \u_riscv_top.core0_debug[33] , |
| \u_riscv_top.core0_debug[32] , |
| \u_riscv_top.core0_debug[31] , |
| \u_riscv_top.core0_debug[30] , |
| \u_riscv_top.core0_debug[29] , |
| \u_riscv_top.core0_debug[28] , |
| \u_riscv_top.core0_debug[27] , |
| \u_riscv_top.core0_debug[26] , |
| \u_riscv_top.core0_debug[25] , |
| \u_riscv_top.core0_debug[24] , |
| \u_riscv_top.core0_debug[23] , |
| \u_riscv_top.core0_debug[22] , |
| \u_riscv_top.core0_debug[21] , |
| \u_riscv_top.core0_debug[20] , |
| \u_riscv_top.core0_debug[19] , |
| \u_riscv_top.core0_debug[18] , |
| \u_riscv_top.core0_debug[17] , |
| \u_riscv_top.core0_debug[16] , |
| \u_riscv_top.core0_debug[15] , |
| \u_riscv_top.core0_debug[14] , |
| \u_riscv_top.core0_debug[13] , |
| \u_riscv_top.core0_debug[12] , |
| \u_riscv_top.core0_debug[11] , |
| \u_riscv_top.core0_debug[10] , |
| \u_riscv_top.core0_debug[9] , |
| \u_riscv_top.core0_debug[8] , |
| \u_riscv_top.core0_debug[7] , |
| \u_riscv_top.core0_debug[6] , |
| \u_riscv_top.core0_debug[5] , |
| \u_riscv_top.core0_debug[4] , |
| \u_riscv_top.core0_debug[3] , |
| \u_riscv_top.core0_debug[2] , |
| \u_riscv_top.core0_debug[1] , |
| \u_riscv_top.core0_debug[0] }), |
| .core_irq_lines_i({\u_riscv_top.core0_irq_lines[31] , |
| \u_riscv_top.core0_irq_lines[30] , |
| \u_riscv_top.core0_irq_lines[29] , |
| \u_riscv_top.core0_irq_lines[28] , |
| \u_riscv_top.core0_irq_lines[27] , |
| \u_riscv_top.core0_irq_lines[26] , |
| \u_riscv_top.core0_irq_lines[25] , |
| \u_riscv_top.core0_irq_lines[24] , |
| \u_riscv_top.core0_irq_lines[23] , |
| \u_riscv_top.core0_irq_lines[22] , |
| \u_riscv_top.core0_irq_lines[21] , |
| \u_riscv_top.core0_irq_lines[20] , |
| \u_riscv_top.core0_irq_lines[19] , |
| \u_riscv_top.core0_irq_lines[18] , |
| \u_riscv_top.core0_irq_lines[17] , |
| \u_riscv_top.core0_irq_lines[16] , |
| \u_riscv_top.core0_irq_lines[15] , |
| \u_riscv_top.core0_irq_lines[14] , |
| \u_riscv_top.core0_irq_lines[13] , |
| \u_riscv_top.core0_irq_lines[12] , |
| \u_riscv_top.core0_irq_lines[11] , |
| \u_riscv_top.core0_irq_lines[10] , |
| \u_riscv_top.core0_irq_lines[9] , |
| \u_riscv_top.core0_irq_lines[8] , |
| \u_riscv_top.core0_irq_lines[7] , |
| \u_riscv_top.core0_irq_lines[6] , |
| \u_riscv_top.core0_irq_lines[5] , |
| \u_riscv_top.core0_irq_lines[4] , |
| \u_riscv_top.core0_irq_lines[3] , |
| \u_riscv_top.core0_irq_lines[2] , |
| \u_riscv_top.core0_irq_lines[1] , |
| \u_riscv_top.core0_irq_lines[0] }), |
| .core_mtimer_val_i({\u_riscv_top.core0_timer_val[63] , |
| \u_riscv_top.core0_timer_val[62] , |
| \u_riscv_top.core0_timer_val[61] , |
| \u_riscv_top.core0_timer_val[60] , |
| \u_riscv_top.core0_timer_val[59] , |
| \u_riscv_top.core0_timer_val[58] , |
| \u_riscv_top.core0_timer_val[57] , |
| \u_riscv_top.core0_timer_val[56] , |
| \u_riscv_top.core0_timer_val[55] , |
| \u_riscv_top.core0_timer_val[54] , |
| \u_riscv_top.core0_timer_val[53] , |
| \u_riscv_top.core0_timer_val[52] , |
| \u_riscv_top.core0_timer_val[51] , |
| \u_riscv_top.core0_timer_val[50] , |
| \u_riscv_top.core0_timer_val[49] , |
| \u_riscv_top.core0_timer_val[48] , |
| \u_riscv_top.core0_timer_val[47] , |
| \u_riscv_top.core0_timer_val[46] , |
| \u_riscv_top.core0_timer_val[45] , |
| \u_riscv_top.core0_timer_val[44] , |
| \u_riscv_top.core0_timer_val[43] , |
| \u_riscv_top.core0_timer_val[42] , |
| \u_riscv_top.core0_timer_val[41] , |
| \u_riscv_top.core0_timer_val[40] , |
| \u_riscv_top.core0_timer_val[39] , |
| \u_riscv_top.core0_timer_val[38] , |
| \u_riscv_top.core0_timer_val[37] , |
| \u_riscv_top.core0_timer_val[36] , |
| \u_riscv_top.core0_timer_val[35] , |
| \u_riscv_top.core0_timer_val[34] , |
| \u_riscv_top.core0_timer_val[33] , |
| \u_riscv_top.core0_timer_val[32] , |
| \u_riscv_top.core0_timer_val[31] , |
| \u_riscv_top.core0_timer_val[30] , |
| \u_riscv_top.core0_timer_val[29] , |
| \u_riscv_top.core0_timer_val[28] , |
| \u_riscv_top.core0_timer_val[27] , |
| \u_riscv_top.core0_timer_val[26] , |
| \u_riscv_top.core0_timer_val[25] , |
| \u_riscv_top.core0_timer_val[24] , |
| \u_riscv_top.core0_timer_val[23] , |
| \u_riscv_top.core0_timer_val[22] , |
| \u_riscv_top.core0_timer_val[21] , |
| \u_riscv_top.core0_timer_val[20] , |
| \u_riscv_top.core0_timer_val[19] , |
| \u_riscv_top.core0_timer_val[18] , |
| \u_riscv_top.core0_timer_val[17] , |
| \u_riscv_top.core0_timer_val[16] , |
| \u_riscv_top.core0_timer_val[15] , |
| \u_riscv_top.core0_timer_val[14] , |
| \u_riscv_top.core0_timer_val[13] , |
| \u_riscv_top.core0_timer_val[12] , |
| \u_riscv_top.core0_timer_val[11] , |
| \u_riscv_top.core0_timer_val[10] , |
| \u_riscv_top.core0_timer_val[9] , |
| \u_riscv_top.core0_timer_val[8] , |
| \u_riscv_top.core0_timer_val[7] , |
| \u_riscv_top.core0_timer_val[6] , |
| \u_riscv_top.core0_timer_val[5] , |
| \u_riscv_top.core0_timer_val[4] , |
| \u_riscv_top.core0_timer_val[3] , |
| \u_riscv_top.core0_timer_val[2] , |
| \u_riscv_top.core0_timer_val[1] , |
| \u_riscv_top.core0_timer_val[0] }), |
| .core_uid({\u_riscv_top.core0_uid[1] , |
| \u_riscv_top.core0_uid[0] }), |
| .dmem2core_rdata_i({\u_riscv_top.core0_dmem_rdata[31] , |
| \u_riscv_top.core0_dmem_rdata[30] , |
| \u_riscv_top.core0_dmem_rdata[29] , |
| \u_riscv_top.core0_dmem_rdata[28] , |
| \u_riscv_top.core0_dmem_rdata[27] , |
| \u_riscv_top.core0_dmem_rdata[26] , |
| \u_riscv_top.core0_dmem_rdata[25] , |
| \u_riscv_top.core0_dmem_rdata[24] , |
| \u_riscv_top.core0_dmem_rdata[23] , |
| \u_riscv_top.core0_dmem_rdata[22] , |
| \u_riscv_top.core0_dmem_rdata[21] , |
| \u_riscv_top.core0_dmem_rdata[20] , |
| \u_riscv_top.core0_dmem_rdata[19] , |
| \u_riscv_top.core0_dmem_rdata[18] , |
| \u_riscv_top.core0_dmem_rdata[17] , |
| \u_riscv_top.core0_dmem_rdata[16] , |
| \u_riscv_top.core0_dmem_rdata[15] , |
| \u_riscv_top.core0_dmem_rdata[14] , |
| \u_riscv_top.core0_dmem_rdata[13] , |
| \u_riscv_top.core0_dmem_rdata[12] , |
| \u_riscv_top.core0_dmem_rdata[11] , |
| \u_riscv_top.core0_dmem_rdata[10] , |
| \u_riscv_top.core0_dmem_rdata[9] , |
| \u_riscv_top.core0_dmem_rdata[8] , |
| \u_riscv_top.core0_dmem_rdata[7] , |
| \u_riscv_top.core0_dmem_rdata[6] , |
| \u_riscv_top.core0_dmem_rdata[5] , |
| \u_riscv_top.core0_dmem_rdata[4] , |
| \u_riscv_top.core0_dmem_rdata[3] , |
| \u_riscv_top.core0_dmem_rdata[2] , |
| \u_riscv_top.core0_dmem_rdata[1] , |
| \u_riscv_top.core0_dmem_rdata[0] }), |
| .dmem2core_resp_i({\u_riscv_top.core0_dmem_resp[1] , |
| \u_riscv_top.core0_dmem_resp[0] }), |
| .imem2core_rdata_i({\u_riscv_top.core0_imem_rdata[31] , |
| \u_riscv_top.core0_imem_rdata[30] , |
| \u_riscv_top.core0_imem_rdata[29] , |
| \u_riscv_top.core0_imem_rdata[28] , |
| \u_riscv_top.core0_imem_rdata[27] , |
| \u_riscv_top.core0_imem_rdata[26] , |
| \u_riscv_top.core0_imem_rdata[25] , |
| \u_riscv_top.core0_imem_rdata[24] , |
| \u_riscv_top.core0_imem_rdata[23] , |
| \u_riscv_top.core0_imem_rdata[22] , |
| \u_riscv_top.core0_imem_rdata[21] , |
| \u_riscv_top.core0_imem_rdata[20] , |
| \u_riscv_top.core0_imem_rdata[19] , |
| \u_riscv_top.core0_imem_rdata[18] , |
| \u_riscv_top.core0_imem_rdata[17] , |
| \u_riscv_top.core0_imem_rdata[16] , |
| \u_riscv_top.core0_imem_rdata[15] , |
| \u_riscv_top.core0_imem_rdata[14] , |
| \u_riscv_top.core0_imem_rdata[13] , |
| \u_riscv_top.core0_imem_rdata[12] , |
| \u_riscv_top.core0_imem_rdata[11] , |
| \u_riscv_top.core0_imem_rdata[10] , |
| \u_riscv_top.core0_imem_rdata[9] , |
| \u_riscv_top.core0_imem_rdata[8] , |
| \u_riscv_top.core0_imem_rdata[7] , |
| \u_riscv_top.core0_imem_rdata[6] , |
| \u_riscv_top.core0_imem_rdata[5] , |
| \u_riscv_top.core0_imem_rdata[4] , |
| \u_riscv_top.core0_imem_rdata[3] , |
| \u_riscv_top.core0_imem_rdata[2] , |
| \u_riscv_top.core0_imem_rdata[1] , |
| \u_riscv_top.core0_imem_rdata[0] }), |
| .imem2core_resp_i({\u_riscv_top.core0_imem_resp[1] , |
| \u_riscv_top.core0_imem_resp[0] })); |
| ycr_core_top \u_riscv_top.i_core_top_1 (.clk(\u_riscv_top.core_clk_core1_skew ), |
| .clk_o(\u_riscv_top.core_clk_out[1] ), |
| .core2dmem_cmd_o(\u_riscv_top.core1_dmem_cmd ), |
| .core2dmem_req_o(\u_riscv_top.core1_dmem_req ), |
| .core2imem_cmd_o(\u_riscv_top.core1_imem_cmd ), |
| .core2imem_req_o(\u_riscv_top.core1_imem_req ), |
| .core_clk_int(\u_riscv_top.core1_clk ), |
| .core_clk_skew(\u_riscv_top.core_clk_core1_skew ), |
| .core_irq_mtimer_i(\u_riscv_top.core1_timer_irq ), |
| .core_irq_soft_i(\u_riscv_top.core1_soft_irq ), |
| .cpu_rst_n(\cpu_core_rst_n[1] ), |
| .dmem2core_req_ack_i(\u_riscv_top.core1_dmem_req_ack ), |
| .imem2core_req_ack_i(\u_riscv_top.core1_imem_req_ack ), |
| .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ), |
| .rst_n(\u_riscv_top.pwrup_rst_n ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core1[3] , |
| \u_riscv_top.cfg_ccska_riscv_core1[2] , |
| \u_riscv_top.cfg_ccska_riscv_core1[1] , |
| \u_riscv_top.cfg_ccska_riscv_core1[0] }), |
| .core2dmem_addr_o({\u_riscv_top.core1_dmem_addr[31] , |
| \u_riscv_top.core1_dmem_addr[30] , |
| \u_riscv_top.core1_dmem_addr[29] , |
| \u_riscv_top.core1_dmem_addr[28] , |
| \u_riscv_top.core1_dmem_addr[27] , |
| \u_riscv_top.core1_dmem_addr[26] , |
| \u_riscv_top.core1_dmem_addr[25] , |
| \u_riscv_top.core1_dmem_addr[24] , |
| \u_riscv_top.core1_dmem_addr[23] , |
| \u_riscv_top.core1_dmem_addr[22] , |
| \u_riscv_top.core1_dmem_addr[21] , |
| \u_riscv_top.core1_dmem_addr[20] , |
| \u_riscv_top.core1_dmem_addr[19] , |
| \u_riscv_top.core1_dmem_addr[18] , |
| \u_riscv_top.core1_dmem_addr[17] , |
| \u_riscv_top.core1_dmem_addr[16] , |
| \u_riscv_top.core1_dmem_addr[15] , |
| \u_riscv_top.core1_dmem_addr[14] , |
| \u_riscv_top.core1_dmem_addr[13] , |
| \u_riscv_top.core1_dmem_addr[12] , |
| \u_riscv_top.core1_dmem_addr[11] , |
| \u_riscv_top.core1_dmem_addr[10] , |
| \u_riscv_top.core1_dmem_addr[9] , |
| \u_riscv_top.core1_dmem_addr[8] , |
| \u_riscv_top.core1_dmem_addr[7] , |
| \u_riscv_top.core1_dmem_addr[6] , |
| \u_riscv_top.core1_dmem_addr[5] , |
| \u_riscv_top.core1_dmem_addr[4] , |
| \u_riscv_top.core1_dmem_addr[3] , |
| \u_riscv_top.core1_dmem_addr[2] , |
| \u_riscv_top.core1_dmem_addr[1] , |
| \u_riscv_top.core1_dmem_addr[0] }), |
| .core2dmem_wdata_o({\u_riscv_top.core1_dmem_wdata[31] , |
| \u_riscv_top.core1_dmem_wdata[30] , |
| \u_riscv_top.core1_dmem_wdata[29] , |
| \u_riscv_top.core1_dmem_wdata[28] , |
| \u_riscv_top.core1_dmem_wdata[27] , |
| \u_riscv_top.core1_dmem_wdata[26] , |
| \u_riscv_top.core1_dmem_wdata[25] , |
| \u_riscv_top.core1_dmem_wdata[24] , |
| \u_riscv_top.core1_dmem_wdata[23] , |
| \u_riscv_top.core1_dmem_wdata[22] , |
| \u_riscv_top.core1_dmem_wdata[21] , |
| \u_riscv_top.core1_dmem_wdata[20] , |
| \u_riscv_top.core1_dmem_wdata[19] , |
| \u_riscv_top.core1_dmem_wdata[18] , |
| \u_riscv_top.core1_dmem_wdata[17] , |
| \u_riscv_top.core1_dmem_wdata[16] , |
| \u_riscv_top.core1_dmem_wdata[15] , |
| \u_riscv_top.core1_dmem_wdata[14] , |
| \u_riscv_top.core1_dmem_wdata[13] , |
| \u_riscv_top.core1_dmem_wdata[12] , |
| \u_riscv_top.core1_dmem_wdata[11] , |
| \u_riscv_top.core1_dmem_wdata[10] , |
| \u_riscv_top.core1_dmem_wdata[9] , |
| \u_riscv_top.core1_dmem_wdata[8] , |
| \u_riscv_top.core1_dmem_wdata[7] , |
| \u_riscv_top.core1_dmem_wdata[6] , |
| \u_riscv_top.core1_dmem_wdata[5] , |
| \u_riscv_top.core1_dmem_wdata[4] , |
| \u_riscv_top.core1_dmem_wdata[3] , |
| \u_riscv_top.core1_dmem_wdata[2] , |
| \u_riscv_top.core1_dmem_wdata[1] , |
| \u_riscv_top.core1_dmem_wdata[0] }), |
| .core2dmem_width_o({\u_riscv_top.core1_dmem_width[1] , |
| \u_riscv_top.core1_dmem_width[0] }), |
| .core2imem_addr_o({\u_riscv_top.core1_imem_addr[31] , |
| \u_riscv_top.core1_imem_addr[30] , |
| \u_riscv_top.core1_imem_addr[29] , |
| \u_riscv_top.core1_imem_addr[28] , |
| \u_riscv_top.core1_imem_addr[27] , |
| \u_riscv_top.core1_imem_addr[26] , |
| \u_riscv_top.core1_imem_addr[25] , |
| \u_riscv_top.core1_imem_addr[24] , |
| \u_riscv_top.core1_imem_addr[23] , |
| \u_riscv_top.core1_imem_addr[22] , |
| \u_riscv_top.core1_imem_addr[21] , |
| \u_riscv_top.core1_imem_addr[20] , |
| \u_riscv_top.core1_imem_addr[19] , |
| \u_riscv_top.core1_imem_addr[18] , |
| \u_riscv_top.core1_imem_addr[17] , |
| \u_riscv_top.core1_imem_addr[16] , |
| \u_riscv_top.core1_imem_addr[15] , |
| \u_riscv_top.core1_imem_addr[14] , |
| \u_riscv_top.core1_imem_addr[13] , |
| \u_riscv_top.core1_imem_addr[12] , |
| \u_riscv_top.core1_imem_addr[11] , |
| \u_riscv_top.core1_imem_addr[10] , |
| \u_riscv_top.core1_imem_addr[9] , |
| \u_riscv_top.core1_imem_addr[8] , |
| \u_riscv_top.core1_imem_addr[7] , |
| \u_riscv_top.core1_imem_addr[6] , |
| \u_riscv_top.core1_imem_addr[5] , |
| \u_riscv_top.core1_imem_addr[4] , |
| \u_riscv_top.core1_imem_addr[3] , |
| \u_riscv_top.core1_imem_addr[2] , |
| \u_riscv_top.core1_imem_addr[1] , |
| \u_riscv_top.core1_imem_addr[0] }), |
| .core2imem_bl_o({\u_riscv_top.core1_imem_bl[2] , |
| \u_riscv_top.core1_imem_bl[1] , |
| \u_riscv_top.core1_imem_bl[0] }), |
| .core_debug({\u_riscv_top.core1_debug[48] , |
| \u_riscv_top.core1_debug[47] , |
| \u_riscv_top.core1_debug[46] , |
| \u_riscv_top.core1_debug[45] , |
| \u_riscv_top.core1_debug[44] , |
| \u_riscv_top.core1_debug[43] , |
| \u_riscv_top.core1_debug[42] , |
| \u_riscv_top.core1_debug[41] , |
| \u_riscv_top.core1_debug[40] , |
| \u_riscv_top.core1_debug[39] , |
| \u_riscv_top.core1_debug[38] , |
| \u_riscv_top.core1_debug[37] , |
| \u_riscv_top.core1_debug[36] , |
| \u_riscv_top.core1_debug[35] , |
| \u_riscv_top.core1_debug[34] , |
| \u_riscv_top.core1_debug[33] , |
| \u_riscv_top.core1_debug[32] , |
| \u_riscv_top.core1_debug[31] , |
| \u_riscv_top.core1_debug[30] , |
| \u_riscv_top.core1_debug[29] , |
| \u_riscv_top.core1_debug[28] , |
| \u_riscv_top.core1_debug[27] , |
| \u_riscv_top.core1_debug[26] , |
| \u_riscv_top.core1_debug[25] , |
| \u_riscv_top.core1_debug[24] , |
| \u_riscv_top.core1_debug[23] , |
| \u_riscv_top.core1_debug[22] , |
| \u_riscv_top.core1_debug[21] , |
| \u_riscv_top.core1_debug[20] , |
| \u_riscv_top.core1_debug[19] , |
| \u_riscv_top.core1_debug[18] , |
| \u_riscv_top.core1_debug[17] , |
| \u_riscv_top.core1_debug[16] , |
| \u_riscv_top.core1_debug[15] , |
| \u_riscv_top.core1_debug[14] , |
| \u_riscv_top.core1_debug[13] , |
| \u_riscv_top.core1_debug[12] , |
| \u_riscv_top.core1_debug[11] , |
| \u_riscv_top.core1_debug[10] , |
| \u_riscv_top.core1_debug[9] , |
| \u_riscv_top.core1_debug[8] , |
| \u_riscv_top.core1_debug[7] , |
| \u_riscv_top.core1_debug[6] , |
| \u_riscv_top.core1_debug[5] , |
| \u_riscv_top.core1_debug[4] , |
| \u_riscv_top.core1_debug[3] , |
| \u_riscv_top.core1_debug[2] , |
| \u_riscv_top.core1_debug[1] , |
| \u_riscv_top.core1_debug[0] }), |
| .core_irq_lines_i({\u_riscv_top.core1_irq_lines[31] , |
| \u_riscv_top.core1_irq_lines[30] , |
| \u_riscv_top.core1_irq_lines[29] , |
| \u_riscv_top.core1_irq_lines[28] , |
| \u_riscv_top.core1_irq_lines[27] , |
| \u_riscv_top.core1_irq_lines[26] , |
| \u_riscv_top.core1_irq_lines[25] , |
| \u_riscv_top.core1_irq_lines[24] , |
| \u_riscv_top.core1_irq_lines[23] , |
| \u_riscv_top.core1_irq_lines[22] , |
| \u_riscv_top.core1_irq_lines[21] , |
| \u_riscv_top.core1_irq_lines[20] , |
| \u_riscv_top.core1_irq_lines[19] , |
| \u_riscv_top.core1_irq_lines[18] , |
| \u_riscv_top.core1_irq_lines[17] , |
| \u_riscv_top.core1_irq_lines[16] , |
| \u_riscv_top.core1_irq_lines[15] , |
| \u_riscv_top.core1_irq_lines[14] , |
| \u_riscv_top.core1_irq_lines[13] , |
| \u_riscv_top.core1_irq_lines[12] , |
| \u_riscv_top.core1_irq_lines[11] , |
| \u_riscv_top.core1_irq_lines[10] , |
| \u_riscv_top.core1_irq_lines[9] , |
| \u_riscv_top.core1_irq_lines[8] , |
| \u_riscv_top.core1_irq_lines[7] , |
| \u_riscv_top.core1_irq_lines[6] , |
| \u_riscv_top.core1_irq_lines[5] , |
| \u_riscv_top.core1_irq_lines[4] , |
| \u_riscv_top.core1_irq_lines[3] , |
| \u_riscv_top.core1_irq_lines[2] , |
| \u_riscv_top.core1_irq_lines[1] , |
| \u_riscv_top.core1_irq_lines[0] }), |
| .core_mtimer_val_i({\u_riscv_top.core1_timer_val[63] , |
| \u_riscv_top.core1_timer_val[62] , |
| \u_riscv_top.core1_timer_val[61] , |
| \u_riscv_top.core1_timer_val[60] , |
| \u_riscv_top.core1_timer_val[59] , |
| \u_riscv_top.core1_timer_val[58] , |
| \u_riscv_top.core1_timer_val[57] , |
| \u_riscv_top.core1_timer_val[56] , |
| \u_riscv_top.core1_timer_val[55] , |
| \u_riscv_top.core1_timer_val[54] , |
| \u_riscv_top.core1_timer_val[53] , |
| \u_riscv_top.core1_timer_val[52] , |
| \u_riscv_top.core1_timer_val[51] , |
| \u_riscv_top.core1_timer_val[50] , |
| \u_riscv_top.core1_timer_val[49] , |
| \u_riscv_top.core1_timer_val[48] , |
| \u_riscv_top.core1_timer_val[47] , |
| \u_riscv_top.core1_timer_val[46] , |
| \u_riscv_top.core1_timer_val[45] , |
| \u_riscv_top.core1_timer_val[44] , |
| \u_riscv_top.core1_timer_val[43] , |
| \u_riscv_top.core1_timer_val[42] , |
| \u_riscv_top.core1_timer_val[41] , |
| \u_riscv_top.core1_timer_val[40] , |
| \u_riscv_top.core1_timer_val[39] , |
| \u_riscv_top.core1_timer_val[38] , |
| \u_riscv_top.core1_timer_val[37] , |
| \u_riscv_top.core1_timer_val[36] , |
| \u_riscv_top.core1_timer_val[35] , |
| \u_riscv_top.core1_timer_val[34] , |
| \u_riscv_top.core1_timer_val[33] , |
| \u_riscv_top.core1_timer_val[32] , |
| \u_riscv_top.core1_timer_val[31] , |
| \u_riscv_top.core1_timer_val[30] , |
| \u_riscv_top.core1_timer_val[29] , |
| \u_riscv_top.core1_timer_val[28] , |
| \u_riscv_top.core1_timer_val[27] , |
| \u_riscv_top.core1_timer_val[26] , |
| \u_riscv_top.core1_timer_val[25] , |
| \u_riscv_top.core1_timer_val[24] , |
| \u_riscv_top.core1_timer_val[23] , |
| \u_riscv_top.core1_timer_val[22] , |
| \u_riscv_top.core1_timer_val[21] , |
| \u_riscv_top.core1_timer_val[20] , |
| \u_riscv_top.core1_timer_val[19] , |
| \u_riscv_top.core1_timer_val[18] , |
| \u_riscv_top.core1_timer_val[17] , |
| \u_riscv_top.core1_timer_val[16] , |
| \u_riscv_top.core1_timer_val[15] , |
| \u_riscv_top.core1_timer_val[14] , |
| \u_riscv_top.core1_timer_val[13] , |
| \u_riscv_top.core1_timer_val[12] , |
| \u_riscv_top.core1_timer_val[11] , |
| \u_riscv_top.core1_timer_val[10] , |
| \u_riscv_top.core1_timer_val[9] , |
| \u_riscv_top.core1_timer_val[8] , |
| \u_riscv_top.core1_timer_val[7] , |
| \u_riscv_top.core1_timer_val[6] , |
| \u_riscv_top.core1_timer_val[5] , |
| \u_riscv_top.core1_timer_val[4] , |
| \u_riscv_top.core1_timer_val[3] , |
| \u_riscv_top.core1_timer_val[2] , |
| \u_riscv_top.core1_timer_val[1] , |
| \u_riscv_top.core1_timer_val[0] }), |
| .core_uid({\u_riscv_top.core1_uid[1] , |
| \u_riscv_top.core1_uid[0] }), |
| .dmem2core_rdata_i({\u_riscv_top.core1_dmem_rdata[31] , |
| \u_riscv_top.core1_dmem_rdata[30] , |
| \u_riscv_top.core1_dmem_rdata[29] , |
| \u_riscv_top.core1_dmem_rdata[28] , |
| \u_riscv_top.core1_dmem_rdata[27] , |
| \u_riscv_top.core1_dmem_rdata[26] , |
| \u_riscv_top.core1_dmem_rdata[25] , |
| \u_riscv_top.core1_dmem_rdata[24] , |
| \u_riscv_top.core1_dmem_rdata[23] , |
| \u_riscv_top.core1_dmem_rdata[22] , |
| \u_riscv_top.core1_dmem_rdata[21] , |
| \u_riscv_top.core1_dmem_rdata[20] , |
| \u_riscv_top.core1_dmem_rdata[19] , |
| \u_riscv_top.core1_dmem_rdata[18] , |
| \u_riscv_top.core1_dmem_rdata[17] , |
| \u_riscv_top.core1_dmem_rdata[16] , |
| \u_riscv_top.core1_dmem_rdata[15] , |
| \u_riscv_top.core1_dmem_rdata[14] , |
| \u_riscv_top.core1_dmem_rdata[13] , |
| \u_riscv_top.core1_dmem_rdata[12] , |
| \u_riscv_top.core1_dmem_rdata[11] , |
| \u_riscv_top.core1_dmem_rdata[10] , |
| \u_riscv_top.core1_dmem_rdata[9] , |
| \u_riscv_top.core1_dmem_rdata[8] , |
| \u_riscv_top.core1_dmem_rdata[7] , |
| \u_riscv_top.core1_dmem_rdata[6] , |
| \u_riscv_top.core1_dmem_rdata[5] , |
| \u_riscv_top.core1_dmem_rdata[4] , |
| \u_riscv_top.core1_dmem_rdata[3] , |
| \u_riscv_top.core1_dmem_rdata[2] , |
| \u_riscv_top.core1_dmem_rdata[1] , |
| \u_riscv_top.core1_dmem_rdata[0] }), |
| .dmem2core_resp_i({\u_riscv_top.core1_dmem_resp[1] , |
| \u_riscv_top.core1_dmem_resp[0] }), |
| .imem2core_rdata_i({\u_riscv_top.core1_imem_rdata[31] , |
| \u_riscv_top.core1_imem_rdata[30] , |
| \u_riscv_top.core1_imem_rdata[29] , |
| \u_riscv_top.core1_imem_rdata[28] , |
| \u_riscv_top.core1_imem_rdata[27] , |
| \u_riscv_top.core1_imem_rdata[26] , |
| \u_riscv_top.core1_imem_rdata[25] , |
| \u_riscv_top.core1_imem_rdata[24] , |
| \u_riscv_top.core1_imem_rdata[23] , |
| \u_riscv_top.core1_imem_rdata[22] , |
| \u_riscv_top.core1_imem_rdata[21] , |
| \u_riscv_top.core1_imem_rdata[20] , |
| \u_riscv_top.core1_imem_rdata[19] , |
| \u_riscv_top.core1_imem_rdata[18] , |
| \u_riscv_top.core1_imem_rdata[17] , |
| \u_riscv_top.core1_imem_rdata[16] , |
| \u_riscv_top.core1_imem_rdata[15] , |
| \u_riscv_top.core1_imem_rdata[14] , |
| \u_riscv_top.core1_imem_rdata[13] , |
| \u_riscv_top.core1_imem_rdata[12] , |
| \u_riscv_top.core1_imem_rdata[11] , |
| \u_riscv_top.core1_imem_rdata[10] , |
| \u_riscv_top.core1_imem_rdata[9] , |
| \u_riscv_top.core1_imem_rdata[8] , |
| \u_riscv_top.core1_imem_rdata[7] , |
| \u_riscv_top.core1_imem_rdata[6] , |
| \u_riscv_top.core1_imem_rdata[5] , |
| \u_riscv_top.core1_imem_rdata[4] , |
| \u_riscv_top.core1_imem_rdata[3] , |
| \u_riscv_top.core1_imem_rdata[2] , |
| \u_riscv_top.core1_imem_rdata[1] , |
| \u_riscv_top.core1_imem_rdata[0] }), |
| .imem2core_resp_i({\u_riscv_top.core1_imem_resp[1] , |
| \u_riscv_top.core1_imem_resp[0] })); |
| ycr2_iconnect \u_riscv_top.u_connect (.VGND(vssd1), |
| .VPWR(vccd1), |
| .aes_dmem_cmd(\u_riscv_top.aes_dmem_cmd ), |
| .aes_dmem_req(\u_riscv_top.aes_dmem_req ), |
| .aes_dmem_req_ack(\u_riscv_top.aes_dmem_req_ack ), |
| .cfg_bypass_dcache(\cfg_riscv_ctrl[11] ), |
| .cfg_bypass_icache(\cfg_riscv_ctrl[10] ), |
| .cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ), |
| .core0_clk(\u_riscv_top.core0_clk ), |
| .core0_dmem_cmd(\u_riscv_top.core0_dmem_cmd ), |
| .core0_dmem_req(\u_riscv_top.core0_dmem_req ), |
| .core0_dmem_req_ack(\u_riscv_top.core0_dmem_req_ack ), |
| .core0_imem_cmd(\u_riscv_top.core0_imem_cmd ), |
| .core0_imem_req(\u_riscv_top.core0_imem_req ), |
| .core0_imem_req_ack(\u_riscv_top.core0_imem_req_ack ), |
| .core0_irq_soft(\u_riscv_top.core0_soft_irq ), |
| .core0_timer_irq(\u_riscv_top.core0_timer_irq ), |
| .core1_clk(\u_riscv_top.core1_clk ), |
| .core1_dmem_cmd(\u_riscv_top.core1_dmem_cmd ), |
| .core1_dmem_req(\u_riscv_top.core1_dmem_req ), |
| .core1_dmem_req_ack(\u_riscv_top.core1_dmem_req_ack ), |
| .core1_imem_cmd(\u_riscv_top.core1_imem_cmd ), |
| .core1_imem_req(\u_riscv_top.core1_imem_req ), |
| .core1_imem_req_ack(\u_riscv_top.core1_imem_req_ack ), |
| .core1_irq_soft(\u_riscv_top.core1_soft_irq ), |
| .core1_timer_irq(\u_riscv_top.core1_timer_irq ), |
| .core_clk(\u_riscv_top.core_clk_icon_skew ), |
| .core_clk_int(\u_riscv_top.core_clk_int[1] ), |
| .core_clk_skew(\u_riscv_top.core_clk_icon_skew ), |
| .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ), |
| .core_dcache_req(\u_riscv_top.core_dcache_req ), |
| .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ), |
| .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ), |
| .core_dmem_req(\u_riscv_top.core_dmem_req ), |
| .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ), |
| .core_icache_cmd(\u_riscv_top.core_icache_cmd ), |
| .core_icache_req(\u_riscv_top.core_icache_req ), |
| .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ), |
| .core_irq_soft_i(\u_riscv_top.soft_irq ), |
| .cpu_clk_aes(\u_riscv_top.cpu_clk_aes ), |
| .cpu_clk_fpu(\u_riscv_top.cpu_clk_fpu ), |
| .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ), |
| .fpu_dmem_cmd(\u_riscv_top.fpu_dmem_cmd ), |
| .fpu_dmem_req(\u_riscv_top.fpu_dmem_req ), |
| .fpu_dmem_req_ack(\u_riscv_top.fpu_dmem_req_ack ), |
| .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ), |
| .rtc_clk(\u_riscv_top.rtc_clk ), |
| .sram0_clk0(\u_riscv_top.sram0_clk0 ), |
| .sram0_clk1(\u_riscv_top.sram0_clk1 ), |
| .sram0_csb0(\u_riscv_top.sram0_csb0 ), |
| .sram0_csb1(\u_riscv_top.sram0_csb1 ), |
| .sram0_web0(\u_riscv_top.sram0_web0 ), |
| .aes_dmem_addr({\u_riscv_top.aes_dmem_addr[6] , |
| \u_riscv_top.aes_dmem_addr[5] , |
| \u_riscv_top.aes_dmem_addr[4] , |
| \u_riscv_top.aes_dmem_addr[3] , |
| \u_riscv_top.aes_dmem_addr[2] , |
| \u_riscv_top.aes_dmem_addr[1] , |
| \u_riscv_top.aes_dmem_addr[0] }), |
| .aes_dmem_rdata({\u_riscv_top.aes_dmem_rdata[31] , |
| \u_riscv_top.aes_dmem_rdata[30] , |
| \u_riscv_top.aes_dmem_rdata[29] , |
| \u_riscv_top.aes_dmem_rdata[28] , |
| \u_riscv_top.aes_dmem_rdata[27] , |
| \u_riscv_top.aes_dmem_rdata[26] , |
| \u_riscv_top.aes_dmem_rdata[25] , |
| \u_riscv_top.aes_dmem_rdata[24] , |
| \u_riscv_top.aes_dmem_rdata[23] , |
| \u_riscv_top.aes_dmem_rdata[22] , |
| \u_riscv_top.aes_dmem_rdata[21] , |
| \u_riscv_top.aes_dmem_rdata[20] , |
| \u_riscv_top.aes_dmem_rdata[19] , |
| \u_riscv_top.aes_dmem_rdata[18] , |
| \u_riscv_top.aes_dmem_rdata[17] , |
| \u_riscv_top.aes_dmem_rdata[16] , |
| \u_riscv_top.aes_dmem_rdata[15] , |
| \u_riscv_top.aes_dmem_rdata[14] , |
| \u_riscv_top.aes_dmem_rdata[13] , |
| \u_riscv_top.aes_dmem_rdata[12] , |
| \u_riscv_top.aes_dmem_rdata[11] , |
| \u_riscv_top.aes_dmem_rdata[10] , |
| \u_riscv_top.aes_dmem_rdata[9] , |
| \u_riscv_top.aes_dmem_rdata[8] , |
| \u_riscv_top.aes_dmem_rdata[7] , |
| \u_riscv_top.aes_dmem_rdata[6] , |
| \u_riscv_top.aes_dmem_rdata[5] , |
| \u_riscv_top.aes_dmem_rdata[4] , |
| \u_riscv_top.aes_dmem_rdata[3] , |
| \u_riscv_top.aes_dmem_rdata[2] , |
| \u_riscv_top.aes_dmem_rdata[1] , |
| \u_riscv_top.aes_dmem_rdata[0] }), |
| .aes_dmem_resp({\u_riscv_top.aes_dmem_resp[1] , |
| \u_riscv_top.aes_dmem_resp[0] }), |
| .aes_dmem_wdata({\u_riscv_top.aes_dmem_wdata[31] , |
| \u_riscv_top.aes_dmem_wdata[30] , |
| \u_riscv_top.aes_dmem_wdata[29] , |
| \u_riscv_top.aes_dmem_wdata[28] , |
| \u_riscv_top.aes_dmem_wdata[27] , |
| \u_riscv_top.aes_dmem_wdata[26] , |
| \u_riscv_top.aes_dmem_wdata[25] , |
| \u_riscv_top.aes_dmem_wdata[24] , |
| \u_riscv_top.aes_dmem_wdata[23] , |
| \u_riscv_top.aes_dmem_wdata[22] , |
| \u_riscv_top.aes_dmem_wdata[21] , |
| \u_riscv_top.aes_dmem_wdata[20] , |
| \u_riscv_top.aes_dmem_wdata[19] , |
| \u_riscv_top.aes_dmem_wdata[18] , |
| \u_riscv_top.aes_dmem_wdata[17] , |
| \u_riscv_top.aes_dmem_wdata[16] , |
| \u_riscv_top.aes_dmem_wdata[15] , |
| \u_riscv_top.aes_dmem_wdata[14] , |
| \u_riscv_top.aes_dmem_wdata[13] , |
| \u_riscv_top.aes_dmem_wdata[12] , |
| \u_riscv_top.aes_dmem_wdata[11] , |
| \u_riscv_top.aes_dmem_wdata[10] , |
| \u_riscv_top.aes_dmem_wdata[9] , |
| \u_riscv_top.aes_dmem_wdata[8] , |
| \u_riscv_top.aes_dmem_wdata[7] , |
| \u_riscv_top.aes_dmem_wdata[6] , |
| \u_riscv_top.aes_dmem_wdata[5] , |
| \u_riscv_top.aes_dmem_wdata[4] , |
| \u_riscv_top.aes_dmem_wdata[3] , |
| \u_riscv_top.aes_dmem_wdata[2] , |
| \u_riscv_top.aes_dmem_wdata[1] , |
| \u_riscv_top.aes_dmem_wdata[0] }), |
| .aes_dmem_width({\u_riscv_top.aes_dmem_width[1] , |
| \u_riscv_top.aes_dmem_width[0] }), |
| .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_icon[3] , |
| \u_riscv_top.cfg_ccska_riscv_icon[2] , |
| \u_riscv_top.cfg_ccska_riscv_icon[1] , |
| \u_riscv_top.cfg_ccska_riscv_icon[0] }), |
| .cfg_sram_lphase({\cfg_riscv_ctrl[3] , |
| \cfg_riscv_ctrl[2] }), |
| .core0_debug({\u_riscv_top.core0_debug[48] , |
| \u_riscv_top.core0_debug[47] , |
| \u_riscv_top.core0_debug[46] , |
| \u_riscv_top.core0_debug[45] , |
| \u_riscv_top.core0_debug[44] , |
| \u_riscv_top.core0_debug[43] , |
| \u_riscv_top.core0_debug[42] , |
| \u_riscv_top.core0_debug[41] , |
| \u_riscv_top.core0_debug[40] , |
| \u_riscv_top.core0_debug[39] , |
| \u_riscv_top.core0_debug[38] , |
| \u_riscv_top.core0_debug[37] , |
| \u_riscv_top.core0_debug[36] , |
| \u_riscv_top.core0_debug[35] , |
| \u_riscv_top.core0_debug[34] , |
| \u_riscv_top.core0_debug[33] , |
| \u_riscv_top.core0_debug[32] , |
| \u_riscv_top.core0_debug[31] , |
| \u_riscv_top.core0_debug[30] , |
| \u_riscv_top.core0_debug[29] , |
| \u_riscv_top.core0_debug[28] , |
| \u_riscv_top.core0_debug[27] , |
| \u_riscv_top.core0_debug[26] , |
| \u_riscv_top.core0_debug[25] , |
| \u_riscv_top.core0_debug[24] , |
| \u_riscv_top.core0_debug[23] , |
| \u_riscv_top.core0_debug[22] , |
| \u_riscv_top.core0_debug[21] , |
| \u_riscv_top.core0_debug[20] , |
| \u_riscv_top.core0_debug[19] , |
| \u_riscv_top.core0_debug[18] , |
| \u_riscv_top.core0_debug[17] , |
| \u_riscv_top.core0_debug[16] , |
| \u_riscv_top.core0_debug[15] , |
| \u_riscv_top.core0_debug[14] , |
| \u_riscv_top.core0_debug[13] , |
| \u_riscv_top.core0_debug[12] , |
| \u_riscv_top.core0_debug[11] , |
| \u_riscv_top.core0_debug[10] , |
| \u_riscv_top.core0_debug[9] , |
| \u_riscv_top.core0_debug[8] , |
| \u_riscv_top.core0_debug[7] , |
| \u_riscv_top.core0_debug[6] , |
| \u_riscv_top.core0_debug[5] , |
| \u_riscv_top.core0_debug[4] , |
| \u_riscv_top.core0_debug[3] , |
| \u_riscv_top.core0_debug[2] , |
| \u_riscv_top.core0_debug[1] , |
| \u_riscv_top.core0_debug[0] }), |
| .core0_dmem_addr({\u_riscv_top.core0_dmem_addr[31] , |
| \u_riscv_top.core0_dmem_addr[30] , |
| \u_riscv_top.core0_dmem_addr[29] , |
| \u_riscv_top.core0_dmem_addr[28] , |
| \u_riscv_top.core0_dmem_addr[27] , |
| \u_riscv_top.core0_dmem_addr[26] , |
| \u_riscv_top.core0_dmem_addr[25] , |
| \u_riscv_top.core0_dmem_addr[24] , |
| \u_riscv_top.core0_dmem_addr[23] , |
| \u_riscv_top.core0_dmem_addr[22] , |
| \u_riscv_top.core0_dmem_addr[21] , |
| \u_riscv_top.core0_dmem_addr[20] , |
| \u_riscv_top.core0_dmem_addr[19] , |
| \u_riscv_top.core0_dmem_addr[18] , |
| \u_riscv_top.core0_dmem_addr[17] , |
| \u_riscv_top.core0_dmem_addr[16] , |
| \u_riscv_top.core0_dmem_addr[15] , |
| \u_riscv_top.core0_dmem_addr[14] , |
| \u_riscv_top.core0_dmem_addr[13] , |
| \u_riscv_top.core0_dmem_addr[12] , |
| \u_riscv_top.core0_dmem_addr[11] , |
| \u_riscv_top.core0_dmem_addr[10] , |
| \u_riscv_top.core0_dmem_addr[9] , |
| \u_riscv_top.core0_dmem_addr[8] , |
| \u_riscv_top.core0_dmem_addr[7] , |
| \u_riscv_top.core0_dmem_addr[6] , |
| \u_riscv_top.core0_dmem_addr[5] , |
| \u_riscv_top.core0_dmem_addr[4] , |
| \u_riscv_top.core0_dmem_addr[3] , |
| \u_riscv_top.core0_dmem_addr[2] , |
| \u_riscv_top.core0_dmem_addr[1] , |
| \u_riscv_top.core0_dmem_addr[0] }), |
| .core0_dmem_rdata({\u_riscv_top.core0_dmem_rdata[31] , |
| \u_riscv_top.core0_dmem_rdata[30] , |
| \u_riscv_top.core0_dmem_rdata[29] , |
| \u_riscv_top.core0_dmem_rdata[28] , |
| \u_riscv_top.core0_dmem_rdata[27] , |
| \u_riscv_top.core0_dmem_rdata[26] , |
| \u_riscv_top.core0_dmem_rdata[25] , |
| \u_riscv_top.core0_dmem_rdata[24] , |
| \u_riscv_top.core0_dmem_rdata[23] , |
| \u_riscv_top.core0_dmem_rdata[22] , |
| \u_riscv_top.core0_dmem_rdata[21] , |
| \u_riscv_top.core0_dmem_rdata[20] , |
| \u_riscv_top.core0_dmem_rdata[19] , |
| \u_riscv_top.core0_dmem_rdata[18] , |
| \u_riscv_top.core0_dmem_rdata[17] , |
| \u_riscv_top.core0_dmem_rdata[16] , |
| \u_riscv_top.core0_dmem_rdata[15] , |
| \u_riscv_top.core0_dmem_rdata[14] , |
| \u_riscv_top.core0_dmem_rdata[13] , |
| \u_riscv_top.core0_dmem_rdata[12] , |
| \u_riscv_top.core0_dmem_rdata[11] , |
| \u_riscv_top.core0_dmem_rdata[10] , |
| \u_riscv_top.core0_dmem_rdata[9] , |
| \u_riscv_top.core0_dmem_rdata[8] , |
| \u_riscv_top.core0_dmem_rdata[7] , |
| \u_riscv_top.core0_dmem_rdata[6] , |
| \u_riscv_top.core0_dmem_rdata[5] , |
| \u_riscv_top.core0_dmem_rdata[4] , |
| \u_riscv_top.core0_dmem_rdata[3] , |
| \u_riscv_top.core0_dmem_rdata[2] , |
| \u_riscv_top.core0_dmem_rdata[1] , |
| \u_riscv_top.core0_dmem_rdata[0] }), |
| .core0_dmem_resp({\u_riscv_top.core0_dmem_resp[1] , |
| \u_riscv_top.core0_dmem_resp[0] }), |
| .core0_dmem_wdata({\u_riscv_top.core0_dmem_wdata[31] , |
| \u_riscv_top.core0_dmem_wdata[30] , |
| \u_riscv_top.core0_dmem_wdata[29] , |
| \u_riscv_top.core0_dmem_wdata[28] , |
| \u_riscv_top.core0_dmem_wdata[27] , |
| \u_riscv_top.core0_dmem_wdata[26] , |
| \u_riscv_top.core0_dmem_wdata[25] , |
| \u_riscv_top.core0_dmem_wdata[24] , |
| \u_riscv_top.core0_dmem_wdata[23] , |
| \u_riscv_top.core0_dmem_wdata[22] , |
| \u_riscv_top.core0_dmem_wdata[21] , |
| \u_riscv_top.core0_dmem_wdata[20] , |
| \u_riscv_top.core0_dmem_wdata[19] , |
| \u_riscv_top.core0_dmem_wdata[18] , |
| \u_riscv_top.core0_dmem_wdata[17] , |
| \u_riscv_top.core0_dmem_wdata[16] , |
| \u_riscv_top.core0_dmem_wdata[15] , |
| \u_riscv_top.core0_dmem_wdata[14] , |
| \u_riscv_top.core0_dmem_wdata[13] , |
| \u_riscv_top.core0_dmem_wdata[12] , |
| \u_riscv_top.core0_dmem_wdata[11] , |
| \u_riscv_top.core0_dmem_wdata[10] , |
| \u_riscv_top.core0_dmem_wdata[9] , |
| \u_riscv_top.core0_dmem_wdata[8] , |
| \u_riscv_top.core0_dmem_wdata[7] , |
| \u_riscv_top.core0_dmem_wdata[6] , |
| \u_riscv_top.core0_dmem_wdata[5] , |
| \u_riscv_top.core0_dmem_wdata[4] , |
| \u_riscv_top.core0_dmem_wdata[3] , |
| \u_riscv_top.core0_dmem_wdata[2] , |
| \u_riscv_top.core0_dmem_wdata[1] , |
| \u_riscv_top.core0_dmem_wdata[0] }), |
| .core0_dmem_width({\u_riscv_top.core0_dmem_width[1] , |
| \u_riscv_top.core0_dmem_width[0] }), |
| .core0_imem_addr({\u_riscv_top.core0_imem_addr[31] , |
| \u_riscv_top.core0_imem_addr[30] , |
| \u_riscv_top.core0_imem_addr[29] , |
| \u_riscv_top.core0_imem_addr[28] , |
| \u_riscv_top.core0_imem_addr[27] , |
| \u_riscv_top.core0_imem_addr[26] , |
| \u_riscv_top.core0_imem_addr[25] , |
| \u_riscv_top.core0_imem_addr[24] , |
| \u_riscv_top.core0_imem_addr[23] , |
| \u_riscv_top.core0_imem_addr[22] , |
| \u_riscv_top.core0_imem_addr[21] , |
| \u_riscv_top.core0_imem_addr[20] , |
| \u_riscv_top.core0_imem_addr[19] , |
| \u_riscv_top.core0_imem_addr[18] , |
| \u_riscv_top.core0_imem_addr[17] , |
| \u_riscv_top.core0_imem_addr[16] , |
| \u_riscv_top.core0_imem_addr[15] , |
| \u_riscv_top.core0_imem_addr[14] , |
| \u_riscv_top.core0_imem_addr[13] , |
| \u_riscv_top.core0_imem_addr[12] , |
| \u_riscv_top.core0_imem_addr[11] , |
| \u_riscv_top.core0_imem_addr[10] , |
| \u_riscv_top.core0_imem_addr[9] , |
| \u_riscv_top.core0_imem_addr[8] , |
| \u_riscv_top.core0_imem_addr[7] , |
| \u_riscv_top.core0_imem_addr[6] , |
| \u_riscv_top.core0_imem_addr[5] , |
| \u_riscv_top.core0_imem_addr[4] , |
| \u_riscv_top.core0_imem_addr[3] , |
| \u_riscv_top.core0_imem_addr[2] , |
| \u_riscv_top.core0_imem_addr[1] , |
| \u_riscv_top.core0_imem_addr[0] }), |
| .core0_imem_bl({\u_riscv_top.core0_imem_bl[2] , |
| \u_riscv_top.core0_imem_bl[1] , |
| \u_riscv_top.core0_imem_bl[0] }), |
| .core0_imem_rdata({\u_riscv_top.core0_imem_rdata[31] , |
| \u_riscv_top.core0_imem_rdata[30] , |
| \u_riscv_top.core0_imem_rdata[29] , |
| \u_riscv_top.core0_imem_rdata[28] , |
| \u_riscv_top.core0_imem_rdata[27] , |
| \u_riscv_top.core0_imem_rdata[26] , |
| \u_riscv_top.core0_imem_rdata[25] , |
| \u_riscv_top.core0_imem_rdata[24] , |
| \u_riscv_top.core0_imem_rdata[23] , |
| \u_riscv_top.core0_imem_rdata[22] , |
| \u_riscv_top.core0_imem_rdata[21] , |
| \u_riscv_top.core0_imem_rdata[20] , |
| \u_riscv_top.core0_imem_rdata[19] , |
| \u_riscv_top.core0_imem_rdata[18] , |
| \u_riscv_top.core0_imem_rdata[17] , |
| \u_riscv_top.core0_imem_rdata[16] , |
| \u_riscv_top.core0_imem_rdata[15] , |
| \u_riscv_top.core0_imem_rdata[14] , |
| \u_riscv_top.core0_imem_rdata[13] , |
| \u_riscv_top.core0_imem_rdata[12] , |
| \u_riscv_top.core0_imem_rdata[11] , |
| \u_riscv_top.core0_imem_rdata[10] , |
| \u_riscv_top.core0_imem_rdata[9] , |
| \u_riscv_top.core0_imem_rdata[8] , |
| \u_riscv_top.core0_imem_rdata[7] , |
| \u_riscv_top.core0_imem_rdata[6] , |
| \u_riscv_top.core0_imem_rdata[5] , |
| \u_riscv_top.core0_imem_rdata[4] , |
| \u_riscv_top.core0_imem_rdata[3] , |
| \u_riscv_top.core0_imem_rdata[2] , |
| \u_riscv_top.core0_imem_rdata[1] , |
| \u_riscv_top.core0_imem_rdata[0] }), |
| .core0_imem_resp({\u_riscv_top.core0_imem_resp[1] , |
| \u_riscv_top.core0_imem_resp[0] }), |
| .core0_irq_lines({\u_riscv_top.core0_irq_lines[31] , |
| \u_riscv_top.core0_irq_lines[30] , |
| \u_riscv_top.core0_irq_lines[29] , |
| \u_riscv_top.core0_irq_lines[28] , |
| \u_riscv_top.core0_irq_lines[27] , |
| \u_riscv_top.core0_irq_lines[26] , |
| \u_riscv_top.core0_irq_lines[25] , |
| \u_riscv_top.core0_irq_lines[24] , |
| \u_riscv_top.core0_irq_lines[23] , |
| \u_riscv_top.core0_irq_lines[22] , |
| \u_riscv_top.core0_irq_lines[21] , |
| \u_riscv_top.core0_irq_lines[20] , |
| \u_riscv_top.core0_irq_lines[19] , |
| \u_riscv_top.core0_irq_lines[18] , |
| \u_riscv_top.core0_irq_lines[17] , |
| \u_riscv_top.core0_irq_lines[16] , |
| \u_riscv_top.core0_irq_lines[15] , |
| \u_riscv_top.core0_irq_lines[14] , |
| \u_riscv_top.core0_irq_lines[13] , |
| \u_riscv_top.core0_irq_lines[12] , |
| \u_riscv_top.core0_irq_lines[11] , |
| \u_riscv_top.core0_irq_lines[10] , |
| \u_riscv_top.core0_irq_lines[9] , |
| \u_riscv_top.core0_irq_lines[8] , |
| \u_riscv_top.core0_irq_lines[7] , |
| \u_riscv_top.core0_irq_lines[6] , |
| \u_riscv_top.core0_irq_lines[5] , |
| \u_riscv_top.core0_irq_lines[4] , |
| \u_riscv_top.core0_irq_lines[3] , |
| \u_riscv_top.core0_irq_lines[2] , |
| \u_riscv_top.core0_irq_lines[1] , |
| \u_riscv_top.core0_irq_lines[0] }), |
| .core0_timer_val({\u_riscv_top.core0_timer_val[63] , |
| \u_riscv_top.core0_timer_val[62] , |
| \u_riscv_top.core0_timer_val[61] , |
| \u_riscv_top.core0_timer_val[60] , |
| \u_riscv_top.core0_timer_val[59] , |
| \u_riscv_top.core0_timer_val[58] , |
| \u_riscv_top.core0_timer_val[57] , |
| \u_riscv_top.core0_timer_val[56] , |
| \u_riscv_top.core0_timer_val[55] , |
| \u_riscv_top.core0_timer_val[54] , |
| \u_riscv_top.core0_timer_val[53] , |
| \u_riscv_top.core0_timer_val[52] , |
| \u_riscv_top.core0_timer_val[51] , |
| \u_riscv_top.core0_timer_val[50] , |
| \u_riscv_top.core0_timer_val[49] , |
| \u_riscv_top.core0_timer_val[48] , |
| \u_riscv_top.core0_timer_val[47] , |
| \u_riscv_top.core0_timer_val[46] , |
| \u_riscv_top.core0_timer_val[45] , |
| \u_riscv_top.core0_timer_val[44] , |
| \u_riscv_top.core0_timer_val[43] , |
| \u_riscv_top.core0_timer_val[42] , |
| \u_riscv_top.core0_timer_val[41] , |
| \u_riscv_top.core0_timer_val[40] , |
| \u_riscv_top.core0_timer_val[39] , |
| \u_riscv_top.core0_timer_val[38] , |
| \u_riscv_top.core0_timer_val[37] , |
| \u_riscv_top.core0_timer_val[36] , |
| \u_riscv_top.core0_timer_val[35] , |
| \u_riscv_top.core0_timer_val[34] , |
| \u_riscv_top.core0_timer_val[33] , |
| \u_riscv_top.core0_timer_val[32] , |
| \u_riscv_top.core0_timer_val[31] , |
| \u_riscv_top.core0_timer_val[30] , |
| \u_riscv_top.core0_timer_val[29] , |
| \u_riscv_top.core0_timer_val[28] , |
| \u_riscv_top.core0_timer_val[27] , |
| \u_riscv_top.core0_timer_val[26] , |
| \u_riscv_top.core0_timer_val[25] , |
| \u_riscv_top.core0_timer_val[24] , |
| \u_riscv_top.core0_timer_val[23] , |
| \u_riscv_top.core0_timer_val[22] , |
| \u_riscv_top.core0_timer_val[21] , |
| \u_riscv_top.core0_timer_val[20] , |
| \u_riscv_top.core0_timer_val[19] , |
| \u_riscv_top.core0_timer_val[18] , |
| \u_riscv_top.core0_timer_val[17] , |
| \u_riscv_top.core0_timer_val[16] , |
| \u_riscv_top.core0_timer_val[15] , |
| \u_riscv_top.core0_timer_val[14] , |
| \u_riscv_top.core0_timer_val[13] , |
| \u_riscv_top.core0_timer_val[12] , |
| \u_riscv_top.core0_timer_val[11] , |
| \u_riscv_top.core0_timer_val[10] , |
| \u_riscv_top.core0_timer_val[9] , |
| \u_riscv_top.core0_timer_val[8] , |
| \u_riscv_top.core0_timer_val[7] , |
| \u_riscv_top.core0_timer_val[6] , |
| \u_riscv_top.core0_timer_val[5] , |
| \u_riscv_top.core0_timer_val[4] , |
| \u_riscv_top.core0_timer_val[3] , |
| \u_riscv_top.core0_timer_val[2] , |
| \u_riscv_top.core0_timer_val[1] , |
| \u_riscv_top.core0_timer_val[0] }), |
| .core0_uid({\u_riscv_top.core0_uid[1] , |
| \u_riscv_top.core0_uid[0] }), |
| .core1_debug({\u_riscv_top.core1_debug[48] , |
| \u_riscv_top.core1_debug[47] , |
| \u_riscv_top.core1_debug[46] , |
| \u_riscv_top.core1_debug[45] , |
| \u_riscv_top.core1_debug[44] , |
| \u_riscv_top.core1_debug[43] , |
| \u_riscv_top.core1_debug[42] , |
| \u_riscv_top.core1_debug[41] , |
| \u_riscv_top.core1_debug[40] , |
| \u_riscv_top.core1_debug[39] , |
| \u_riscv_top.core1_debug[38] , |
| \u_riscv_top.core1_debug[37] , |
| \u_riscv_top.core1_debug[36] , |
| \u_riscv_top.core1_debug[35] , |
| \u_riscv_top.core1_debug[34] , |
| \u_riscv_top.core1_debug[33] , |
| \u_riscv_top.core1_debug[32] , |
| \u_riscv_top.core1_debug[31] , |
| \u_riscv_top.core1_debug[30] , |
| \u_riscv_top.core1_debug[29] , |
| \u_riscv_top.core1_debug[28] , |
| \u_riscv_top.core1_debug[27] , |
| \u_riscv_top.core1_debug[26] , |
| \u_riscv_top.core1_debug[25] , |
| \u_riscv_top.core1_debug[24] , |
| \u_riscv_top.core1_debug[23] , |
| \u_riscv_top.core1_debug[22] , |
| \u_riscv_top.core1_debug[21] , |
| \u_riscv_top.core1_debug[20] , |
| \u_riscv_top.core1_debug[19] , |
| \u_riscv_top.core1_debug[18] , |
| \u_riscv_top.core1_debug[17] , |
| \u_riscv_top.core1_debug[16] , |
| \u_riscv_top.core1_debug[15] , |
| \u_riscv_top.core1_debug[14] , |
| \u_riscv_top.core1_debug[13] , |
| \u_riscv_top.core1_debug[12] , |
| \u_riscv_top.core1_debug[11] , |
| \u_riscv_top.core1_debug[10] , |
| \u_riscv_top.core1_debug[9] , |
| \u_riscv_top.core1_debug[8] , |
| \u_riscv_top.core1_debug[7] , |
| \u_riscv_top.core1_debug[6] , |
| \u_riscv_top.core1_debug[5] , |
| \u_riscv_top.core1_debug[4] , |
| \u_riscv_top.core1_debug[3] , |
| \u_riscv_top.core1_debug[2] , |
| \u_riscv_top.core1_debug[1] , |
| \u_riscv_top.core1_debug[0] }), |
| .core1_dmem_addr({\u_riscv_top.core1_dmem_addr[31] , |
| \u_riscv_top.core1_dmem_addr[30] , |
| \u_riscv_top.core1_dmem_addr[29] , |
| \u_riscv_top.core1_dmem_addr[28] , |
| \u_riscv_top.core1_dmem_addr[27] , |
| \u_riscv_top.core1_dmem_addr[26] , |
| \u_riscv_top.core1_dmem_addr[25] , |
| \u_riscv_top.core1_dmem_addr[24] , |
| \u_riscv_top.core1_dmem_addr[23] , |
| \u_riscv_top.core1_dmem_addr[22] , |
| \u_riscv_top.core1_dmem_addr[21] , |
| \u_riscv_top.core1_dmem_addr[20] , |
| \u_riscv_top.core1_dmem_addr[19] , |
| \u_riscv_top.core1_dmem_addr[18] , |
| \u_riscv_top.core1_dmem_addr[17] , |
| \u_riscv_top.core1_dmem_addr[16] , |
| \u_riscv_top.core1_dmem_addr[15] , |
| \u_riscv_top.core1_dmem_addr[14] , |
| \u_riscv_top.core1_dmem_addr[13] , |
| \u_riscv_top.core1_dmem_addr[12] , |
| \u_riscv_top.core1_dmem_addr[11] , |
| \u_riscv_top.core1_dmem_addr[10] , |
| \u_riscv_top.core1_dmem_addr[9] , |
| \u_riscv_top.core1_dmem_addr[8] , |
| \u_riscv_top.core1_dmem_addr[7] , |
| \u_riscv_top.core1_dmem_addr[6] , |
| \u_riscv_top.core1_dmem_addr[5] , |
| \u_riscv_top.core1_dmem_addr[4] , |
| \u_riscv_top.core1_dmem_addr[3] , |
| \u_riscv_top.core1_dmem_addr[2] , |
| \u_riscv_top.core1_dmem_addr[1] , |
| \u_riscv_top.core1_dmem_addr[0] }), |
| .core1_dmem_rdata({\u_riscv_top.core1_dmem_rdata[31] , |
| \u_riscv_top.core1_dmem_rdata[30] , |
| \u_riscv_top.core1_dmem_rdata[29] , |
| \u_riscv_top.core1_dmem_rdata[28] , |
| \u_riscv_top.core1_dmem_rdata[27] , |
| \u_riscv_top.core1_dmem_rdata[26] , |
| \u_riscv_top.core1_dmem_rdata[25] , |
| \u_riscv_top.core1_dmem_rdata[24] , |
| \u_riscv_top.core1_dmem_rdata[23] , |
| \u_riscv_top.core1_dmem_rdata[22] , |
| \u_riscv_top.core1_dmem_rdata[21] , |
| \u_riscv_top.core1_dmem_rdata[20] , |
| \u_riscv_top.core1_dmem_rdata[19] , |
| \u_riscv_top.core1_dmem_rdata[18] , |
| \u_riscv_top.core1_dmem_rdata[17] , |
| \u_riscv_top.core1_dmem_rdata[16] , |
| \u_riscv_top.core1_dmem_rdata[15] , |
| \u_riscv_top.core1_dmem_rdata[14] , |
| \u_riscv_top.core1_dmem_rdata[13] , |
| \u_riscv_top.core1_dmem_rdata[12] , |
| \u_riscv_top.core1_dmem_rdata[11] , |
| \u_riscv_top.core1_dmem_rdata[10] , |
| \u_riscv_top.core1_dmem_rdata[9] , |
| \u_riscv_top.core1_dmem_rdata[8] , |
| \u_riscv_top.core1_dmem_rdata[7] , |
| \u_riscv_top.core1_dmem_rdata[6] , |
| \u_riscv_top.core1_dmem_rdata[5] , |
| \u_riscv_top.core1_dmem_rdata[4] , |
| \u_riscv_top.core1_dmem_rdata[3] , |
| \u_riscv_top.core1_dmem_rdata[2] , |
| \u_riscv_top.core1_dmem_rdata[1] , |
| \u_riscv_top.core1_dmem_rdata[0] }), |
| .core1_dmem_resp({\u_riscv_top.core1_dmem_resp[1] , |
| \u_riscv_top.core1_dmem_resp[0] }), |
| .core1_dmem_wdata({\u_riscv_top.core1_dmem_wdata[31] , |
| \u_riscv_top.core1_dmem_wdata[30] , |
| \u_riscv_top.core1_dmem_wdata[29] , |
| \u_riscv_top.core1_dmem_wdata[28] , |
| \u_riscv_top.core1_dmem_wdata[27] , |
| \u_riscv_top.core1_dmem_wdata[26] , |
| \u_riscv_top.core1_dmem_wdata[25] , |
| \u_riscv_top.core1_dmem_wdata[24] , |
| \u_riscv_top.core1_dmem_wdata[23] , |
| \u_riscv_top.core1_dmem_wdata[22] , |
| \u_riscv_top.core1_dmem_wdata[21] , |
| \u_riscv_top.core1_dmem_wdata[20] , |
| \u_riscv_top.core1_dmem_wdata[19] , |
| \u_riscv_top.core1_dmem_wdata[18] , |
| \u_riscv_top.core1_dmem_wdata[17] , |
| \u_riscv_top.core1_dmem_wdata[16] , |
| \u_riscv_top.core1_dmem_wdata[15] , |
| \u_riscv_top.core1_dmem_wdata[14] , |
| \u_riscv_top.core1_dmem_wdata[13] , |
| \u_riscv_top.core1_dmem_wdata[12] , |
| \u_riscv_top.core1_dmem_wdata[11] , |
| \u_riscv_top.core1_dmem_wdata[10] , |
| \u_riscv_top.core1_dmem_wdata[9] , |
| \u_riscv_top.core1_dmem_wdata[8] , |
| \u_riscv_top.core1_dmem_wdata[7] , |
| \u_riscv_top.core1_dmem_wdata[6] , |
| \u_riscv_top.core1_dmem_wdata[5] , |
| \u_riscv_top.core1_dmem_wdata[4] , |
| \u_riscv_top.core1_dmem_wdata[3] , |
| \u_riscv_top.core1_dmem_wdata[2] , |
| \u_riscv_top.core1_dmem_wdata[1] , |
| \u_riscv_top.core1_dmem_wdata[0] }), |
| .core1_dmem_width({\u_riscv_top.core1_dmem_width[1] , |
| \u_riscv_top.core1_dmem_width[0] }), |
| .core1_imem_addr({\u_riscv_top.core1_imem_addr[31] , |
| \u_riscv_top.core1_imem_addr[30] , |
| \u_riscv_top.core1_imem_addr[29] , |
| \u_riscv_top.core1_imem_addr[28] , |
| \u_riscv_top.core1_imem_addr[27] , |
| \u_riscv_top.core1_imem_addr[26] , |
| \u_riscv_top.core1_imem_addr[25] , |
| \u_riscv_top.core1_imem_addr[24] , |
| \u_riscv_top.core1_imem_addr[23] , |
| \u_riscv_top.core1_imem_addr[22] , |
| \u_riscv_top.core1_imem_addr[21] , |
| \u_riscv_top.core1_imem_addr[20] , |
| \u_riscv_top.core1_imem_addr[19] , |
| \u_riscv_top.core1_imem_addr[18] , |
| \u_riscv_top.core1_imem_addr[17] , |
| \u_riscv_top.core1_imem_addr[16] , |
| \u_riscv_top.core1_imem_addr[15] , |
| \u_riscv_top.core1_imem_addr[14] , |
| \u_riscv_top.core1_imem_addr[13] , |
| \u_riscv_top.core1_imem_addr[12] , |
| \u_riscv_top.core1_imem_addr[11] , |
| \u_riscv_top.core1_imem_addr[10] , |
| \u_riscv_top.core1_imem_addr[9] , |
| \u_riscv_top.core1_imem_addr[8] , |
| \u_riscv_top.core1_imem_addr[7] , |
| \u_riscv_top.core1_imem_addr[6] , |
| \u_riscv_top.core1_imem_addr[5] , |
| \u_riscv_top.core1_imem_addr[4] , |
| \u_riscv_top.core1_imem_addr[3] , |
| \u_riscv_top.core1_imem_addr[2] , |
| \u_riscv_top.core1_imem_addr[1] , |
| \u_riscv_top.core1_imem_addr[0] }), |
| .core1_imem_bl({\u_riscv_top.core1_imem_bl[2] , |
| \u_riscv_top.core1_imem_bl[1] , |
| \u_riscv_top.core1_imem_bl[0] }), |
| .core1_imem_rdata({\u_riscv_top.core1_imem_rdata[31] , |
| \u_riscv_top.core1_imem_rdata[30] , |
| \u_riscv_top.core1_imem_rdata[29] , |
| \u_riscv_top.core1_imem_rdata[28] , |
| \u_riscv_top.core1_imem_rdata[27] , |
| \u_riscv_top.core1_imem_rdata[26] , |
| \u_riscv_top.core1_imem_rdata[25] , |
| \u_riscv_top.core1_imem_rdata[24] , |
| \u_riscv_top.core1_imem_rdata[23] , |
| \u_riscv_top.core1_imem_rdata[22] , |
| \u_riscv_top.core1_imem_rdata[21] , |
| \u_riscv_top.core1_imem_rdata[20] , |
| \u_riscv_top.core1_imem_rdata[19] , |
| \u_riscv_top.core1_imem_rdata[18] , |
| \u_riscv_top.core1_imem_rdata[17] , |
| \u_riscv_top.core1_imem_rdata[16] , |
| \u_riscv_top.core1_imem_rdata[15] , |
| \u_riscv_top.core1_imem_rdata[14] , |
| \u_riscv_top.core1_imem_rdata[13] , |
| \u_riscv_top.core1_imem_rdata[12] , |
| \u_riscv_top.core1_imem_rdata[11] , |
| \u_riscv_top.core1_imem_rdata[10] , |
| \u_riscv_top.core1_imem_rdata[9] , |
| \u_riscv_top.core1_imem_rdata[8] , |
| \u_riscv_top.core1_imem_rdata[7] , |
| \u_riscv_top.core1_imem_rdata[6] , |
| \u_riscv_top.core1_imem_rdata[5] , |
| \u_riscv_top.core1_imem_rdata[4] , |
| \u_riscv_top.core1_imem_rdata[3] , |
| \u_riscv_top.core1_imem_rdata[2] , |
| \u_riscv_top.core1_imem_rdata[1] , |
| \u_riscv_top.core1_imem_rdata[0] }), |
| .core1_imem_resp({\u_riscv_top.core1_imem_resp[1] , |
| \u_riscv_top.core1_imem_resp[0] }), |
| .core1_irq_lines({\u_riscv_top.core1_irq_lines[31] , |
| \u_riscv_top.core1_irq_lines[30] , |
| \u_riscv_top.core1_irq_lines[29] , |
| \u_riscv_top.core1_irq_lines[28] , |
| \u_riscv_top.core1_irq_lines[27] , |
| \u_riscv_top.core1_irq_lines[26] , |
| \u_riscv_top.core1_irq_lines[25] , |
| \u_riscv_top.core1_irq_lines[24] , |
| \u_riscv_top.core1_irq_lines[23] , |
| \u_riscv_top.core1_irq_lines[22] , |
| \u_riscv_top.core1_irq_lines[21] , |
| \u_riscv_top.core1_irq_lines[20] , |
| \u_riscv_top.core1_irq_lines[19] , |
| \u_riscv_top.core1_irq_lines[18] , |
| \u_riscv_top.core1_irq_lines[17] , |
| \u_riscv_top.core1_irq_lines[16] , |
| \u_riscv_top.core1_irq_lines[15] , |
| \u_riscv_top.core1_irq_lines[14] , |
| \u_riscv_top.core1_irq_lines[13] , |
| \u_riscv_top.core1_irq_lines[12] , |
| \u_riscv_top.core1_irq_lines[11] , |
| \u_riscv_top.core1_irq_lines[10] , |
| \u_riscv_top.core1_irq_lines[9] , |
| \u_riscv_top.core1_irq_lines[8] , |
| \u_riscv_top.core1_irq_lines[7] , |
| \u_riscv_top.core1_irq_lines[6] , |
| \u_riscv_top.core1_irq_lines[5] , |
| \u_riscv_top.core1_irq_lines[4] , |
| \u_riscv_top.core1_irq_lines[3] , |
| \u_riscv_top.core1_irq_lines[2] , |
| \u_riscv_top.core1_irq_lines[1] , |
| \u_riscv_top.core1_irq_lines[0] }), |
| .core1_timer_val({\u_riscv_top.core1_timer_val[63] , |
| \u_riscv_top.core1_timer_val[62] , |
| \u_riscv_top.core1_timer_val[61] , |
| \u_riscv_top.core1_timer_val[60] , |
| \u_riscv_top.core1_timer_val[59] , |
| \u_riscv_top.core1_timer_val[58] , |
| \u_riscv_top.core1_timer_val[57] , |
| \u_riscv_top.core1_timer_val[56] , |
| \u_riscv_top.core1_timer_val[55] , |
| \u_riscv_top.core1_timer_val[54] , |
| \u_riscv_top.core1_timer_val[53] , |
| \u_riscv_top.core1_timer_val[52] , |
| \u_riscv_top.core1_timer_val[51] , |
| \u_riscv_top.core1_timer_val[50] , |
| \u_riscv_top.core1_timer_val[49] , |
| \u_riscv_top.core1_timer_val[48] , |
| \u_riscv_top.core1_timer_val[47] , |
| \u_riscv_top.core1_timer_val[46] , |
| \u_riscv_top.core1_timer_val[45] , |
| \u_riscv_top.core1_timer_val[44] , |
| \u_riscv_top.core1_timer_val[43] , |
| \u_riscv_top.core1_timer_val[42] , |
| \u_riscv_top.core1_timer_val[41] , |
| \u_riscv_top.core1_timer_val[40] , |
| \u_riscv_top.core1_timer_val[39] , |
| \u_riscv_top.core1_timer_val[38] , |
| \u_riscv_top.core1_timer_val[37] , |
| \u_riscv_top.core1_timer_val[36] , |
| \u_riscv_top.core1_timer_val[35] , |
| \u_riscv_top.core1_timer_val[34] , |
| \u_riscv_top.core1_timer_val[33] , |
| \u_riscv_top.core1_timer_val[32] , |
| \u_riscv_top.core1_timer_val[31] , |
| \u_riscv_top.core1_timer_val[30] , |
| \u_riscv_top.core1_timer_val[29] , |
| \u_riscv_top.core1_timer_val[28] , |
| \u_riscv_top.core1_timer_val[27] , |
| \u_riscv_top.core1_timer_val[26] , |
| \u_riscv_top.core1_timer_val[25] , |
| \u_riscv_top.core1_timer_val[24] , |
| \u_riscv_top.core1_timer_val[23] , |
| \u_riscv_top.core1_timer_val[22] , |
| \u_riscv_top.core1_timer_val[21] , |
| \u_riscv_top.core1_timer_val[20] , |
| \u_riscv_top.core1_timer_val[19] , |
| \u_riscv_top.core1_timer_val[18] , |
| \u_riscv_top.core1_timer_val[17] , |
| \u_riscv_top.core1_timer_val[16] , |
| \u_riscv_top.core1_timer_val[15] , |
| \u_riscv_top.core1_timer_val[14] , |
| \u_riscv_top.core1_timer_val[13] , |
| \u_riscv_top.core1_timer_val[12] , |
| \u_riscv_top.core1_timer_val[11] , |
| \u_riscv_top.core1_timer_val[10] , |
| \u_riscv_top.core1_timer_val[9] , |
| \u_riscv_top.core1_timer_val[8] , |
| \u_riscv_top.core1_timer_val[7] , |
| \u_riscv_top.core1_timer_val[6] , |
| \u_riscv_top.core1_timer_val[5] , |
| \u_riscv_top.core1_timer_val[4] , |
| \u_riscv_top.core1_timer_val[3] , |
| \u_riscv_top.core1_timer_val[2] , |
| \u_riscv_top.core1_timer_val[1] , |
| \u_riscv_top.core1_timer_val[0] }), |
| .core1_uid({\u_riscv_top.core1_uid[1] , |
| \u_riscv_top.core1_uid[0] }), |
| .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] , |
| \u_riscv_top.core_dcache_addr[30] , |
| \u_riscv_top.core_dcache_addr[29] , |
| \u_riscv_top.core_dcache_addr[28] , |
| \u_riscv_top.core_dcache_addr[27] , |
| \u_riscv_top.core_dcache_addr[26] , |
| \u_riscv_top.core_dcache_addr[25] , |
| \u_riscv_top.core_dcache_addr[24] , |
| \u_riscv_top.core_dcache_addr[23] , |
| \u_riscv_top.core_dcache_addr[22] , |
| \u_riscv_top.core_dcache_addr[21] , |
| \u_riscv_top.core_dcache_addr[20] , |
| \u_riscv_top.core_dcache_addr[19] , |
| \u_riscv_top.core_dcache_addr[18] , |
| \u_riscv_top.core_dcache_addr[17] , |
| \u_riscv_top.core_dcache_addr[16] , |
| \u_riscv_top.core_dcache_addr[15] , |
| \u_riscv_top.core_dcache_addr[14] , |
| \u_riscv_top.core_dcache_addr[13] , |
| \u_riscv_top.core_dcache_addr[12] , |
| \u_riscv_top.core_dcache_addr[11] , |
| \u_riscv_top.core_dcache_addr[10] , |
| \u_riscv_top.core_dcache_addr[9] , |
| \u_riscv_top.core_dcache_addr[8] , |
| \u_riscv_top.core_dcache_addr[7] , |
| \u_riscv_top.core_dcache_addr[6] , |
| \u_riscv_top.core_dcache_addr[5] , |
| \u_riscv_top.core_dcache_addr[4] , |
| \u_riscv_top.core_dcache_addr[3] , |
| \u_riscv_top.core_dcache_addr[2] , |
| \u_riscv_top.core_dcache_addr[1] , |
| \u_riscv_top.core_dcache_addr[0] }), |
| .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] , |
| \u_riscv_top.core_dcache_rdata[30] , |
| \u_riscv_top.core_dcache_rdata[29] , |
| \u_riscv_top.core_dcache_rdata[28] , |
| \u_riscv_top.core_dcache_rdata[27] , |
| \u_riscv_top.core_dcache_rdata[26] , |
| \u_riscv_top.core_dcache_rdata[25] , |
| \u_riscv_top.core_dcache_rdata[24] , |
| \u_riscv_top.core_dcache_rdata[23] , |
| \u_riscv_top.core_dcache_rdata[22] , |
| \u_riscv_top.core_dcache_rdata[21] , |
| \u_riscv_top.core_dcache_rdata[20] , |
| \u_riscv_top.core_dcache_rdata[19] , |
| \u_riscv_top.core_dcache_rdata[18] , |
| \u_riscv_top.core_dcache_rdata[17] , |
| \u_riscv_top.core_dcache_rdata[16] , |
| \u_riscv_top.core_dcache_rdata[15] , |
| \u_riscv_top.core_dcache_rdata[14] , |
| \u_riscv_top.core_dcache_rdata[13] , |
| \u_riscv_top.core_dcache_rdata[12] , |
| \u_riscv_top.core_dcache_rdata[11] , |
| \u_riscv_top.core_dcache_rdata[10] , |
| \u_riscv_top.core_dcache_rdata[9] , |
| \u_riscv_top.core_dcache_rdata[8] , |
| \u_riscv_top.core_dcache_rdata[7] , |
| \u_riscv_top.core_dcache_rdata[6] , |
| \u_riscv_top.core_dcache_rdata[5] , |
| \u_riscv_top.core_dcache_rdata[4] , |
| \u_riscv_top.core_dcache_rdata[3] , |
| \u_riscv_top.core_dcache_rdata[2] , |
| \u_riscv_top.core_dcache_rdata[1] , |
| \u_riscv_top.core_dcache_rdata[0] }), |
| .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] , |
| \u_riscv_top.core_dcache_resp[0] }), |
| .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] , |
| \u_riscv_top.core_dcache_wdata[30] , |
| \u_riscv_top.core_dcache_wdata[29] , |
| \u_riscv_top.core_dcache_wdata[28] , |
| \u_riscv_top.core_dcache_wdata[27] , |
| \u_riscv_top.core_dcache_wdata[26] , |
| \u_riscv_top.core_dcache_wdata[25] , |
| \u_riscv_top.core_dcache_wdata[24] , |
| \u_riscv_top.core_dcache_wdata[23] , |
| \u_riscv_top.core_dcache_wdata[22] , |
| \u_riscv_top.core_dcache_wdata[21] , |
| \u_riscv_top.core_dcache_wdata[20] , |
| \u_riscv_top.core_dcache_wdata[19] , |
| \u_riscv_top.core_dcache_wdata[18] , |
| \u_riscv_top.core_dcache_wdata[17] , |
| \u_riscv_top.core_dcache_wdata[16] , |
| \u_riscv_top.core_dcache_wdata[15] , |
| \u_riscv_top.core_dcache_wdata[14] , |
| \u_riscv_top.core_dcache_wdata[13] , |
| \u_riscv_top.core_dcache_wdata[12] , |
| \u_riscv_top.core_dcache_wdata[11] , |
| \u_riscv_top.core_dcache_wdata[10] , |
| \u_riscv_top.core_dcache_wdata[9] , |
| \u_riscv_top.core_dcache_wdata[8] , |
| \u_riscv_top.core_dcache_wdata[7] , |
| \u_riscv_top.core_dcache_wdata[6] , |
| \u_riscv_top.core_dcache_wdata[5] , |
| \u_riscv_top.core_dcache_wdata[4] , |
| \u_riscv_top.core_dcache_wdata[3] , |
| \u_riscv_top.core_dcache_wdata[2] , |
| \u_riscv_top.core_dcache_wdata[1] , |
| \u_riscv_top.core_dcache_wdata[0] }), |
| .core_dcache_width({\u_riscv_top.core_dcache_width[1] , |
| \u_riscv_top.core_dcache_width[0] }), |
| .core_debug_sel({\cfg_riscv_ctrl[9] , |
| \cfg_riscv_ctrl[8] }), |
| .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] , |
| \u_riscv_top.core_dmem_addr[30] , |
| \u_riscv_top.core_dmem_addr[29] , |
| \u_riscv_top.core_dmem_addr[28] , |
| \u_riscv_top.core_dmem_addr[27] , |
| \u_riscv_top.core_dmem_addr[26] , |
| \u_riscv_top.core_dmem_addr[25] , |
| \u_riscv_top.core_dmem_addr[24] , |
| \u_riscv_top.core_dmem_addr[23] , |
| \u_riscv_top.core_dmem_addr[22] , |
| \u_riscv_top.core_dmem_addr[21] , |
| \u_riscv_top.core_dmem_addr[20] , |
| \u_riscv_top.core_dmem_addr[19] , |
| \u_riscv_top.core_dmem_addr[18] , |
| \u_riscv_top.core_dmem_addr[17] , |
| \u_riscv_top.core_dmem_addr[16] , |
| \u_riscv_top.core_dmem_addr[15] , |
| \u_riscv_top.core_dmem_addr[14] , |
| \u_riscv_top.core_dmem_addr[13] , |
| \u_riscv_top.core_dmem_addr[12] , |
| \u_riscv_top.core_dmem_addr[11] , |
| \u_riscv_top.core_dmem_addr[10] , |
| \u_riscv_top.core_dmem_addr[9] , |
| \u_riscv_top.core_dmem_addr[8] , |
| \u_riscv_top.core_dmem_addr[7] , |
| \u_riscv_top.core_dmem_addr[6] , |
| \u_riscv_top.core_dmem_addr[5] , |
| \u_riscv_top.core_dmem_addr[4] , |
| \u_riscv_top.core_dmem_addr[3] , |
| \u_riscv_top.core_dmem_addr[2] , |
| \u_riscv_top.core_dmem_addr[1] , |
| \u_riscv_top.core_dmem_addr[0] }), |
| .core_dmem_bl({\u_riscv_top.core_dmem_bl[2] , |
| \u_riscv_top.core_dmem_bl[1] , |
| \u_riscv_top.core_dmem_bl[0] }), |
| .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] , |
| \u_riscv_top.core_dmem_rdata[30] , |
| \u_riscv_top.core_dmem_rdata[29] , |
| \u_riscv_top.core_dmem_rdata[28] , |
| \u_riscv_top.core_dmem_rdata[27] , |
| \u_riscv_top.core_dmem_rdata[26] , |
| \u_riscv_top.core_dmem_rdata[25] , |
| \u_riscv_top.core_dmem_rdata[24] , |
| \u_riscv_top.core_dmem_rdata[23] , |
| \u_riscv_top.core_dmem_rdata[22] , |
| \u_riscv_top.core_dmem_rdata[21] , |
| \u_riscv_top.core_dmem_rdata[20] , |
| \u_riscv_top.core_dmem_rdata[19] , |
| \u_riscv_top.core_dmem_rdata[18] , |
| \u_riscv_top.core_dmem_rdata[17] , |
| \u_riscv_top.core_dmem_rdata[16] , |
| \u_riscv_top.core_dmem_rdata[15] , |
| \u_riscv_top.core_dmem_rdata[14] , |
| \u_riscv_top.core_dmem_rdata[13] , |
| \u_riscv_top.core_dmem_rdata[12] , |
| \u_riscv_top.core_dmem_rdata[11] , |
| \u_riscv_top.core_dmem_rdata[10] , |
| \u_riscv_top.core_dmem_rdata[9] , |
| \u_riscv_top.core_dmem_rdata[8] , |
| \u_riscv_top.core_dmem_rdata[7] , |
| \u_riscv_top.core_dmem_rdata[6] , |
| \u_riscv_top.core_dmem_rdata[5] , |
| \u_riscv_top.core_dmem_rdata[4] , |
| \u_riscv_top.core_dmem_rdata[3] , |
| \u_riscv_top.core_dmem_rdata[2] , |
| \u_riscv_top.core_dmem_rdata[1] , |
| \u_riscv_top.core_dmem_rdata[0] }), |
| .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] , |
| \u_riscv_top.core_dmem_resp[0] }), |
| .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] , |
| \u_riscv_top.core_dmem_wdata[30] , |
| \u_riscv_top.core_dmem_wdata[29] , |
| \u_riscv_top.core_dmem_wdata[28] , |
| \u_riscv_top.core_dmem_wdata[27] , |
| \u_riscv_top.core_dmem_wdata[26] , |
| \u_riscv_top.core_dmem_wdata[25] , |
| \u_riscv_top.core_dmem_wdata[24] , |
| \u_riscv_top.core_dmem_wdata[23] , |
| \u_riscv_top.core_dmem_wdata[22] , |
| \u_riscv_top.core_dmem_wdata[21] , |
| \u_riscv_top.core_dmem_wdata[20] , |
| \u_riscv_top.core_dmem_wdata[19] , |
| \u_riscv_top.core_dmem_wdata[18] , |
| \u_riscv_top.core_dmem_wdata[17] , |
| \u_riscv_top.core_dmem_wdata[16] , |
| \u_riscv_top.core_dmem_wdata[15] , |
| \u_riscv_top.core_dmem_wdata[14] , |
| \u_riscv_top.core_dmem_wdata[13] , |
| \u_riscv_top.core_dmem_wdata[12] , |
| \u_riscv_top.core_dmem_wdata[11] , |
| \u_riscv_top.core_dmem_wdata[10] , |
| \u_riscv_top.core_dmem_wdata[9] , |
| \u_riscv_top.core_dmem_wdata[8] , |
| \u_riscv_top.core_dmem_wdata[7] , |
| \u_riscv_top.core_dmem_wdata[6] , |
| \u_riscv_top.core_dmem_wdata[5] , |
| \u_riscv_top.core_dmem_wdata[4] , |
| \u_riscv_top.core_dmem_wdata[3] , |
| \u_riscv_top.core_dmem_wdata[2] , |
| \u_riscv_top.core_dmem_wdata[1] , |
| \u_riscv_top.core_dmem_wdata[0] }), |
| .core_dmem_width({\u_riscv_top.core_dmem_width[1] , |
| \u_riscv_top.core_dmem_width[0] }), |
| .core_icache_addr({\u_riscv_top.core_icache_addr[31] , |
| \u_riscv_top.core_icache_addr[30] , |
| \u_riscv_top.core_icache_addr[29] , |
| \u_riscv_top.core_icache_addr[28] , |
| \u_riscv_top.core_icache_addr[27] , |
| \u_riscv_top.core_icache_addr[26] , |
| \u_riscv_top.core_icache_addr[25] , |
| \u_riscv_top.core_icache_addr[24] , |
| \u_riscv_top.core_icache_addr[23] , |
| \u_riscv_top.core_icache_addr[22] , |
| \u_riscv_top.core_icache_addr[21] , |
| \u_riscv_top.core_icache_addr[20] , |
| \u_riscv_top.core_icache_addr[19] , |
| \u_riscv_top.core_icache_addr[18] , |
| \u_riscv_top.core_icache_addr[17] , |
| \u_riscv_top.core_icache_addr[16] , |
| \u_riscv_top.core_icache_addr[15] , |
| \u_riscv_top.core_icache_addr[14] , |
| \u_riscv_top.core_icache_addr[13] , |
| \u_riscv_top.core_icache_addr[12] , |
| \u_riscv_top.core_icache_addr[11] , |
| \u_riscv_top.core_icache_addr[10] , |
| \u_riscv_top.core_icache_addr[9] , |
| \u_riscv_top.core_icache_addr[8] , |
| \u_riscv_top.core_icache_addr[7] , |
| \u_riscv_top.core_icache_addr[6] , |
| \u_riscv_top.core_icache_addr[5] , |
| \u_riscv_top.core_icache_addr[4] , |
| \u_riscv_top.core_icache_addr[3] , |
| \u_riscv_top.core_icache_addr[2] , |
| \u_riscv_top.core_icache_addr[1] , |
| \u_riscv_top.core_icache_addr[0] }), |
| .core_icache_bl({\u_riscv_top.core_icache_bl[2] , |
| \u_riscv_top.core_icache_bl[1] , |
| \u_riscv_top.core_icache_bl[0] }), |
| .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] , |
| \u_riscv_top.core_icache_rdata[30] , |
| \u_riscv_top.core_icache_rdata[29] , |
| \u_riscv_top.core_icache_rdata[28] , |
| \u_riscv_top.core_icache_rdata[27] , |
| \u_riscv_top.core_icache_rdata[26] , |
| \u_riscv_top.core_icache_rdata[25] , |
| \u_riscv_top.core_icache_rdata[24] , |
| \u_riscv_top.core_icache_rdata[23] , |
| \u_riscv_top.core_icache_rdata[22] , |
| \u_riscv_top.core_icache_rdata[21] , |
| \u_riscv_top.core_icache_rdata[20] , |
| \u_riscv_top.core_icache_rdata[19] , |
| \u_riscv_top.core_icache_rdata[18] , |
| \u_riscv_top.core_icache_rdata[17] , |
| \u_riscv_top.core_icache_rdata[16] , |
| \u_riscv_top.core_icache_rdata[15] , |
| \u_riscv_top.core_icache_rdata[14] , |
| \u_riscv_top.core_icache_rdata[13] , |
| \u_riscv_top.core_icache_rdata[12] , |
| \u_riscv_top.core_icache_rdata[11] , |
| \u_riscv_top.core_icache_rdata[10] , |
| \u_riscv_top.core_icache_rdata[9] , |
| \u_riscv_top.core_icache_rdata[8] , |
| \u_riscv_top.core_icache_rdata[7] , |
| \u_riscv_top.core_icache_rdata[6] , |
| \u_riscv_top.core_icache_rdata[5] , |
| \u_riscv_top.core_icache_rdata[4] , |
| \u_riscv_top.core_icache_rdata[3] , |
| \u_riscv_top.core_icache_rdata[2] , |
| \u_riscv_top.core_icache_rdata[1] , |
| \u_riscv_top.core_icache_rdata[0] }), |
| .core_icache_resp({\u_riscv_top.core_icache_resp[1] , |
| \u_riscv_top.core_icache_resp[0] }), |
| .core_icache_width({\u_riscv_top.core_icache_width[1] , |
| \u_riscv_top.core_icache_width[0] }), |
| .core_irq_lines_i({\u_riscv_top.irq_lines[31] , |
| \u_riscv_top.irq_lines[30] , |
| \u_riscv_top.irq_lines[29] , |
| \u_riscv_top.irq_lines[28] , |
| \u_riscv_top.irq_lines[27] , |
| \u_riscv_top.irq_lines[26] , |
| \u_riscv_top.irq_lines[25] , |
| \u_riscv_top.irq_lines[24] , |
| \u_riscv_top.irq_lines[23] , |
| \u_riscv_top.irq_lines[22] , |
| \u_riscv_top.irq_lines[21] , |
| \u_riscv_top.irq_lines[20] , |
| \u_riscv_top.irq_lines[19] , |
| \u_riscv_top.irq_lines[18] , |
| \u_riscv_top.irq_lines[17] , |
| \u_riscv_top.irq_lines[16] , |
| \u_riscv_top.irq_lines[15] , |
| \u_riscv_top.irq_lines[14] , |
| \u_riscv_top.irq_lines[13] , |
| \u_riscv_top.irq_lines[12] , |
| \u_riscv_top.irq_lines[11] , |
| \u_riscv_top.irq_lines[10] , |
| \u_riscv_top.irq_lines[9] , |
| \u_riscv_top.irq_lines[8] , |
| \u_riscv_top.irq_lines[7] , |
| \u_riscv_top.irq_lines[6] , |
| \u_riscv_top.irq_lines[5] , |
| \u_riscv_top.irq_lines[4] , |
| \u_riscv_top.irq_lines[3] , |
| \u_riscv_top.irq_lines[2] , |
| \u_riscv_top.irq_lines[1] , |
| \u_riscv_top.irq_lines[0] }), |
| .fpu_dmem_addr({\u_riscv_top.fpu_dmem_addr[4] , |
| \u_riscv_top.fpu_dmem_addr[3] , |
| \u_riscv_top.fpu_dmem_addr[2] , |
| \u_riscv_top.fpu_dmem_addr[1] , |
| \u_riscv_top.fpu_dmem_addr[0] }), |
| .fpu_dmem_rdata({\u_riscv_top.fpu_dmem_rdata[31] , |
| \u_riscv_top.fpu_dmem_rdata[30] , |
| \u_riscv_top.fpu_dmem_rdata[29] , |
| \u_riscv_top.fpu_dmem_rdata[28] , |
| \u_riscv_top.fpu_dmem_rdata[27] , |
| \u_riscv_top.fpu_dmem_rdata[26] , |
| \u_riscv_top.fpu_dmem_rdata[25] , |
| \u_riscv_top.fpu_dmem_rdata[24] , |
| \u_riscv_top.fpu_dmem_rdata[23] , |
| \u_riscv_top.fpu_dmem_rdata[22] , |
| \u_riscv_top.fpu_dmem_rdata[21] , |
| \u_riscv_top.fpu_dmem_rdata[20] , |
| \u_riscv_top.fpu_dmem_rdata[19] , |
| \u_riscv_top.fpu_dmem_rdata[18] , |
| \u_riscv_top.fpu_dmem_rdata[17] , |
| \u_riscv_top.fpu_dmem_rdata[16] , |
| \u_riscv_top.fpu_dmem_rdata[15] , |
| \u_riscv_top.fpu_dmem_rdata[14] , |
| \u_riscv_top.fpu_dmem_rdata[13] , |
| \u_riscv_top.fpu_dmem_rdata[12] , |
| \u_riscv_top.fpu_dmem_rdata[11] , |
| \u_riscv_top.fpu_dmem_rdata[10] , |
| \u_riscv_top.fpu_dmem_rdata[9] , |
| \u_riscv_top.fpu_dmem_rdata[8] , |
| \u_riscv_top.fpu_dmem_rdata[7] , |
| \u_riscv_top.fpu_dmem_rdata[6] , |
| \u_riscv_top.fpu_dmem_rdata[5] , |
| \u_riscv_top.fpu_dmem_rdata[4] , |
| \u_riscv_top.fpu_dmem_rdata[3] , |
| \u_riscv_top.fpu_dmem_rdata[2] , |
| \u_riscv_top.fpu_dmem_rdata[1] , |
| \u_riscv_top.fpu_dmem_rdata[0] }), |
| .fpu_dmem_resp({\u_riscv_top.fpu_dmem_resp[1] , |
| \u_riscv_top.fpu_dmem_resp[0] }), |
| .fpu_dmem_wdata({\u_riscv_top.fpu_dmem_wdata[31] , |
| \u_riscv_top.fpu_dmem_wdata[30] , |
| \u_riscv_top.fpu_dmem_wdata[29] , |
| \u_riscv_top.fpu_dmem_wdata[28] , |
| \u_riscv_top.fpu_dmem_wdata[27] , |
| \u_riscv_top.fpu_dmem_wdata[26] , |
| \u_riscv_top.fpu_dmem_wdata[25] , |
| \u_riscv_top.fpu_dmem_wdata[24] , |
| \u_riscv_top.fpu_dmem_wdata[23] , |
| \u_riscv_top.fpu_dmem_wdata[22] , |
| \u_riscv_top.fpu_dmem_wdata[21] , |
| \u_riscv_top.fpu_dmem_wdata[20] , |
| \u_riscv_top.fpu_dmem_wdata[19] , |
| \u_riscv_top.fpu_dmem_wdata[18] , |
| \u_riscv_top.fpu_dmem_wdata[17] , |
| \u_riscv_top.fpu_dmem_wdata[16] , |
| \u_riscv_top.fpu_dmem_wdata[15] , |
| \u_riscv_top.fpu_dmem_wdata[14] , |
| \u_riscv_top.fpu_dmem_wdata[13] , |
| \u_riscv_top.fpu_dmem_wdata[12] , |
| \u_riscv_top.fpu_dmem_wdata[11] , |
| \u_riscv_top.fpu_dmem_wdata[10] , |
| \u_riscv_top.fpu_dmem_wdata[9] , |
| \u_riscv_top.fpu_dmem_wdata[8] , |
| \u_riscv_top.fpu_dmem_wdata[7] , |
| \u_riscv_top.fpu_dmem_wdata[6] , |
| \u_riscv_top.fpu_dmem_wdata[5] , |
| \u_riscv_top.fpu_dmem_wdata[4] , |
| \u_riscv_top.fpu_dmem_wdata[3] , |
| \u_riscv_top.fpu_dmem_wdata[2] , |
| \u_riscv_top.fpu_dmem_wdata[1] , |
| \u_riscv_top.fpu_dmem_wdata[0] }), |
| .fpu_dmem_width({\u_riscv_top.fpu_dmem_width[1] , |
| \u_riscv_top.fpu_dmem_width[0] }), |
| .riscv_debug({\u_riscv_top.riscv_debug[63] , |
| \u_riscv_top.riscv_debug[62] , |
| \u_riscv_top.riscv_debug[61] , |
| \u_riscv_top.riscv_debug[60] , |
| \u_riscv_top.riscv_debug[59] , |
| \u_riscv_top.riscv_debug[58] , |
| \u_riscv_top.riscv_debug[57] , |
| \u_riscv_top.riscv_debug[56] , |
| \u_riscv_top.riscv_debug[55] , |
| \u_riscv_top.riscv_debug[54] , |
| \u_riscv_top.riscv_debug[53] , |
| \u_riscv_top.riscv_debug[52] , |
| \u_riscv_top.riscv_debug[51] , |
| \u_riscv_top.riscv_debug[50] , |
| \u_riscv_top.riscv_debug[49] , |
| \u_riscv_top.riscv_debug[48] , |
| \u_riscv_top.riscv_debug[47] , |
| \u_riscv_top.riscv_debug[46] , |
| \u_riscv_top.riscv_debug[45] , |
| \u_riscv_top.riscv_debug[44] , |
| \u_riscv_top.riscv_debug[43] , |
| \u_riscv_top.riscv_debug[42] , |
| \u_riscv_top.riscv_debug[41] , |
| \u_riscv_top.riscv_debug[40] , |
| \u_riscv_top.riscv_debug[39] , |
| \u_riscv_top.riscv_debug[38] , |
| \u_riscv_top.riscv_debug[37] , |
| \u_riscv_top.riscv_debug[36] , |
| \u_riscv_top.riscv_debug[35] , |
| \u_riscv_top.riscv_debug[34] , |
| \u_riscv_top.riscv_debug[33] , |
| \u_riscv_top.riscv_debug[32] , |
| \u_riscv_top.riscv_debug[31] , |
| \u_riscv_top.riscv_debug[30] , |
| \u_riscv_top.riscv_debug[29] , |
| \u_riscv_top.riscv_debug[28] , |
| \u_riscv_top.riscv_debug[27] , |
| \u_riscv_top.riscv_debug[26] , |
| \u_riscv_top.riscv_debug[25] , |
| \u_riscv_top.riscv_debug[24] , |
| \u_riscv_top.riscv_debug[23] , |
| \u_riscv_top.riscv_debug[22] , |
| \u_riscv_top.riscv_debug[21] , |
| \u_riscv_top.riscv_debug[20] , |
| \u_riscv_top.riscv_debug[19] , |
| \u_riscv_top.riscv_debug[18] , |
| \u_riscv_top.riscv_debug[17] , |
| \u_riscv_top.riscv_debug[16] , |
| \u_riscv_top.riscv_debug[15] , |
| \u_riscv_top.riscv_debug[14] , |
| \u_riscv_top.riscv_debug[13] , |
| \u_riscv_top.riscv_debug[12] , |
| \u_riscv_top.riscv_debug[11] , |
| \u_riscv_top.riscv_debug[10] , |
| \u_riscv_top.riscv_debug[9] , |
| \u_riscv_top.riscv_debug[8] , |
| \u_riscv_top.riscv_debug[7] , |
| \u_riscv_top.riscv_debug[6] , |
| \u_riscv_top.riscv_debug[5] , |
| \u_riscv_top.riscv_debug[4] , |
| \u_riscv_top.riscv_debug[3] , |
| \u_riscv_top.riscv_debug[2] , |
| \u_riscv_top.riscv_debug[1] , |
| \u_riscv_top.riscv_debug[0] }), |
| .sram0_addr0({\u_riscv_top.sram0_addr0[8] , |
| \u_riscv_top.sram0_addr0[7] , |
| \u_riscv_top.sram0_addr0[6] , |
| \u_riscv_top.sram0_addr0[5] , |
| \u_riscv_top.sram0_addr0[4] , |
| \u_riscv_top.sram0_addr0[3] , |
| \u_riscv_top.sram0_addr0[2] , |
| \u_riscv_top.sram0_addr0[1] , |
| \u_riscv_top.sram0_addr0[0] }), |
| .sram0_addr1({\u_riscv_top.sram0_addr1[8] , |
| \u_riscv_top.sram0_addr1[7] , |
| \u_riscv_top.sram0_addr1[6] , |
| \u_riscv_top.sram0_addr1[5] , |
| \u_riscv_top.sram0_addr1[4] , |
| \u_riscv_top.sram0_addr1[3] , |
| \u_riscv_top.sram0_addr1[2] , |
| \u_riscv_top.sram0_addr1[1] , |
| \u_riscv_top.sram0_addr1[0] }), |
| .sram0_din0({\u_riscv_top.sram0_din0[31] , |
| \u_riscv_top.sram0_din0[30] , |
| \u_riscv_top.sram0_din0[29] , |
| \u_riscv_top.sram0_din0[28] , |
| \u_riscv_top.sram0_din0[27] , |
| \u_riscv_top.sram0_din0[26] , |
| \u_riscv_top.sram0_din0[25] , |
| \u_riscv_top.sram0_din0[24] , |
| \u_riscv_top.sram0_din0[23] , |
| \u_riscv_top.sram0_din0[22] , |
| \u_riscv_top.sram0_din0[21] , |
| \u_riscv_top.sram0_din0[20] , |
| \u_riscv_top.sram0_din0[19] , |
| \u_riscv_top.sram0_din0[18] , |
| \u_riscv_top.sram0_din0[17] , |
| \u_riscv_top.sram0_din0[16] , |
| \u_riscv_top.sram0_din0[15] , |
| \u_riscv_top.sram0_din0[14] , |
| \u_riscv_top.sram0_din0[13] , |
| \u_riscv_top.sram0_din0[12] , |
| \u_riscv_top.sram0_din0[11] , |
| \u_riscv_top.sram0_din0[10] , |
| \u_riscv_top.sram0_din0[9] , |
| \u_riscv_top.sram0_din0[8] , |
| \u_riscv_top.sram0_din0[7] , |
| \u_riscv_top.sram0_din0[6] , |
| \u_riscv_top.sram0_din0[5] , |
| \u_riscv_top.sram0_din0[4] , |
| \u_riscv_top.sram0_din0[3] , |
| \u_riscv_top.sram0_din0[2] , |
| \u_riscv_top.sram0_din0[1] , |
| \u_riscv_top.sram0_din0[0] }), |
| .sram0_dout0({\u_riscv_top.sram0_dout0[31] , |
| \u_riscv_top.sram0_dout0[30] , |
| \u_riscv_top.sram0_dout0[29] , |
| \u_riscv_top.sram0_dout0[28] , |
| \u_riscv_top.sram0_dout0[27] , |
| \u_riscv_top.sram0_dout0[26] , |
| \u_riscv_top.sram0_dout0[25] , |
| \u_riscv_top.sram0_dout0[24] , |
| \u_riscv_top.sram0_dout0[23] , |
| \u_riscv_top.sram0_dout0[22] , |
| \u_riscv_top.sram0_dout0[21] , |
| \u_riscv_top.sram0_dout0[20] , |
| \u_riscv_top.sram0_dout0[19] , |
| \u_riscv_top.sram0_dout0[18] , |
| \u_riscv_top.sram0_dout0[17] , |
| \u_riscv_top.sram0_dout0[16] , |
| \u_riscv_top.sram0_dout0[15] , |
| \u_riscv_top.sram0_dout0[14] , |
| \u_riscv_top.sram0_dout0[13] , |
| \u_riscv_top.sram0_dout0[12] , |
| \u_riscv_top.sram0_dout0[11] , |
| \u_riscv_top.sram0_dout0[10] , |
| \u_riscv_top.sram0_dout0[9] , |
| \u_riscv_top.sram0_dout0[8] , |
| \u_riscv_top.sram0_dout0[7] , |
| \u_riscv_top.sram0_dout0[6] , |
| \u_riscv_top.sram0_dout0[5] , |
| \u_riscv_top.sram0_dout0[4] , |
| \u_riscv_top.sram0_dout0[3] , |
| \u_riscv_top.sram0_dout0[2] , |
| \u_riscv_top.sram0_dout0[1] , |
| \u_riscv_top.sram0_dout0[0] }), |
| .sram0_dout1({\u_riscv_top.sram0_dout1[31] , |
| \u_riscv_top.sram0_dout1[30] , |
| \u_riscv_top.sram0_dout1[29] , |
| \u_riscv_top.sram0_dout1[28] , |
| \u_riscv_top.sram0_dout1[27] , |
| \u_riscv_top.sram0_dout1[26] , |
| \u_riscv_top.sram0_dout1[25] , |
| \u_riscv_top.sram0_dout1[24] , |
| \u_riscv_top.sram0_dout1[23] , |
| \u_riscv_top.sram0_dout1[22] , |
| \u_riscv_top.sram0_dout1[21] , |
| \u_riscv_top.sram0_dout1[20] , |
| \u_riscv_top.sram0_dout1[19] , |
| \u_riscv_top.sram0_dout1[18] , |
| \u_riscv_top.sram0_dout1[17] , |
| \u_riscv_top.sram0_dout1[16] , |
| \u_riscv_top.sram0_dout1[15] , |
| \u_riscv_top.sram0_dout1[14] , |
| \u_riscv_top.sram0_dout1[13] , |
| \u_riscv_top.sram0_dout1[12] , |
| \u_riscv_top.sram0_dout1[11] , |
| \u_riscv_top.sram0_dout1[10] , |
| \u_riscv_top.sram0_dout1[9] , |
| \u_riscv_top.sram0_dout1[8] , |
| \u_riscv_top.sram0_dout1[7] , |
| \u_riscv_top.sram0_dout1[6] , |
| \u_riscv_top.sram0_dout1[5] , |
| \u_riscv_top.sram0_dout1[4] , |
| \u_riscv_top.sram0_dout1[3] , |
| \u_riscv_top.sram0_dout1[2] , |
| \u_riscv_top.sram0_dout1[1] , |
| \u_riscv_top.sram0_dout1[0] }), |
| .sram0_wmask0({\u_riscv_top.sram0_wmask0[3] , |
| \u_riscv_top.sram0_wmask0[2] , |
| \u_riscv_top.sram0_wmask0[1] , |
| \u_riscv_top.sram0_wmask0[0] })); |
| ycr_intf \u_riscv_top.u_intf (.cfg_bypass_dcache(\cfg_riscv_ctrl[11] ), |
| .cfg_bypass_icache(\cfg_riscv_ctrl[10] ), |
| .cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ), |
| .cfg_dcache_pfet_dis(\cfg_riscv_ctrl[6] ), |
| .cfg_icache_ntag_pfet_dis(\cfg_riscv_ctrl[5] ), |
| .cfg_icache_pfet_dis(\cfg_riscv_ctrl[4] ), |
| .core_clk(\u_riscv_top.core_clk_intf_skew ), |
| .core_clk_int(\u_riscv_top.core_clk_int[0] ), |
| .core_clk_skew(\u_riscv_top.core_clk_intf_skew ), |
| .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ), |
| .core_dcache_req(\u_riscv_top.core_dcache_req ), |
| .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ), |
| .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ), |
| .core_dmem_req(\u_riscv_top.core_dmem_req ), |
| .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ), |
| .core_icache_cmd(\u_riscv_top.core_icache_cmd ), |
| .core_icache_req(\u_riscv_top.core_icache_req ), |
| .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ), |
| .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ), |
| .dcache_mem_clk0(\u_riscv_top.dcache_mem_clk0 ), |
| .dcache_mem_clk1(\u_riscv_top.dcache_mem_clk1 ), |
| .dcache_mem_csb0(\u_riscv_top.dcache_mem_csb0 ), |
| .dcache_mem_csb1(\u_riscv_top.dcache_mem_csb1 ), |
| .dcache_mem_web0(\u_riscv_top.dcache_mem_web0 ), |
| .icache_mem_clk0(\u_riscv_top.icache_mem_clk0 ), |
| .icache_mem_clk1(\u_riscv_top.icache_mem_clk1 ), |
| .icache_mem_csb0(\u_riscv_top.icache_mem_csb0 ), |
| .icache_mem_csb1(\u_riscv_top.icache_mem_csb1 ), |
| .icache_mem_web0(\u_riscv_top.icache_mem_web0 ), |
| .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wb_clk(\u_riscv_top.wb_clk ), |
| .wb_dcache_ack_i(\u_riscv_top.wb_dcache_ack_i ), |
| .wb_dcache_bry_o(\u_riscv_top.wb_dcache_bry_o ), |
| .wb_dcache_err_i(\u_riscv_top.wb_dcache_err_i ), |
| .wb_dcache_lack_i(\u_riscv_top.wb_dcache_lack_i ), |
| .wb_dcache_stb_o(\u_riscv_top.wb_dcache_stb_o ), |
| .wb_dcache_we_o(\u_riscv_top.wb_dcache_we_o ), |
| .wb_icache_ack_i(\u_riscv_top.wb_icache_ack_i ), |
| .wb_icache_bry_o(\u_riscv_top.wb_icache_bry_o ), |
| .wb_icache_err_i(\u_riscv_top.wb_icache_err_i ), |
| .wb_icache_lack_i(\u_riscv_top.wb_icache_lack_i ), |
| .wb_icache_stb_o(\u_riscv_top.wb_icache_stb_o ), |
| .wb_icache_we_o(\u_riscv_top.wb_icache_we_o ), |
| .wb_rst_n(\u_riscv_top.pwrup_rst_n ), |
| .wbd_clk_int(\u_riscv_top.wbd_clk_int ), |
| .wbd_clk_skew(\u_riscv_top.wb_clk ), |
| .wbd_dmem_ack_i(\u_riscv_top.wbd_dmem_ack_i ), |
| .wbd_dmem_bry_o(\u_riscv_top.wbd_dmem_bry_o ), |
| .wbd_dmem_err_i(\u_riscv_top.wbd_dmem_err_i ), |
| .wbd_dmem_lack_i(\u_riscv_top.wbd_dmem_lack_i ), |
| .wbd_dmem_stb_o(\u_riscv_top.wbd_dmem_stb_o ), |
| .wbd_dmem_we_o(\u_riscv_top.wbd_dmem_we_o ), |
| .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_intf[3] , |
| \u_riscv_top.cfg_ccska_riscv_intf[2] , |
| \u_riscv_top.cfg_ccska_riscv_intf[1] , |
| \u_riscv_top.cfg_ccska_riscv_intf[0] }), |
| .cfg_sram_lphase({\cfg_riscv_ctrl[1] , |
| \cfg_riscv_ctrl[0] }), |
| .cfg_wcska({\u_riscv_top.cfg_wcska_riscv_intf[3] , |
| \u_riscv_top.cfg_wcska_riscv_intf[2] , |
| \u_riscv_top.cfg_wcska_riscv_intf[1] , |
| \u_riscv_top.cfg_wcska_riscv_intf[0] }), |
| .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] , |
| \u_riscv_top.core_dcache_addr[30] , |
| \u_riscv_top.core_dcache_addr[29] , |
| \u_riscv_top.core_dcache_addr[28] , |
| \u_riscv_top.core_dcache_addr[27] , |
| \u_riscv_top.core_dcache_addr[26] , |
| \u_riscv_top.core_dcache_addr[25] , |
| \u_riscv_top.core_dcache_addr[24] , |
| \u_riscv_top.core_dcache_addr[23] , |
| \u_riscv_top.core_dcache_addr[22] , |
| \u_riscv_top.core_dcache_addr[21] , |
| \u_riscv_top.core_dcache_addr[20] , |
| \u_riscv_top.core_dcache_addr[19] , |
| \u_riscv_top.core_dcache_addr[18] , |
| \u_riscv_top.core_dcache_addr[17] , |
| \u_riscv_top.core_dcache_addr[16] , |
| \u_riscv_top.core_dcache_addr[15] , |
| \u_riscv_top.core_dcache_addr[14] , |
| \u_riscv_top.core_dcache_addr[13] , |
| \u_riscv_top.core_dcache_addr[12] , |
| \u_riscv_top.core_dcache_addr[11] , |
| \u_riscv_top.core_dcache_addr[10] , |
| \u_riscv_top.core_dcache_addr[9] , |
| \u_riscv_top.core_dcache_addr[8] , |
| \u_riscv_top.core_dcache_addr[7] , |
| \u_riscv_top.core_dcache_addr[6] , |
| \u_riscv_top.core_dcache_addr[5] , |
| \u_riscv_top.core_dcache_addr[4] , |
| \u_riscv_top.core_dcache_addr[3] , |
| \u_riscv_top.core_dcache_addr[2] , |
| \u_riscv_top.core_dcache_addr[1] , |
| \u_riscv_top.core_dcache_addr[0] }), |
| .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] , |
| \u_riscv_top.core_dcache_rdata[30] , |
| \u_riscv_top.core_dcache_rdata[29] , |
| \u_riscv_top.core_dcache_rdata[28] , |
| \u_riscv_top.core_dcache_rdata[27] , |
| \u_riscv_top.core_dcache_rdata[26] , |
| \u_riscv_top.core_dcache_rdata[25] , |
| \u_riscv_top.core_dcache_rdata[24] , |
| \u_riscv_top.core_dcache_rdata[23] , |
| \u_riscv_top.core_dcache_rdata[22] , |
| \u_riscv_top.core_dcache_rdata[21] , |
| \u_riscv_top.core_dcache_rdata[20] , |
| \u_riscv_top.core_dcache_rdata[19] , |
| \u_riscv_top.core_dcache_rdata[18] , |
| \u_riscv_top.core_dcache_rdata[17] , |
| \u_riscv_top.core_dcache_rdata[16] , |
| \u_riscv_top.core_dcache_rdata[15] , |
| \u_riscv_top.core_dcache_rdata[14] , |
| \u_riscv_top.core_dcache_rdata[13] , |
| \u_riscv_top.core_dcache_rdata[12] , |
| \u_riscv_top.core_dcache_rdata[11] , |
| \u_riscv_top.core_dcache_rdata[10] , |
| \u_riscv_top.core_dcache_rdata[9] , |
| \u_riscv_top.core_dcache_rdata[8] , |
| \u_riscv_top.core_dcache_rdata[7] , |
| \u_riscv_top.core_dcache_rdata[6] , |
| \u_riscv_top.core_dcache_rdata[5] , |
| \u_riscv_top.core_dcache_rdata[4] , |
| \u_riscv_top.core_dcache_rdata[3] , |
| \u_riscv_top.core_dcache_rdata[2] , |
| \u_riscv_top.core_dcache_rdata[1] , |
| \u_riscv_top.core_dcache_rdata[0] }), |
| .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] , |
| \u_riscv_top.core_dcache_resp[0] }), |
| .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] , |
| \u_riscv_top.core_dcache_wdata[30] , |
| \u_riscv_top.core_dcache_wdata[29] , |
| \u_riscv_top.core_dcache_wdata[28] , |
| \u_riscv_top.core_dcache_wdata[27] , |
| \u_riscv_top.core_dcache_wdata[26] , |
| \u_riscv_top.core_dcache_wdata[25] , |
| \u_riscv_top.core_dcache_wdata[24] , |
| \u_riscv_top.core_dcache_wdata[23] , |
| \u_riscv_top.core_dcache_wdata[22] , |
| \u_riscv_top.core_dcache_wdata[21] , |
| \u_riscv_top.core_dcache_wdata[20] , |
| \u_riscv_top.core_dcache_wdata[19] , |
| \u_riscv_top.core_dcache_wdata[18] , |
| \u_riscv_top.core_dcache_wdata[17] , |
| \u_riscv_top.core_dcache_wdata[16] , |
| \u_riscv_top.core_dcache_wdata[15] , |
| \u_riscv_top.core_dcache_wdata[14] , |
| \u_riscv_top.core_dcache_wdata[13] , |
| \u_riscv_top.core_dcache_wdata[12] , |
| \u_riscv_top.core_dcache_wdata[11] , |
| \u_riscv_top.core_dcache_wdata[10] , |
| \u_riscv_top.core_dcache_wdata[9] , |
| \u_riscv_top.core_dcache_wdata[8] , |
| \u_riscv_top.core_dcache_wdata[7] , |
| \u_riscv_top.core_dcache_wdata[6] , |
| \u_riscv_top.core_dcache_wdata[5] , |
| \u_riscv_top.core_dcache_wdata[4] , |
| \u_riscv_top.core_dcache_wdata[3] , |
| \u_riscv_top.core_dcache_wdata[2] , |
| \u_riscv_top.core_dcache_wdata[1] , |
| \u_riscv_top.core_dcache_wdata[0] }), |
| .core_dcache_width({\u_riscv_top.core_dcache_width[1] , |
| \u_riscv_top.core_dcache_width[0] }), |
| .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] , |
| \u_riscv_top.core_dmem_addr[30] , |
| \u_riscv_top.core_dmem_addr[29] , |
| \u_riscv_top.core_dmem_addr[28] , |
| \u_riscv_top.core_dmem_addr[27] , |
| \u_riscv_top.core_dmem_addr[26] , |
| \u_riscv_top.core_dmem_addr[25] , |
| \u_riscv_top.core_dmem_addr[24] , |
| \u_riscv_top.core_dmem_addr[23] , |
| \u_riscv_top.core_dmem_addr[22] , |
| \u_riscv_top.core_dmem_addr[21] , |
| \u_riscv_top.core_dmem_addr[20] , |
| \u_riscv_top.core_dmem_addr[19] , |
| \u_riscv_top.core_dmem_addr[18] , |
| \u_riscv_top.core_dmem_addr[17] , |
| \u_riscv_top.core_dmem_addr[16] , |
| \u_riscv_top.core_dmem_addr[15] , |
| \u_riscv_top.core_dmem_addr[14] , |
| \u_riscv_top.core_dmem_addr[13] , |
| \u_riscv_top.core_dmem_addr[12] , |
| \u_riscv_top.core_dmem_addr[11] , |
| \u_riscv_top.core_dmem_addr[10] , |
| \u_riscv_top.core_dmem_addr[9] , |
| \u_riscv_top.core_dmem_addr[8] , |
| \u_riscv_top.core_dmem_addr[7] , |
| \u_riscv_top.core_dmem_addr[6] , |
| \u_riscv_top.core_dmem_addr[5] , |
| \u_riscv_top.core_dmem_addr[4] , |
| \u_riscv_top.core_dmem_addr[3] , |
| \u_riscv_top.core_dmem_addr[2] , |
| \u_riscv_top.core_dmem_addr[1] , |
| \u_riscv_top.core_dmem_addr[0] }), |
| .core_dmem_bl({\u_riscv_top.core_dmem_bl[2] , |
| \u_riscv_top.core_dmem_bl[1] , |
| \u_riscv_top.core_dmem_bl[0] }), |
| .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] , |
| \u_riscv_top.core_dmem_rdata[30] , |
| \u_riscv_top.core_dmem_rdata[29] , |
| \u_riscv_top.core_dmem_rdata[28] , |
| \u_riscv_top.core_dmem_rdata[27] , |
| \u_riscv_top.core_dmem_rdata[26] , |
| \u_riscv_top.core_dmem_rdata[25] , |
| \u_riscv_top.core_dmem_rdata[24] , |
| \u_riscv_top.core_dmem_rdata[23] , |
| \u_riscv_top.core_dmem_rdata[22] , |
| \u_riscv_top.core_dmem_rdata[21] , |
| \u_riscv_top.core_dmem_rdata[20] , |
| \u_riscv_top.core_dmem_rdata[19] , |
| \u_riscv_top.core_dmem_rdata[18] , |
| \u_riscv_top.core_dmem_rdata[17] , |
| \u_riscv_top.core_dmem_rdata[16] , |
| \u_riscv_top.core_dmem_rdata[15] , |
| \u_riscv_top.core_dmem_rdata[14] , |
| \u_riscv_top.core_dmem_rdata[13] , |
| \u_riscv_top.core_dmem_rdata[12] , |
| \u_riscv_top.core_dmem_rdata[11] , |
| \u_riscv_top.core_dmem_rdata[10] , |
| \u_riscv_top.core_dmem_rdata[9] , |
| \u_riscv_top.core_dmem_rdata[8] , |
| \u_riscv_top.core_dmem_rdata[7] , |
| \u_riscv_top.core_dmem_rdata[6] , |
| \u_riscv_top.core_dmem_rdata[5] , |
| \u_riscv_top.core_dmem_rdata[4] , |
| \u_riscv_top.core_dmem_rdata[3] , |
| \u_riscv_top.core_dmem_rdata[2] , |
| \u_riscv_top.core_dmem_rdata[1] , |
| \u_riscv_top.core_dmem_rdata[0] }), |
| .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] , |
| \u_riscv_top.core_dmem_resp[0] }), |
| .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] , |
| \u_riscv_top.core_dmem_wdata[30] , |
| \u_riscv_top.core_dmem_wdata[29] , |
| \u_riscv_top.core_dmem_wdata[28] , |
| \u_riscv_top.core_dmem_wdata[27] , |
| \u_riscv_top.core_dmem_wdata[26] , |
| \u_riscv_top.core_dmem_wdata[25] , |
| \u_riscv_top.core_dmem_wdata[24] , |
| \u_riscv_top.core_dmem_wdata[23] , |
| \u_riscv_top.core_dmem_wdata[22] , |
| \u_riscv_top.core_dmem_wdata[21] , |
| \u_riscv_top.core_dmem_wdata[20] , |
| \u_riscv_top.core_dmem_wdata[19] , |
| \u_riscv_top.core_dmem_wdata[18] , |
| \u_riscv_top.core_dmem_wdata[17] , |
| \u_riscv_top.core_dmem_wdata[16] , |
| \u_riscv_top.core_dmem_wdata[15] , |
| \u_riscv_top.core_dmem_wdata[14] , |
| \u_riscv_top.core_dmem_wdata[13] , |
| \u_riscv_top.core_dmem_wdata[12] , |
| \u_riscv_top.core_dmem_wdata[11] , |
| \u_riscv_top.core_dmem_wdata[10] , |
| \u_riscv_top.core_dmem_wdata[9] , |
| \u_riscv_top.core_dmem_wdata[8] , |
| \u_riscv_top.core_dmem_wdata[7] , |
| \u_riscv_top.core_dmem_wdata[6] , |
| \u_riscv_top.core_dmem_wdata[5] , |
| \u_riscv_top.core_dmem_wdata[4] , |
| \u_riscv_top.core_dmem_wdata[3] , |
| \u_riscv_top.core_dmem_wdata[2] , |
| \u_riscv_top.core_dmem_wdata[1] , |
| \u_riscv_top.core_dmem_wdata[0] }), |
| .core_dmem_width({\u_riscv_top.core_dmem_width[1] , |
| \u_riscv_top.core_dmem_width[0] }), |
| .core_icache_addr({\u_riscv_top.core_icache_addr[31] , |
| \u_riscv_top.core_icache_addr[30] , |
| \u_riscv_top.core_icache_addr[29] , |
| \u_riscv_top.core_icache_addr[28] , |
| \u_riscv_top.core_icache_addr[27] , |
| \u_riscv_top.core_icache_addr[26] , |
| \u_riscv_top.core_icache_addr[25] , |
| \u_riscv_top.core_icache_addr[24] , |
| \u_riscv_top.core_icache_addr[23] , |
| \u_riscv_top.core_icache_addr[22] , |
| \u_riscv_top.core_icache_addr[21] , |
| \u_riscv_top.core_icache_addr[20] , |
| \u_riscv_top.core_icache_addr[19] , |
| \u_riscv_top.core_icache_addr[18] , |
| \u_riscv_top.core_icache_addr[17] , |
| \u_riscv_top.core_icache_addr[16] , |
| \u_riscv_top.core_icache_addr[15] , |
| \u_riscv_top.core_icache_addr[14] , |
| \u_riscv_top.core_icache_addr[13] , |
| \u_riscv_top.core_icache_addr[12] , |
| \u_riscv_top.core_icache_addr[11] , |
| \u_riscv_top.core_icache_addr[10] , |
| \u_riscv_top.core_icache_addr[9] , |
| \u_riscv_top.core_icache_addr[8] , |
| \u_riscv_top.core_icache_addr[7] , |
| \u_riscv_top.core_icache_addr[6] , |
| \u_riscv_top.core_icache_addr[5] , |
| \u_riscv_top.core_icache_addr[4] , |
| \u_riscv_top.core_icache_addr[3] , |
| \u_riscv_top.core_icache_addr[2] , |
| \u_riscv_top.core_icache_addr[1] , |
| \u_riscv_top.core_icache_addr[0] }), |
| .core_icache_bl({\u_riscv_top.core_icache_bl[2] , |
| \u_riscv_top.core_icache_bl[1] , |
| \u_riscv_top.core_icache_bl[0] }), |
| .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] , |
| \u_riscv_top.core_icache_rdata[30] , |
| \u_riscv_top.core_icache_rdata[29] , |
| \u_riscv_top.core_icache_rdata[28] , |
| \u_riscv_top.core_icache_rdata[27] , |
| \u_riscv_top.core_icache_rdata[26] , |
| \u_riscv_top.core_icache_rdata[25] , |
| \u_riscv_top.core_icache_rdata[24] , |
| \u_riscv_top.core_icache_rdata[23] , |
| \u_riscv_top.core_icache_rdata[22] , |
| \u_riscv_top.core_icache_rdata[21] , |
| \u_riscv_top.core_icache_rdata[20] , |
| \u_riscv_top.core_icache_rdata[19] , |
| \u_riscv_top.core_icache_rdata[18] , |
| \u_riscv_top.core_icache_rdata[17] , |
| \u_riscv_top.core_icache_rdata[16] , |
| \u_riscv_top.core_icache_rdata[15] , |
| \u_riscv_top.core_icache_rdata[14] , |
| \u_riscv_top.core_icache_rdata[13] , |
| \u_riscv_top.core_icache_rdata[12] , |
| \u_riscv_top.core_icache_rdata[11] , |
| \u_riscv_top.core_icache_rdata[10] , |
| \u_riscv_top.core_icache_rdata[9] , |
| \u_riscv_top.core_icache_rdata[8] , |
| \u_riscv_top.core_icache_rdata[7] , |
| \u_riscv_top.core_icache_rdata[6] , |
| \u_riscv_top.core_icache_rdata[5] , |
| \u_riscv_top.core_icache_rdata[4] , |
| \u_riscv_top.core_icache_rdata[3] , |
| \u_riscv_top.core_icache_rdata[2] , |
| \u_riscv_top.core_icache_rdata[1] , |
| \u_riscv_top.core_icache_rdata[0] }), |
| .core_icache_resp({\u_riscv_top.core_icache_resp[1] , |
| \u_riscv_top.core_icache_resp[0] }), |
| .core_icache_width({\u_riscv_top.core_icache_width[1] , |
| \u_riscv_top.core_icache_width[0] }), |
| .dcache_mem_addr0({\u_riscv_top.dcache_mem_addr0[8] , |
| \u_riscv_top.dcache_mem_addr0[7] , |
| \u_riscv_top.dcache_mem_addr0[6] , |
| \u_riscv_top.dcache_mem_addr0[5] , |
| \u_riscv_top.dcache_mem_addr0[4] , |
| \u_riscv_top.dcache_mem_addr0[3] , |
| \u_riscv_top.dcache_mem_addr0[2] , |
| \u_riscv_top.dcache_mem_addr0[1] , |
| \u_riscv_top.dcache_mem_addr0[0] }), |
| .dcache_mem_addr1({\u_riscv_top.dcache_mem_addr1[8] , |
| \u_riscv_top.dcache_mem_addr1[7] , |
| \u_riscv_top.dcache_mem_addr1[6] , |
| \u_riscv_top.dcache_mem_addr1[5] , |
| \u_riscv_top.dcache_mem_addr1[4] , |
| \u_riscv_top.dcache_mem_addr1[3] , |
| \u_riscv_top.dcache_mem_addr1[2] , |
| \u_riscv_top.dcache_mem_addr1[1] , |
| \u_riscv_top.dcache_mem_addr1[0] }), |
| .dcache_mem_din0({\u_riscv_top.dcache_mem_din0[31] , |
| \u_riscv_top.dcache_mem_din0[30] , |
| \u_riscv_top.dcache_mem_din0[29] , |
| \u_riscv_top.dcache_mem_din0[28] , |
| \u_riscv_top.dcache_mem_din0[27] , |
| \u_riscv_top.dcache_mem_din0[26] , |
| \u_riscv_top.dcache_mem_din0[25] , |
| \u_riscv_top.dcache_mem_din0[24] , |
| \u_riscv_top.dcache_mem_din0[23] , |
| \u_riscv_top.dcache_mem_din0[22] , |
| \u_riscv_top.dcache_mem_din0[21] , |
| \u_riscv_top.dcache_mem_din0[20] , |
| \u_riscv_top.dcache_mem_din0[19] , |
| \u_riscv_top.dcache_mem_din0[18] , |
| \u_riscv_top.dcache_mem_din0[17] , |
| \u_riscv_top.dcache_mem_din0[16] , |
| \u_riscv_top.dcache_mem_din0[15] , |
| \u_riscv_top.dcache_mem_din0[14] , |
| \u_riscv_top.dcache_mem_din0[13] , |
| \u_riscv_top.dcache_mem_din0[12] , |
| \u_riscv_top.dcache_mem_din0[11] , |
| \u_riscv_top.dcache_mem_din0[10] , |
| \u_riscv_top.dcache_mem_din0[9] , |
| \u_riscv_top.dcache_mem_din0[8] , |
| \u_riscv_top.dcache_mem_din0[7] , |
| \u_riscv_top.dcache_mem_din0[6] , |
| \u_riscv_top.dcache_mem_din0[5] , |
| \u_riscv_top.dcache_mem_din0[4] , |
| \u_riscv_top.dcache_mem_din0[3] , |
| \u_riscv_top.dcache_mem_din0[2] , |
| \u_riscv_top.dcache_mem_din0[1] , |
| \u_riscv_top.dcache_mem_din0[0] }), |
| .dcache_mem_dout0({\u_riscv_top.dcache_mem_dout0[31] , |
| \u_riscv_top.dcache_mem_dout0[30] , |
| \u_riscv_top.dcache_mem_dout0[29] , |
| \u_riscv_top.dcache_mem_dout0[28] , |
| \u_riscv_top.dcache_mem_dout0[27] , |
| \u_riscv_top.dcache_mem_dout0[26] , |
| \u_riscv_top.dcache_mem_dout0[25] , |
| \u_riscv_top.dcache_mem_dout0[24] , |
| \u_riscv_top.dcache_mem_dout0[23] , |
| \u_riscv_top.dcache_mem_dout0[22] , |
| \u_riscv_top.dcache_mem_dout0[21] , |
| \u_riscv_top.dcache_mem_dout0[20] , |
| \u_riscv_top.dcache_mem_dout0[19] , |
| \u_riscv_top.dcache_mem_dout0[18] , |
| \u_riscv_top.dcache_mem_dout0[17] , |
| \u_riscv_top.dcache_mem_dout0[16] , |
| \u_riscv_top.dcache_mem_dout0[15] , |
| \u_riscv_top.dcache_mem_dout0[14] , |
| \u_riscv_top.dcache_mem_dout0[13] , |
| \u_riscv_top.dcache_mem_dout0[12] , |
| \u_riscv_top.dcache_mem_dout0[11] , |
| \u_riscv_top.dcache_mem_dout0[10] , |
| \u_riscv_top.dcache_mem_dout0[9] , |
| \u_riscv_top.dcache_mem_dout0[8] , |
| \u_riscv_top.dcache_mem_dout0[7] , |
| \u_riscv_top.dcache_mem_dout0[6] , |
| \u_riscv_top.dcache_mem_dout0[5] , |
| \u_riscv_top.dcache_mem_dout0[4] , |
| \u_riscv_top.dcache_mem_dout0[3] , |
| \u_riscv_top.dcache_mem_dout0[2] , |
| \u_riscv_top.dcache_mem_dout0[1] , |
| \u_riscv_top.dcache_mem_dout0[0] }), |
| .dcache_mem_dout1({\u_riscv_top.dcache_mem_dout1[31] , |
| \u_riscv_top.dcache_mem_dout1[30] , |
| \u_riscv_top.dcache_mem_dout1[29] , |
| \u_riscv_top.dcache_mem_dout1[28] , |
| \u_riscv_top.dcache_mem_dout1[27] , |
| \u_riscv_top.dcache_mem_dout1[26] , |
| \u_riscv_top.dcache_mem_dout1[25] , |
| \u_riscv_top.dcache_mem_dout1[24] , |
| \u_riscv_top.dcache_mem_dout1[23] , |
| \u_riscv_top.dcache_mem_dout1[22] , |
| \u_riscv_top.dcache_mem_dout1[21] , |
| \u_riscv_top.dcache_mem_dout1[20] , |
| \u_riscv_top.dcache_mem_dout1[19] , |
| \u_riscv_top.dcache_mem_dout1[18] , |
| \u_riscv_top.dcache_mem_dout1[17] , |
| \u_riscv_top.dcache_mem_dout1[16] , |
| \u_riscv_top.dcache_mem_dout1[15] , |
| \u_riscv_top.dcache_mem_dout1[14] , |
| \u_riscv_top.dcache_mem_dout1[13] , |
| \u_riscv_top.dcache_mem_dout1[12] , |
| \u_riscv_top.dcache_mem_dout1[11] , |
| \u_riscv_top.dcache_mem_dout1[10] , |
| \u_riscv_top.dcache_mem_dout1[9] , |
| \u_riscv_top.dcache_mem_dout1[8] , |
| \u_riscv_top.dcache_mem_dout1[7] , |
| \u_riscv_top.dcache_mem_dout1[6] , |
| \u_riscv_top.dcache_mem_dout1[5] , |
| \u_riscv_top.dcache_mem_dout1[4] , |
| \u_riscv_top.dcache_mem_dout1[3] , |
| \u_riscv_top.dcache_mem_dout1[2] , |
| \u_riscv_top.dcache_mem_dout1[1] , |
| \u_riscv_top.dcache_mem_dout1[0] }), |
| .dcache_mem_wmask0({\u_riscv_top.dcache_mem_wmask0[3] , |
| \u_riscv_top.dcache_mem_wmask0[2] , |
| \u_riscv_top.dcache_mem_wmask0[1] , |
| \u_riscv_top.dcache_mem_wmask0[0] }), |
| .icache_mem_addr0({\u_riscv_top.icache_mem_addr0[8] , |
| \u_riscv_top.icache_mem_addr0[7] , |
| \u_riscv_top.icache_mem_addr0[6] , |
| \u_riscv_top.icache_mem_addr0[5] , |
| \u_riscv_top.icache_mem_addr0[4] , |
| \u_riscv_top.icache_mem_addr0[3] , |
| \u_riscv_top.icache_mem_addr0[2] , |
| \u_riscv_top.icache_mem_addr0[1] , |
| \u_riscv_top.icache_mem_addr0[0] }), |
| .icache_mem_addr1({\u_riscv_top.icache_mem_addr1[8] , |
| \u_riscv_top.icache_mem_addr1[7] , |
| \u_riscv_top.icache_mem_addr1[6] , |
| \u_riscv_top.icache_mem_addr1[5] , |
| \u_riscv_top.icache_mem_addr1[4] , |
| \u_riscv_top.icache_mem_addr1[3] , |
| \u_riscv_top.icache_mem_addr1[2] , |
| \u_riscv_top.icache_mem_addr1[1] , |
| \u_riscv_top.icache_mem_addr1[0] }), |
| .icache_mem_din0({\u_riscv_top.icache_mem_din0[31] , |
| \u_riscv_top.icache_mem_din0[30] , |
| \u_riscv_top.icache_mem_din0[29] , |
| \u_riscv_top.icache_mem_din0[28] , |
| \u_riscv_top.icache_mem_din0[27] , |
| \u_riscv_top.icache_mem_din0[26] , |
| \u_riscv_top.icache_mem_din0[25] , |
| \u_riscv_top.icache_mem_din0[24] , |
| \u_riscv_top.icache_mem_din0[23] , |
| \u_riscv_top.icache_mem_din0[22] , |
| \u_riscv_top.icache_mem_din0[21] , |
| \u_riscv_top.icache_mem_din0[20] , |
| \u_riscv_top.icache_mem_din0[19] , |
| \u_riscv_top.icache_mem_din0[18] , |
| \u_riscv_top.icache_mem_din0[17] , |
| \u_riscv_top.icache_mem_din0[16] , |
| \u_riscv_top.icache_mem_din0[15] , |
| \u_riscv_top.icache_mem_din0[14] , |
| \u_riscv_top.icache_mem_din0[13] , |
| \u_riscv_top.icache_mem_din0[12] , |
| \u_riscv_top.icache_mem_din0[11] , |
| \u_riscv_top.icache_mem_din0[10] , |
| \u_riscv_top.icache_mem_din0[9] , |
| \u_riscv_top.icache_mem_din0[8] , |
| \u_riscv_top.icache_mem_din0[7] , |
| \u_riscv_top.icache_mem_din0[6] , |
| \u_riscv_top.icache_mem_din0[5] , |
| \u_riscv_top.icache_mem_din0[4] , |
| \u_riscv_top.icache_mem_din0[3] , |
| \u_riscv_top.icache_mem_din0[2] , |
| \u_riscv_top.icache_mem_din0[1] , |
| \u_riscv_top.icache_mem_din0[0] }), |
| .icache_mem_dout1({\u_riscv_top.icache_mem_dout1[31] , |
| \u_riscv_top.icache_mem_dout1[30] , |
| \u_riscv_top.icache_mem_dout1[29] , |
| \u_riscv_top.icache_mem_dout1[28] , |
| \u_riscv_top.icache_mem_dout1[27] , |
| \u_riscv_top.icache_mem_dout1[26] , |
| \u_riscv_top.icache_mem_dout1[25] , |
| \u_riscv_top.icache_mem_dout1[24] , |
| \u_riscv_top.icache_mem_dout1[23] , |
| \u_riscv_top.icache_mem_dout1[22] , |
| \u_riscv_top.icache_mem_dout1[21] , |
| \u_riscv_top.icache_mem_dout1[20] , |
| \u_riscv_top.icache_mem_dout1[19] , |
| \u_riscv_top.icache_mem_dout1[18] , |
| \u_riscv_top.icache_mem_dout1[17] , |
| \u_riscv_top.icache_mem_dout1[16] , |
| \u_riscv_top.icache_mem_dout1[15] , |
| \u_riscv_top.icache_mem_dout1[14] , |
| \u_riscv_top.icache_mem_dout1[13] , |
| \u_riscv_top.icache_mem_dout1[12] , |
| \u_riscv_top.icache_mem_dout1[11] , |
| \u_riscv_top.icache_mem_dout1[10] , |
| \u_riscv_top.icache_mem_dout1[9] , |
| \u_riscv_top.icache_mem_dout1[8] , |
| \u_riscv_top.icache_mem_dout1[7] , |
| \u_riscv_top.icache_mem_dout1[6] , |
| \u_riscv_top.icache_mem_dout1[5] , |
| \u_riscv_top.icache_mem_dout1[4] , |
| \u_riscv_top.icache_mem_dout1[3] , |
| \u_riscv_top.icache_mem_dout1[2] , |
| \u_riscv_top.icache_mem_dout1[1] , |
| \u_riscv_top.icache_mem_dout1[0] }), |
| .icache_mem_wmask0({\u_riscv_top.icache_mem_wmask0[3] , |
| \u_riscv_top.icache_mem_wmask0[2] , |
| \u_riscv_top.icache_mem_wmask0[1] , |
| \u_riscv_top.icache_mem_wmask0[0] }), |
| .wb_dcache_adr_o({\u_riscv_top.wb_dcache_adr_o[31] , |
| \u_riscv_top.wb_dcache_adr_o[30] , |
| \u_riscv_top.wb_dcache_adr_o[29] , |
| \u_riscv_top.wb_dcache_adr_o[28] , |
| \u_riscv_top.wb_dcache_adr_o[27] , |
| \u_riscv_top.wb_dcache_adr_o[26] , |
| \u_riscv_top.wb_dcache_adr_o[25] , |
| \u_riscv_top.wb_dcache_adr_o[24] , |
| \u_riscv_top.wb_dcache_adr_o[23] , |
| \u_riscv_top.wb_dcache_adr_o[22] , |
| \u_riscv_top.wb_dcache_adr_o[21] , |
| \u_riscv_top.wb_dcache_adr_o[20] , |
| \u_riscv_top.wb_dcache_adr_o[19] , |
| \u_riscv_top.wb_dcache_adr_o[18] , |
| \u_riscv_top.wb_dcache_adr_o[17] , |
| \u_riscv_top.wb_dcache_adr_o[16] , |
| \u_riscv_top.wb_dcache_adr_o[15] , |
| \u_riscv_top.wb_dcache_adr_o[14] , |
| \u_riscv_top.wb_dcache_adr_o[13] , |
| \u_riscv_top.wb_dcache_adr_o[12] , |
| \u_riscv_top.wb_dcache_adr_o[11] , |
| \u_riscv_top.wb_dcache_adr_o[10] , |
| \u_riscv_top.wb_dcache_adr_o[9] , |
| \u_riscv_top.wb_dcache_adr_o[8] , |
| \u_riscv_top.wb_dcache_adr_o[7] , |
| \u_riscv_top.wb_dcache_adr_o[6] , |
| \u_riscv_top.wb_dcache_adr_o[5] , |
| \u_riscv_top.wb_dcache_adr_o[4] , |
| \u_riscv_top.wb_dcache_adr_o[3] , |
| \u_riscv_top.wb_dcache_adr_o[2] , |
| \u_riscv_top.wb_dcache_adr_o[1] , |
| \u_riscv_top.wb_dcache_adr_o[0] }), |
| .wb_dcache_bl_o({\u_riscv_top.wb_dcache_bl_o[9] , |
| \u_riscv_top.wb_dcache_bl_o[8] , |
| \u_riscv_top.wb_dcache_bl_o[7] , |
| \u_riscv_top.wb_dcache_bl_o[6] , |
| \u_riscv_top.wb_dcache_bl_o[5] , |
| \u_riscv_top.wb_dcache_bl_o[4] , |
| \u_riscv_top.wb_dcache_bl_o[3] , |
| \u_riscv_top.wb_dcache_bl_o[2] , |
| \u_riscv_top.wb_dcache_bl_o[1] , |
| \u_riscv_top.wb_dcache_bl_o[0] }), |
| .wb_dcache_dat_i({\u_riscv_top.wb_dcache_dat_i[31] , |
| \u_riscv_top.wb_dcache_dat_i[30] , |
| \u_riscv_top.wb_dcache_dat_i[29] , |
| \u_riscv_top.wb_dcache_dat_i[28] , |
| \u_riscv_top.wb_dcache_dat_i[27] , |
| \u_riscv_top.wb_dcache_dat_i[26] , |
| \u_riscv_top.wb_dcache_dat_i[25] , |
| \u_riscv_top.wb_dcache_dat_i[24] , |
| \u_riscv_top.wb_dcache_dat_i[23] , |
| \u_riscv_top.wb_dcache_dat_i[22] , |
| \u_riscv_top.wb_dcache_dat_i[21] , |
| \u_riscv_top.wb_dcache_dat_i[20] , |
| \u_riscv_top.wb_dcache_dat_i[19] , |
| \u_riscv_top.wb_dcache_dat_i[18] , |
| \u_riscv_top.wb_dcache_dat_i[17] , |
| \u_riscv_top.wb_dcache_dat_i[16] , |
| \u_riscv_top.wb_dcache_dat_i[15] , |
| \u_riscv_top.wb_dcache_dat_i[14] , |
| \u_riscv_top.wb_dcache_dat_i[13] , |
| \u_riscv_top.wb_dcache_dat_i[12] , |
| \u_riscv_top.wb_dcache_dat_i[11] , |
| \u_riscv_top.wb_dcache_dat_i[10] , |
| \u_riscv_top.wb_dcache_dat_i[9] , |
| \u_riscv_top.wb_dcache_dat_i[8] , |
| \u_riscv_top.wb_dcache_dat_i[7] , |
| \u_riscv_top.wb_dcache_dat_i[6] , |
| \u_riscv_top.wb_dcache_dat_i[5] , |
| \u_riscv_top.wb_dcache_dat_i[4] , |
| \u_riscv_top.wb_dcache_dat_i[3] , |
| \u_riscv_top.wb_dcache_dat_i[2] , |
| \u_riscv_top.wb_dcache_dat_i[1] , |
| \u_riscv_top.wb_dcache_dat_i[0] }), |
| .wb_dcache_dat_o({\u_riscv_top.wb_dcache_dat_o[31] , |
| \u_riscv_top.wb_dcache_dat_o[30] , |
| \u_riscv_top.wb_dcache_dat_o[29] , |
| \u_riscv_top.wb_dcache_dat_o[28] , |
| \u_riscv_top.wb_dcache_dat_o[27] , |
| \u_riscv_top.wb_dcache_dat_o[26] , |
| \u_riscv_top.wb_dcache_dat_o[25] , |
| \u_riscv_top.wb_dcache_dat_o[24] , |
| \u_riscv_top.wb_dcache_dat_o[23] , |
| \u_riscv_top.wb_dcache_dat_o[22] , |
| \u_riscv_top.wb_dcache_dat_o[21] , |
| \u_riscv_top.wb_dcache_dat_o[20] , |
| \u_riscv_top.wb_dcache_dat_o[19] , |
| \u_riscv_top.wb_dcache_dat_o[18] , |
| \u_riscv_top.wb_dcache_dat_o[17] , |
| \u_riscv_top.wb_dcache_dat_o[16] , |
| \u_riscv_top.wb_dcache_dat_o[15] , |
| \u_riscv_top.wb_dcache_dat_o[14] , |
| \u_riscv_top.wb_dcache_dat_o[13] , |
| \u_riscv_top.wb_dcache_dat_o[12] , |
| \u_riscv_top.wb_dcache_dat_o[11] , |
| \u_riscv_top.wb_dcache_dat_o[10] , |
| \u_riscv_top.wb_dcache_dat_o[9] , |
| \u_riscv_top.wb_dcache_dat_o[8] , |
| \u_riscv_top.wb_dcache_dat_o[7] , |
| \u_riscv_top.wb_dcache_dat_o[6] , |
| \u_riscv_top.wb_dcache_dat_o[5] , |
| \u_riscv_top.wb_dcache_dat_o[4] , |
| \u_riscv_top.wb_dcache_dat_o[3] , |
| \u_riscv_top.wb_dcache_dat_o[2] , |
| \u_riscv_top.wb_dcache_dat_o[1] , |
| \u_riscv_top.wb_dcache_dat_o[0] }), |
| .wb_dcache_sel_o({\u_riscv_top.wb_dcache_sel_o[3] , |
| \u_riscv_top.wb_dcache_sel_o[2] , |
| \u_riscv_top.wb_dcache_sel_o[1] , |
| \u_riscv_top.wb_dcache_sel_o[0] }), |
| .wb_icache_adr_o({\u_riscv_top.wb_icache_adr_o[31] , |
| \u_riscv_top.wb_icache_adr_o[30] , |
| \u_riscv_top.wb_icache_adr_o[29] , |
| \u_riscv_top.wb_icache_adr_o[28] , |
| \u_riscv_top.wb_icache_adr_o[27] , |
| \u_riscv_top.wb_icache_adr_o[26] , |
| \u_riscv_top.wb_icache_adr_o[25] , |
| \u_riscv_top.wb_icache_adr_o[24] , |
| \u_riscv_top.wb_icache_adr_o[23] , |
| \u_riscv_top.wb_icache_adr_o[22] , |
| \u_riscv_top.wb_icache_adr_o[21] , |
| \u_riscv_top.wb_icache_adr_o[20] , |
| \u_riscv_top.wb_icache_adr_o[19] , |
| \u_riscv_top.wb_icache_adr_o[18] , |
| \u_riscv_top.wb_icache_adr_o[17] , |
| \u_riscv_top.wb_icache_adr_o[16] , |
| \u_riscv_top.wb_icache_adr_o[15] , |
| \u_riscv_top.wb_icache_adr_o[14] , |
| \u_riscv_top.wb_icache_adr_o[13] , |
| \u_riscv_top.wb_icache_adr_o[12] , |
| \u_riscv_top.wb_icache_adr_o[11] , |
| \u_riscv_top.wb_icache_adr_o[10] , |
| \u_riscv_top.wb_icache_adr_o[9] , |
| \u_riscv_top.wb_icache_adr_o[8] , |
| \u_riscv_top.wb_icache_adr_o[7] , |
| \u_riscv_top.wb_icache_adr_o[6] , |
| \u_riscv_top.wb_icache_adr_o[5] , |
| \u_riscv_top.wb_icache_adr_o[4] , |
| \u_riscv_top.wb_icache_adr_o[3] , |
| \u_riscv_top.wb_icache_adr_o[2] , |
| \u_riscv_top.wb_icache_adr_o[1] , |
| \u_riscv_top.wb_icache_adr_o[0] }), |
| .wb_icache_bl_o({\u_riscv_top.wb_icache_bl_o[9] , |
| \u_riscv_top.wb_icache_bl_o[8] , |
| \u_riscv_top.wb_icache_bl_o[7] , |
| \u_riscv_top.wb_icache_bl_o[6] , |
| \u_riscv_top.wb_icache_bl_o[5] , |
| \u_riscv_top.wb_icache_bl_o[4] , |
| \u_riscv_top.wb_icache_bl_o[3] , |
| \u_riscv_top.wb_icache_bl_o[2] , |
| \u_riscv_top.wb_icache_bl_o[1] , |
| \u_riscv_top.wb_icache_bl_o[0] }), |
| .wb_icache_dat_i({\u_riscv_top.wb_icache_dat_i[31] , |
| \u_riscv_top.wb_icache_dat_i[30] , |
| \u_riscv_top.wb_icache_dat_i[29] , |
| \u_riscv_top.wb_icache_dat_i[28] , |
| \u_riscv_top.wb_icache_dat_i[27] , |
| \u_riscv_top.wb_icache_dat_i[26] , |
| \u_riscv_top.wb_icache_dat_i[25] , |
| \u_riscv_top.wb_icache_dat_i[24] , |
| \u_riscv_top.wb_icache_dat_i[23] , |
| \u_riscv_top.wb_icache_dat_i[22] , |
| \u_riscv_top.wb_icache_dat_i[21] , |
| \u_riscv_top.wb_icache_dat_i[20] , |
| \u_riscv_top.wb_icache_dat_i[19] , |
| \u_riscv_top.wb_icache_dat_i[18] , |
| \u_riscv_top.wb_icache_dat_i[17] , |
| \u_riscv_top.wb_icache_dat_i[16] , |
| \u_riscv_top.wb_icache_dat_i[15] , |
| \u_riscv_top.wb_icache_dat_i[14] , |
| \u_riscv_top.wb_icache_dat_i[13] , |
| \u_riscv_top.wb_icache_dat_i[12] , |
| \u_riscv_top.wb_icache_dat_i[11] , |
| \u_riscv_top.wb_icache_dat_i[10] , |
| \u_riscv_top.wb_icache_dat_i[9] , |
| \u_riscv_top.wb_icache_dat_i[8] , |
| \u_riscv_top.wb_icache_dat_i[7] , |
| \u_riscv_top.wb_icache_dat_i[6] , |
| \u_riscv_top.wb_icache_dat_i[5] , |
| \u_riscv_top.wb_icache_dat_i[4] , |
| \u_riscv_top.wb_icache_dat_i[3] , |
| \u_riscv_top.wb_icache_dat_i[2] , |
| \u_riscv_top.wb_icache_dat_i[1] , |
| \u_riscv_top.wb_icache_dat_i[0] }), |
| .wb_icache_sel_o({\u_riscv_top.wb_icache_sel_o[3] , |
| \u_riscv_top.wb_icache_sel_o[2] , |
| \u_riscv_top.wb_icache_sel_o[1] , |
| \u_riscv_top.wb_icache_sel_o[0] }), |
| .wbd_dmem_adr_o({\u_riscv_top.wbd_dmem_adr_o[31] , |
| \u_riscv_top.wbd_dmem_adr_o[30] , |
| \u_riscv_top.wbd_dmem_adr_o[29] , |
| \u_riscv_top.wbd_dmem_adr_o[28] , |
| \u_riscv_top.wbd_dmem_adr_o[27] , |
| \u_riscv_top.wbd_dmem_adr_o[26] , |
| \u_riscv_top.wbd_dmem_adr_o[25] , |
| \u_riscv_top.wbd_dmem_adr_o[24] , |
| \u_riscv_top.wbd_dmem_adr_o[23] , |
| \u_riscv_top.wbd_dmem_adr_o[22] , |
| \u_riscv_top.wbd_dmem_adr_o[21] , |
| \u_riscv_top.wbd_dmem_adr_o[20] , |
| \u_riscv_top.wbd_dmem_adr_o[19] , |
| \u_riscv_top.wbd_dmem_adr_o[18] , |
| \u_riscv_top.wbd_dmem_adr_o[17] , |
| \u_riscv_top.wbd_dmem_adr_o[16] , |
| \u_riscv_top.wbd_dmem_adr_o[15] , |
| \u_riscv_top.wbd_dmem_adr_o[14] , |
| \u_riscv_top.wbd_dmem_adr_o[13] , |
| \u_riscv_top.wbd_dmem_adr_o[12] , |
| \u_riscv_top.wbd_dmem_adr_o[11] , |
| \u_riscv_top.wbd_dmem_adr_o[10] , |
| \u_riscv_top.wbd_dmem_adr_o[9] , |
| \u_riscv_top.wbd_dmem_adr_o[8] , |
| \u_riscv_top.wbd_dmem_adr_o[7] , |
| \u_riscv_top.wbd_dmem_adr_o[6] , |
| \u_riscv_top.wbd_dmem_adr_o[5] , |
| \u_riscv_top.wbd_dmem_adr_o[4] , |
| \u_riscv_top.wbd_dmem_adr_o[3] , |
| \u_riscv_top.wbd_dmem_adr_o[2] , |
| \u_riscv_top.wbd_dmem_adr_o[1] , |
| \u_riscv_top.wbd_dmem_adr_o[0] }), |
| .wbd_dmem_bl_o({\u_riscv_top.wbd_dmem_bl_o[2] , |
| \u_riscv_top.wbd_dmem_bl_o[1] , |
| \u_riscv_top.wbd_dmem_bl_o[0] }), |
| .wbd_dmem_dat_i({\u_riscv_top.wbd_dmem_dat_i[31] , |
| \u_riscv_top.wbd_dmem_dat_i[30] , |
| \u_riscv_top.wbd_dmem_dat_i[29] , |
| \u_riscv_top.wbd_dmem_dat_i[28] , |
| \u_riscv_top.wbd_dmem_dat_i[27] , |
| \u_riscv_top.wbd_dmem_dat_i[26] , |
| \u_riscv_top.wbd_dmem_dat_i[25] , |
| \u_riscv_top.wbd_dmem_dat_i[24] , |
| \u_riscv_top.wbd_dmem_dat_i[23] , |
| \u_riscv_top.wbd_dmem_dat_i[22] , |
| \u_riscv_top.wbd_dmem_dat_i[21] , |
| \u_riscv_top.wbd_dmem_dat_i[20] , |
| \u_riscv_top.wbd_dmem_dat_i[19] , |
| \u_riscv_top.wbd_dmem_dat_i[18] , |
| \u_riscv_top.wbd_dmem_dat_i[17] , |
| \u_riscv_top.wbd_dmem_dat_i[16] , |
| \u_riscv_top.wbd_dmem_dat_i[15] , |
| \u_riscv_top.wbd_dmem_dat_i[14] , |
| \u_riscv_top.wbd_dmem_dat_i[13] , |
| \u_riscv_top.wbd_dmem_dat_i[12] , |
| \u_riscv_top.wbd_dmem_dat_i[11] , |
| \u_riscv_top.wbd_dmem_dat_i[10] , |
| \u_riscv_top.wbd_dmem_dat_i[9] , |
| \u_riscv_top.wbd_dmem_dat_i[8] , |
| \u_riscv_top.wbd_dmem_dat_i[7] , |
| \u_riscv_top.wbd_dmem_dat_i[6] , |
| \u_riscv_top.wbd_dmem_dat_i[5] , |
| \u_riscv_top.wbd_dmem_dat_i[4] , |
| \u_riscv_top.wbd_dmem_dat_i[3] , |
| \u_riscv_top.wbd_dmem_dat_i[2] , |
| \u_riscv_top.wbd_dmem_dat_i[1] , |
| \u_riscv_top.wbd_dmem_dat_i[0] }), |
| .wbd_dmem_dat_o({\u_riscv_top.wbd_dmem_dat_o[31] , |
| \u_riscv_top.wbd_dmem_dat_o[30] , |
| \u_riscv_top.wbd_dmem_dat_o[29] , |
| \u_riscv_top.wbd_dmem_dat_o[28] , |
| \u_riscv_top.wbd_dmem_dat_o[27] , |
| \u_riscv_top.wbd_dmem_dat_o[26] , |
| \u_riscv_top.wbd_dmem_dat_o[25] , |
| \u_riscv_top.wbd_dmem_dat_o[24] , |
| \u_riscv_top.wbd_dmem_dat_o[23] , |
| \u_riscv_top.wbd_dmem_dat_o[22] , |
| \u_riscv_top.wbd_dmem_dat_o[21] , |
| \u_riscv_top.wbd_dmem_dat_o[20] , |
| \u_riscv_top.wbd_dmem_dat_o[19] , |
| \u_riscv_top.wbd_dmem_dat_o[18] , |
| \u_riscv_top.wbd_dmem_dat_o[17] , |
| \u_riscv_top.wbd_dmem_dat_o[16] , |
| \u_riscv_top.wbd_dmem_dat_o[15] , |
| \u_riscv_top.wbd_dmem_dat_o[14] , |
| \u_riscv_top.wbd_dmem_dat_o[13] , |
| \u_riscv_top.wbd_dmem_dat_o[12] , |
| \u_riscv_top.wbd_dmem_dat_o[11] , |
| \u_riscv_top.wbd_dmem_dat_o[10] , |
| \u_riscv_top.wbd_dmem_dat_o[9] , |
| \u_riscv_top.wbd_dmem_dat_o[8] , |
| \u_riscv_top.wbd_dmem_dat_o[7] , |
| \u_riscv_top.wbd_dmem_dat_o[6] , |
| \u_riscv_top.wbd_dmem_dat_o[5] , |
| \u_riscv_top.wbd_dmem_dat_o[4] , |
| \u_riscv_top.wbd_dmem_dat_o[3] , |
| \u_riscv_top.wbd_dmem_dat_o[2] , |
| \u_riscv_top.wbd_dmem_dat_o[1] , |
| \u_riscv_top.wbd_dmem_dat_o[0] }), |
| .wbd_dmem_sel_o({\u_riscv_top.wbd_dmem_sel_o[3] , |
| \u_riscv_top.wbd_dmem_sel_o[2] , |
| \u_riscv_top.wbd_dmem_sel_o[1] , |
| \u_riscv_top.wbd_dmem_sel_o[0] })); |
| bus_rep_east u_rp_east (.vccd1(vccd1), |
| .vssd1(vssd1), |
| .ch_in({io_in[0], |
| \io_out_int[0] , |
| \io_oeb_int[0] , |
| io_in[1], |
| \io_out_int[1] , |
| \io_oeb_int[1] , |
| io_in[2], |
| \io_out_int[2] , |
| \io_oeb_int[2] , |
| io_in[3], |
| \io_out_int[3] , |
| \io_oeb_int[3] , |
| io_in[4], |
| \io_out_int[4] , |
| \io_oeb_int[4] , |
| io_in[5], |
| \io_out_int[5] , |
| \io_oeb_int[5] , |
| io_in[6], |
| \io_out_int[6] , |
| \io_oeb_int[6] , |
| io_in[7], |
| \io_out_int[7] , |
| \io_oeb_int[7] , |
| io_in[8], |
| \io_out_int[8] , |
| \io_oeb_int[8] , |
| io_in[9], |
| \io_out_int[9] , |
| \io_oeb_int[9] , |
| io_in[10], |
| \io_out_int[10] , |
| \io_oeb_int[10] , |
| io_in[11], |
| \io_out_int[11] , |
| \io_oeb_int[11] , |
| io_in[12], |
| \io_out_int[12] , |
| \io_oeb_int[12] , |
| io_in[13], |
| \io_out_int[13] , |
| \io_oeb_int[13] , |
| io_in[14], |
| \io_out_int[14] , |
| \io_oeb_int[14] }), |
| .ch_out({\ch_out_east[44] , |
| io_out[0], |
| io_oeb[0], |
| \ch_out_east[41] , |
| io_out[1], |
| io_oeb[1], |
| \ch_out_east[38] , |
| io_out[2], |
| io_oeb[2], |
| \ch_out_east[35] , |
| io_out[3], |
| io_oeb[3], |
| \ch_out_east[32] , |
| io_out[4], |
| io_oeb[4], |
| \ch_out_east[29] , |
| io_out[5], |
| io_oeb[5], |
| \ch_out_east[26] , |
| io_out[6], |
| io_oeb[6], |
| \ch_out_east[23] , |
| io_out[7], |
| io_oeb[7], |
| \ch_out_east[20] , |
| io_out[8], |
| io_oeb[8], |
| \ch_out_east[17] , |
| io_out[9], |
| io_oeb[9], |
| \ch_out_east[14] , |
| io_out[10], |
| io_oeb[10], |
| \ch_out_east[11] , |
| io_out[11], |
| io_oeb[11], |
| \ch_out_east[8] , |
| io_out[12], |
| io_oeb[12], |
| \ch_out_east[5] , |
| io_out[13], |
| io_oeb[13], |
| \ch_out_east[2] , |
| io_out[14], |
| io_oeb[14]})); |
| bus_rep_north u_rp_north (.vccd1(vccd1), |
| .vssd1(vssd1), |
| .buf_in({\io_oeb_int[37] , |
| \io_out_int[37] , |
| \ch_out_west[39] , |
| \io_oeb_int[36] , |
| \io_out_int[36] , |
| \ch_out_west[36] , |
| \io_oeb_int[35] , |
| \io_out_int[35] , |
| \ch_out_west[33] , |
| \io_oeb_int[34] , |
| \io_out_int[34] , |
| \ch_out_west[30] , |
| \io_oeb_int[33] , |
| \io_out_int[33] , |
| \ch_out_west[27] , |
| \io_oeb_int[32] , |
| \io_out_int[32] , |
| \ch_out_west[24] , |
| \io_oeb_int[31] , |
| \io_out_int[31] , |
| \ch_out_west[21] , |
| \io_oeb_int[30] , |
| \io_out_int[30] , |
| \ch_out_west[18] , |
| \io_oeb_int[29] , |
| \io_out_int[29] , |
| \ch_out_west[15] , |
| \io_oeb_int[28] , |
| \io_out_int[28] , |
| \ch_out_west[12] , |
| \io_oeb_int[27] , |
| \io_out_int[27] , |
| \ch_out_west[9] , |
| \io_oeb_int[26] , |
| \io_out_int[26] , |
| \ch_out_west[6] , |
| \io_oeb_int[25] , |
| \io_out_int[25] , |
| \ch_out_west[3] , |
| \io_oeb_int[24] , |
| \io_out_int[24] , |
| \ch_out_west[0] }), |
| .buf_out({\buf_out_north[41] , |
| \buf_out_north[40] , |
| \buf_out_north[39] , |
| \buf_out_north[38] , |
| \buf_out_north[37] , |
| \buf_out_north[36] , |
| \buf_out_north[35] , |
| \buf_out_north[34] , |
| \buf_out_north[33] , |
| \buf_out_north[32] , |
| \buf_out_north[31] , |
| \buf_out_north[30] , |
| \buf_out_north[29] , |
| \buf_out_north[28] , |
| \buf_out_north[27] , |
| \buf_out_north[26] , |
| \buf_out_north[25] , |
| \buf_out_north[24] , |
| \buf_out_north[23] , |
| \buf_out_north[22] , |
| \buf_out_north[21] , |
| \buf_out_north[20] , |
| \buf_out_north[19] , |
| \buf_out_north[18] , |
| \buf_out_north[17] , |
| \buf_out_north[16] , |
| \buf_out_north[15] , |
| \buf_out_north[14] , |
| \buf_out_north[13] , |
| \buf_out_north[12] , |
| \buf_out_north[11] , |
| \buf_out_north[10] , |
| \buf_out_north[9] , |
| \buf_out_north[8] , |
| \buf_out_north[7] , |
| \buf_out_north[6] , |
| \buf_out_north[5] , |
| \buf_out_north[4] , |
| \buf_out_north[3] , |
| \buf_out_north[2] , |
| \buf_out_north[1] , |
| \buf_out_north[0] }), |
| .ch_in({io_in[15], |
| \io_out_int[15] , |
| \io_oeb_int[15] , |
| io_in[16], |
| \io_out_int[16] , |
| \io_oeb_int[16] , |
| io_in[17], |
| \io_out_int[17] , |
| \io_oeb_int[17] , |
| io_in[18], |
| \io_out_int[18] , |
| \io_oeb_int[18] , |
| io_in[19], |
| \io_out_int[19] , |
| \io_oeb_int[19] , |
| io_in[20], |
| \io_out_int[20] , |
| \io_oeb_int[20] , |
| io_in[21], |
| \io_out_int[21] , |
| \io_oeb_int[21] , |
| io_in[22], |
| \io_out_int[22] , |
| \io_oeb_int[22] , |
| io_in[23], |
| \io_out_int[23] , |
| \io_oeb_int[23] }), |
| .ch_out({\ch_out_north[26] , |
| io_out[15], |
| io_oeb[15], |
| \ch_out_north[23] , |
| io_out[16], |
| io_oeb[16], |
| \ch_out_north[20] , |
| io_out[17], |
| io_oeb[17], |
| \ch_out_north[17] , |
| io_out[18], |
| io_oeb[18], |
| \ch_out_north[14] , |
| io_out[19], |
| io_oeb[19], |
| \ch_out_north[11] , |
| io_out[20], |
| io_oeb[20], |
| \ch_out_north[8] , |
| io_out[21], |
| io_oeb[21], |
| \ch_out_north[5] , |
| io_out[22], |
| io_oeb[22], |
| \ch_out_north[2] , |
| io_out[23], |
| io_oeb[23]})); |
| bus_rep_south u_rp_south (.vccd1(vccd1), |
| .vssd1(vssd1), |
| .ch_in({user_clock2, |
| \pinmux_debug[31] , |
| \pinmux_debug[30] , |
| \pinmux_debug[29] , |
| \pinmux_debug[28] , |
| \pinmux_debug[27] , |
| \pinmux_debug[26] , |
| \pinmux_debug[25] , |
| \pinmux_debug[24] , |
| \pinmux_debug[23] , |
| \pinmux_debug[22] , |
| \pinmux_debug[21] , |
| \pinmux_debug[20] , |
| \pinmux_debug[19] , |
| \pinmux_debug[18] , |
| \pinmux_debug[17] , |
| \pinmux_debug[16] , |
| \pinmux_debug[15] , |
| \pinmux_debug[14] , |
| \pinmux_debug[13] , |
| \pinmux_debug[12] , |
| \pinmux_debug[11] , |
| \pinmux_debug[10] , |
| \pinmux_debug[9] , |
| \pinmux_debug[8] , |
| \pinmux_debug[7] , |
| \pinmux_debug[6] , |
| \pinmux_debug[5] , |
| \pinmux_debug[4] , |
| \pinmux_debug[3] , |
| \pinmux_debug[2] , |
| \pinmux_debug[1] , |
| \pinmux_debug[0] , |
| \spi_debug[31] , |
| \spi_debug[30] , |
| \spi_debug[29] , |
| \spi_debug[28] , |
| \spi_debug[27] , |
| \spi_debug[26] , |
| \spi_debug[25] , |
| \spi_debug[24] , |
| \spi_debug[23] , |
| \spi_debug[22] , |
| \spi_debug[21] , |
| \spi_debug[20] , |
| \spi_debug[19] , |
| \spi_debug[18] , |
| \spi_debug[17] , |
| \spi_debug[16] , |
| \spi_debug[15] , |
| \spi_debug[14] , |
| \spi_debug[13] , |
| \spi_debug[12] , |
| \spi_debug[11] , |
| \spi_debug[10] , |
| \spi_debug[9] , |
| \spi_debug[8] , |
| \spi_debug[7] , |
| \spi_debug[6] , |
| \spi_debug[5] , |
| \spi_debug[4] , |
| \spi_debug[3] , |
| \spi_debug[2] , |
| \spi_debug[1] , |
| \spi_debug[0] , |
| \u_riscv_top.riscv_debug[63] , |
| \u_riscv_top.riscv_debug[62] , |
| \u_riscv_top.riscv_debug[61] , |
| \u_riscv_top.riscv_debug[60] , |
| \u_riscv_top.riscv_debug[59] , |
| \u_riscv_top.riscv_debug[58] , |
| \u_riscv_top.riscv_debug[57] , |
| \u_riscv_top.riscv_debug[56] , |
| \u_riscv_top.riscv_debug[55] , |
| \u_riscv_top.riscv_debug[54] , |
| \u_riscv_top.riscv_debug[53] , |
| \u_riscv_top.riscv_debug[52] , |
| \u_riscv_top.riscv_debug[51] , |
| \u_riscv_top.riscv_debug[50] , |
| \u_riscv_top.riscv_debug[49] , |
| \u_riscv_top.riscv_debug[48] , |
| \u_riscv_top.riscv_debug[47] , |
| \u_riscv_top.riscv_debug[46] , |
| \u_riscv_top.riscv_debug[45] , |
| \u_riscv_top.riscv_debug[44] , |
| \u_riscv_top.riscv_debug[43] , |
| \u_riscv_top.riscv_debug[42] , |
| \u_riscv_top.riscv_debug[41] , |
| \u_riscv_top.riscv_debug[40] , |
| \u_riscv_top.riscv_debug[39] , |
| \u_riscv_top.riscv_debug[38] , |
| \u_riscv_top.riscv_debug[37] , |
| \u_riscv_top.riscv_debug[36] , |
| \u_riscv_top.riscv_debug[35] , |
| \u_riscv_top.riscv_debug[34] , |
| \u_riscv_top.riscv_debug[33] , |
| \u_riscv_top.riscv_debug[32] , |
| \u_riscv_top.riscv_debug[31] , |
| \u_riscv_top.riscv_debug[30] , |
| \u_riscv_top.riscv_debug[29] , |
| \u_riscv_top.riscv_debug[28] , |
| \u_riscv_top.riscv_debug[27] , |
| \u_riscv_top.riscv_debug[26] , |
| \u_riscv_top.riscv_debug[25] , |
| \u_riscv_top.riscv_debug[24] , |
| \u_riscv_top.riscv_debug[23] , |
| \u_riscv_top.riscv_debug[22] , |
| \u_riscv_top.riscv_debug[21] , |
| \u_riscv_top.riscv_debug[20] , |
| \u_riscv_top.riscv_debug[19] , |
| \u_riscv_top.riscv_debug[18] , |
| \u_riscv_top.riscv_debug[17] , |
| la_data_in[17], |
| \u_riscv_top.riscv_debug[16] , |
| la_data_in[16], |
| \u_riscv_top.riscv_debug[15] , |
| la_data_in[15], |
| \u_riscv_top.riscv_debug[14] , |
| la_data_in[14], |
| \u_riscv_top.riscv_debug[13] , |
| la_data_in[13], |
| \u_riscv_top.riscv_debug[12] , |
| la_data_in[12], |
| \u_riscv_top.riscv_debug[11] , |
| la_data_in[11], |
| \u_riscv_top.riscv_debug[10] , |
| la_data_in[10], |
| \u_riscv_top.riscv_debug[9] , |
| la_data_in[9], |
| \u_riscv_top.riscv_debug[8] , |
| la_data_in[8], |
| \u_riscv_top.riscv_debug[7] , |
| la_data_in[7], |
| \u_riscv_top.riscv_debug[6] , |
| la_data_in[6], |
| \u_riscv_top.riscv_debug[5] , |
| la_data_in[5], |
| \u_riscv_top.riscv_debug[4] , |
| la_data_in[4], |
| \u_riscv_top.riscv_debug[3] , |
| la_data_in[3], |
| \u_riscv_top.riscv_debug[2] , |
| la_data_in[2], |
| \u_riscv_top.riscv_debug[1] , |
| la_data_in[1], |
| \u_riscv_top.riscv_debug[0] , |
| la_data_in[0], |
| \wbs_dat_int_o[31] , |
| wbs_dat_i[31], |
| wbs_adr_i[31], |
| \wbs_dat_int_o[30] , |
| wbs_dat_i[30], |
| wbs_adr_i[30], |
| \wbs_dat_int_o[29] , |
| wbs_dat_i[29], |
| wbs_adr_i[29], |
| \wbs_dat_int_o[28] , |
| wbs_dat_i[28], |
| wbs_adr_i[28], |
| \wbs_dat_int_o[27] , |
| wbs_dat_i[27], |
| wbs_adr_i[27], |
| \wbs_dat_int_o[26] , |
| wbs_dat_i[26], |
| wbs_adr_i[26], |
| \wbs_dat_int_o[25] , |
| wbs_dat_i[25], |
| wbs_adr_i[25], |
| \wbs_dat_int_o[24] , |
| wbs_dat_i[24], |
| wbs_adr_i[24], |
| \wbs_dat_int_o[23] , |
| wbs_dat_i[23], |
| wbs_adr_i[23], |
| \wbs_dat_int_o[22] , |
| wbs_dat_i[22], |
| wbs_adr_i[22], |
| \wbs_dat_int_o[21] , |
| wbs_dat_i[21], |
| wbs_adr_i[21], |
| \wbs_dat_int_o[20] , |
| wbs_dat_i[20], |
| wbs_adr_i[20], |
| \wbs_dat_int_o[19] , |
| wbs_dat_i[19], |
| wbs_adr_i[19], |
| \wbs_dat_int_o[18] , |
| wbs_dat_i[18], |
| wbs_adr_i[18], |
| \wbs_dat_int_o[17] , |
| wbs_dat_i[17], |
| wbs_adr_i[17], |
| \wbs_dat_int_o[16] , |
| wbs_dat_i[16], |
| wbs_adr_i[16], |
| \wbs_dat_int_o[15] , |
| wbs_dat_i[15], |
| wbs_adr_i[15], |
| \wbs_dat_int_o[14] , |
| wbs_dat_i[14], |
| wbs_adr_i[14], |
| \wbs_dat_int_o[13] , |
| wbs_dat_i[13], |
| wbs_adr_i[13], |
| \wbs_dat_int_o[12] , |
| wbs_dat_i[12], |
| wbs_adr_i[12], |
| \wbs_dat_int_o[11] , |
| wbs_dat_i[11], |
| wbs_adr_i[11], |
| \wbs_dat_int_o[10] , |
| wbs_dat_i[10], |
| wbs_adr_i[10], |
| \wbs_dat_int_o[9] , |
| wbs_dat_i[9], |
| wbs_adr_i[9], |
| \wbs_dat_int_o[8] , |
| wbs_dat_i[8], |
| wbs_adr_i[8], |
| \wbs_dat_int_o[7] , |
| wbs_dat_i[7], |
| wbs_adr_i[7], |
| \wbs_dat_int_o[6] , |
| wbs_dat_i[6], |
| wbs_adr_i[6], |
| \wbs_dat_int_o[5] , |
| wbs_dat_i[5], |
| wbs_adr_i[5], |
| \wbs_dat_int_o[4] , |
| wbs_dat_i[4], |
| wbs_adr_i[4], |
| wbs_sel_i[3], |
| \wbs_dat_int_o[3] , |
| wbs_dat_i[3], |
| wbs_adr_i[3], |
| wbs_sel_i[2], |
| \wbs_dat_int_o[2] , |
| wbs_dat_i[2], |
| wbs_adr_i[2], |
| wbs_sel_i[1], |
| \wbs_dat_int_o[1] , |
| wbs_dat_i[1], |
| wbs_adr_i[1], |
| wbs_sel_i[0], |
| \wbs_dat_int_o[0] , |
| wbs_dat_i[0], |
| wbs_adr_i[0], |
| wbs_we_i, |
| wbs_stb_i, |
| wbs_cyc_i, |
| wbs_ack_int_o, |
| wb_rst_i, |
| wb_clk_i}), |
| .ch_out({\ch_out_south[252] , |
| la_data_out[127], |
| la_data_out[126], |
| la_data_out[125], |
| la_data_out[124], |
| la_data_out[123], |
| la_data_out[122], |
| la_data_out[121], |
| la_data_out[120], |
| la_data_out[119], |
| la_data_out[118], |
| la_data_out[117], |
| la_data_out[116], |
| la_data_out[115], |
| la_data_out[114], |
| la_data_out[113], |
| la_data_out[112], |
| la_data_out[111], |
| la_data_out[110], |
| la_data_out[109], |
| la_data_out[108], |
| la_data_out[107], |
| la_data_out[106], |
| la_data_out[105], |
| la_data_out[104], |
| la_data_out[103], |
| la_data_out[102], |
| la_data_out[101], |
| la_data_out[100], |
| la_data_out[99], |
| la_data_out[98], |
| la_data_out[97], |
| la_data_out[96], |
| la_data_out[95], |
| la_data_out[94], |
| la_data_out[93], |
| la_data_out[92], |
| la_data_out[91], |
| la_data_out[90], |
| la_data_out[89], |
| la_data_out[88], |
| la_data_out[87], |
| la_data_out[86], |
| la_data_out[85], |
| la_data_out[84], |
| la_data_out[83], |
| la_data_out[82], |
| la_data_out[81], |
| la_data_out[80], |
| la_data_out[79], |
| la_data_out[78], |
| la_data_out[77], |
| la_data_out[76], |
| la_data_out[75], |
| la_data_out[74], |
| la_data_out[73], |
| la_data_out[72], |
| la_data_out[71], |
| la_data_out[70], |
| la_data_out[69], |
| la_data_out[68], |
| la_data_out[67], |
| la_data_out[66], |
| la_data_out[65], |
| la_data_out[64], |
| la_data_out[63], |
| la_data_out[62], |
| la_data_out[61], |
| la_data_out[60], |
| la_data_out[59], |
| la_data_out[58], |
| la_data_out[57], |
| la_data_out[56], |
| la_data_out[55], |
| la_data_out[54], |
| la_data_out[53], |
| la_data_out[52], |
| la_data_out[51], |
| la_data_out[50], |
| la_data_out[49], |
| la_data_out[48], |
| la_data_out[47], |
| la_data_out[46], |
| la_data_out[45], |
| la_data_out[44], |
| la_data_out[43], |
| la_data_out[42], |
| la_data_out[41], |
| la_data_out[40], |
| la_data_out[39], |
| la_data_out[38], |
| la_data_out[37], |
| la_data_out[36], |
| la_data_out[35], |
| la_data_out[34], |
| la_data_out[33], |
| la_data_out[32], |
| la_data_out[31], |
| la_data_out[30], |
| la_data_out[29], |
| la_data_out[28], |
| la_data_out[27], |
| la_data_out[26], |
| la_data_out[25], |
| la_data_out[24], |
| la_data_out[23], |
| la_data_out[22], |
| la_data_out[21], |
| la_data_out[20], |
| la_data_out[19], |
| la_data_out[18], |
| la_data_out[17], |
| \ch_out_south[140] , |
| la_data_out[16], |
| \ch_out_south[138] , |
| la_data_out[15], |
| \ch_out_south[136] , |
| la_data_out[14], |
| \ch_out_south[134] , |
| la_data_out[13], |
| \ch_out_south[132] , |
| la_data_out[12], |
| \ch_out_south[130] , |
| la_data_out[11], |
| \ch_out_south[128] , |
| la_data_out[10], |
| \ch_out_south[126] , |
| la_data_out[9], |
| \ch_out_south[124] , |
| la_data_out[8], |
| \ch_out_south[122] , |
| la_data_out[7], |
| \ch_out_south[120] , |
| la_data_out[6], |
| \ch_out_south[118] , |
| la_data_out[5], |
| \ch_out_south[116] , |
| la_data_out[4], |
| \ch_out_south[114] , |
| la_data_out[3], |
| \ch_out_south[112] , |
| la_data_out[2], |
| \ch_out_south[110] , |
| la_data_out[1], |
| \ch_out_south[108] , |
| la_data_out[0], |
| \ch_out_south[106] , |
| wbs_dat_o[31], |
| \ch_out_south[104] , |
| \ch_out_south[103] , |
| wbs_dat_o[30], |
| \ch_out_south[101] , |
| \ch_out_south[100] , |
| wbs_dat_o[29], |
| \ch_out_south[98] , |
| \ch_out_south[97] , |
| wbs_dat_o[28], |
| \ch_out_south[95] , |
| \ch_out_south[94] , |
| wbs_dat_o[27], |
| \ch_out_south[92] , |
| \ch_out_south[91] , |
| wbs_dat_o[26], |
| \ch_out_south[89] , |
| \ch_out_south[88] , |
| wbs_dat_o[25], |
| \ch_out_south[86] , |
| \ch_out_south[85] , |
| wbs_dat_o[24], |
| \ch_out_south[83] , |
| \ch_out_south[82] , |
| wbs_dat_o[23], |
| \ch_out_south[80] , |
| \ch_out_south[79] , |
| wbs_dat_o[22], |
| \ch_out_south[77] , |
| \ch_out_south[76] , |
| wbs_dat_o[21], |
| \ch_out_south[74] , |
| \ch_out_south[73] , |
| wbs_dat_o[20], |
| \ch_out_south[71] , |
| \ch_out_south[70] , |
| wbs_dat_o[19], |
| \ch_out_south[68] , |
| \ch_out_south[67] , |
| wbs_dat_o[18], |
| \ch_out_south[65] , |
| \ch_out_south[64] , |
| wbs_dat_o[17], |
| \ch_out_south[62] , |
| \ch_out_south[61] , |
| wbs_dat_o[16], |
| \ch_out_south[59] , |
| \ch_out_south[58] , |
| wbs_dat_o[15], |
| \ch_out_south[56] , |
| \ch_out_south[55] , |
| wbs_dat_o[14], |
| \ch_out_south[53] , |
| \ch_out_south[52] , |
| wbs_dat_o[13], |
| \ch_out_south[50] , |
| \ch_out_south[49] , |
| wbs_dat_o[12], |
| \ch_out_south[47] , |
| \ch_out_south[46] , |
| wbs_dat_o[11], |
| \ch_out_south[44] , |
| \ch_out_south[43] , |
| wbs_dat_o[10], |
| \ch_out_south[41] , |
| \ch_out_south[40] , |
| wbs_dat_o[9], |
| \ch_out_south[38] , |
| \ch_out_south[37] , |
| wbs_dat_o[8], |
| \ch_out_south[35] , |
| \ch_out_south[34] , |
| wbs_dat_o[7], |
| \ch_out_south[32] , |
| \ch_out_south[31] , |
| wbs_dat_o[6], |
| \ch_out_south[29] , |
| \ch_out_south[28] , |
| wbs_dat_o[5], |
| \ch_out_south[26] , |
| \ch_out_south[25] , |
| wbs_dat_o[4], |
| \ch_out_south[23] , |
| \ch_out_south[22] , |
| \ch_out_south[21] , |
| wbs_dat_o[3], |
| \ch_out_south[19] , |
| \ch_out_south[18] , |
| \ch_out_south[17] , |
| wbs_dat_o[2], |
| \ch_out_south[15] , |
| \ch_out_south[14] , |
| \ch_out_south[13] , |
| wbs_dat_o[1], |
| \ch_out_south[11] , |
| \ch_out_south[10] , |
| \ch_out_south[9] , |
| wbs_dat_o[0], |
| \ch_out_south[7] , |
| \ch_out_south[6] , |
| \ch_out_south[5] , |
| \ch_out_south[4] , |
| \ch_out_south[3] , |
| wbs_ack_o, |
| \ch_out_south[1] , |
| \ch_out_south[0] })); |
| bus_rep_west u_rp_west (.vccd1(vccd1), |
| .vssd1(vssd1), |
| .ch_in({\buf_out_north[41] , |
| \buf_out_north[40] , |
| io_in[37], |
| \buf_out_north[38] , |
| \buf_out_north[37] , |
| io_in[36], |
| \buf_out_north[35] , |
| \buf_out_north[34] , |
| io_in[35], |
| \buf_out_north[32] , |
| \buf_out_north[31] , |
| io_in[34], |
| \buf_out_north[29] , |
| \buf_out_north[28] , |
| io_in[33], |
| \buf_out_north[26] , |
| \buf_out_north[25] , |
| io_in[32], |
| \buf_out_north[23] , |
| \buf_out_north[22] , |
| io_in[31], |
| \buf_out_north[20] , |
| \buf_out_north[19] , |
| io_in[30], |
| \buf_out_north[17] , |
| \buf_out_north[16] , |
| io_in[29], |
| \buf_out_north[14] , |
| \buf_out_north[13] , |
| io_in[28], |
| \buf_out_north[11] , |
| \buf_out_north[10] , |
| io_in[27], |
| \buf_out_north[8] , |
| \buf_out_north[7] , |
| io_in[26], |
| \buf_out_north[5] , |
| \buf_out_north[4] , |
| io_in[25], |
| \buf_out_north[2] , |
| \buf_out_north[1] , |
| io_in[24]}), |
| .ch_out({io_oeb[37], |
| io_out[37], |
| \ch_out_west[39] , |
| io_oeb[36], |
| io_out[36], |
| \ch_out_west[36] , |
| io_oeb[35], |
| io_out[35], |
| \ch_out_west[33] , |
| io_oeb[34], |
| io_out[34], |
| \ch_out_west[30] , |
| io_oeb[33], |
| io_out[33], |
| \ch_out_west[27] , |
| io_oeb[32], |
| io_out[32], |
| \ch_out_west[24] , |
| io_oeb[31], |
| io_out[31], |
| \ch_out_west[21] , |
| io_oeb[30], |
| io_out[30], |
| \ch_out_west[18] , |
| io_oeb[29], |
| io_out[29], |
| \ch_out_west[15] , |
| io_oeb[28], |
| io_out[28], |
| \ch_out_west[12] , |
| io_oeb[27], |
| io_out[27], |
| \ch_out_west[9] , |
| io_oeb[26], |
| io_out[26], |
| \ch_out_west[6] , |
| io_oeb[25], |
| io_out[25], |
| \ch_out_west[3] , |
| io_oeb[24], |
| io_out[24], |
| \ch_out_west[0] })); |
| sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb (.csb0(\u_riscv_top.sram0_csb0 ), |
| .csb1(\u_riscv_top.sram0_csb1 ), |
| .web0(\u_riscv_top.sram0_web0 ), |
| .clk0(\u_riscv_top.sram0_clk0 ), |
| .clk1(\u_riscv_top.sram0_clk1 ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .addr0({\u_riscv_top.sram0_addr0[8] , |
| \u_riscv_top.sram0_addr0[7] , |
| \u_riscv_top.sram0_addr0[6] , |
| \u_riscv_top.sram0_addr0[5] , |
| \u_riscv_top.sram0_addr0[4] , |
| \u_riscv_top.sram0_addr0[3] , |
| \u_riscv_top.sram0_addr0[2] , |
| \u_riscv_top.sram0_addr0[1] , |
| \u_riscv_top.sram0_addr0[0] }), |
| .addr1({\u_riscv_top.sram0_addr1[8] , |
| \u_riscv_top.sram0_addr1[7] , |
| \u_riscv_top.sram0_addr1[6] , |
| \u_riscv_top.sram0_addr1[5] , |
| \u_riscv_top.sram0_addr1[4] , |
| \u_riscv_top.sram0_addr1[3] , |
| \u_riscv_top.sram0_addr1[2] , |
| \u_riscv_top.sram0_addr1[1] , |
| \u_riscv_top.sram0_addr1[0] }), |
| .din0({\u_riscv_top.sram0_din0[31] , |
| \u_riscv_top.sram0_din0[30] , |
| \u_riscv_top.sram0_din0[29] , |
| \u_riscv_top.sram0_din0[28] , |
| \u_riscv_top.sram0_din0[27] , |
| \u_riscv_top.sram0_din0[26] , |
| \u_riscv_top.sram0_din0[25] , |
| \u_riscv_top.sram0_din0[24] , |
| \u_riscv_top.sram0_din0[23] , |
| \u_riscv_top.sram0_din0[22] , |
| \u_riscv_top.sram0_din0[21] , |
| \u_riscv_top.sram0_din0[20] , |
| \u_riscv_top.sram0_din0[19] , |
| \u_riscv_top.sram0_din0[18] , |
| \u_riscv_top.sram0_din0[17] , |
| \u_riscv_top.sram0_din0[16] , |
| \u_riscv_top.sram0_din0[15] , |
| \u_riscv_top.sram0_din0[14] , |
| \u_riscv_top.sram0_din0[13] , |
| \u_riscv_top.sram0_din0[12] , |
| \u_riscv_top.sram0_din0[11] , |
| \u_riscv_top.sram0_din0[10] , |
| \u_riscv_top.sram0_din0[9] , |
| \u_riscv_top.sram0_din0[8] , |
| \u_riscv_top.sram0_din0[7] , |
| \u_riscv_top.sram0_din0[6] , |
| \u_riscv_top.sram0_din0[5] , |
| \u_riscv_top.sram0_din0[4] , |
| \u_riscv_top.sram0_din0[3] , |
| \u_riscv_top.sram0_din0[2] , |
| \u_riscv_top.sram0_din0[1] , |
| \u_riscv_top.sram0_din0[0] }), |
| .dout0({\u_riscv_top.sram0_dout0[31] , |
| \u_riscv_top.sram0_dout0[30] , |
| \u_riscv_top.sram0_dout0[29] , |
| \u_riscv_top.sram0_dout0[28] , |
| \u_riscv_top.sram0_dout0[27] , |
| \u_riscv_top.sram0_dout0[26] , |
| \u_riscv_top.sram0_dout0[25] , |
| \u_riscv_top.sram0_dout0[24] , |
| \u_riscv_top.sram0_dout0[23] , |
| \u_riscv_top.sram0_dout0[22] , |
| \u_riscv_top.sram0_dout0[21] , |
| \u_riscv_top.sram0_dout0[20] , |
| \u_riscv_top.sram0_dout0[19] , |
| \u_riscv_top.sram0_dout0[18] , |
| \u_riscv_top.sram0_dout0[17] , |
| \u_riscv_top.sram0_dout0[16] , |
| \u_riscv_top.sram0_dout0[15] , |
| \u_riscv_top.sram0_dout0[14] , |
| \u_riscv_top.sram0_dout0[13] , |
| \u_riscv_top.sram0_dout0[12] , |
| \u_riscv_top.sram0_dout0[11] , |
| \u_riscv_top.sram0_dout0[10] , |
| \u_riscv_top.sram0_dout0[9] , |
| \u_riscv_top.sram0_dout0[8] , |
| \u_riscv_top.sram0_dout0[7] , |
| \u_riscv_top.sram0_dout0[6] , |
| \u_riscv_top.sram0_dout0[5] , |
| \u_riscv_top.sram0_dout0[4] , |
| \u_riscv_top.sram0_dout0[3] , |
| \u_riscv_top.sram0_dout0[2] , |
| \u_riscv_top.sram0_dout0[1] , |
| \u_riscv_top.sram0_dout0[0] }), |
| .dout1({\u_riscv_top.sram0_dout1[31] , |
| \u_riscv_top.sram0_dout1[30] , |
| \u_riscv_top.sram0_dout1[29] , |
| \u_riscv_top.sram0_dout1[28] , |
| \u_riscv_top.sram0_dout1[27] , |
| \u_riscv_top.sram0_dout1[26] , |
| \u_riscv_top.sram0_dout1[25] , |
| \u_riscv_top.sram0_dout1[24] , |
| \u_riscv_top.sram0_dout1[23] , |
| \u_riscv_top.sram0_dout1[22] , |
| \u_riscv_top.sram0_dout1[21] , |
| \u_riscv_top.sram0_dout1[20] , |
| \u_riscv_top.sram0_dout1[19] , |
| \u_riscv_top.sram0_dout1[18] , |
| \u_riscv_top.sram0_dout1[17] , |
| \u_riscv_top.sram0_dout1[16] , |
| \u_riscv_top.sram0_dout1[15] , |
| \u_riscv_top.sram0_dout1[14] , |
| \u_riscv_top.sram0_dout1[13] , |
| \u_riscv_top.sram0_dout1[12] , |
| \u_riscv_top.sram0_dout1[11] , |
| \u_riscv_top.sram0_dout1[10] , |
| \u_riscv_top.sram0_dout1[9] , |
| \u_riscv_top.sram0_dout1[8] , |
| \u_riscv_top.sram0_dout1[7] , |
| \u_riscv_top.sram0_dout1[6] , |
| \u_riscv_top.sram0_dout1[5] , |
| \u_riscv_top.sram0_dout1[4] , |
| \u_riscv_top.sram0_dout1[3] , |
| \u_riscv_top.sram0_dout1[2] , |
| \u_riscv_top.sram0_dout1[1] , |
| \u_riscv_top.sram0_dout1[0] }), |
| .wmask0({\u_riscv_top.sram0_wmask0[3] , |
| \u_riscv_top.sram0_wmask0[2] , |
| \u_riscv_top.sram0_wmask0[1] , |
| \u_riscv_top.sram0_wmask0[0] })); |
| uart_i2c_usb_spi_top u_uart_i2c_usb_spi (.app_clk(wbd_clk_uart_skew), |
| .i2c_rstn(i2c_rst_n), |
| .i2cm_intr_o(i2cm_intr_o), |
| .reg_ack(wbd_uart_ack_i), |
| .reg_cs(wbd_uart_stb_o), |
| .reg_wr(wbd_uart_we_o), |
| .scl_pad_i(i2cm_clk_i), |
| .scl_pad_o(i2cm_clk_o), |
| .scl_pad_oen_o(i2cm_clk_oen), |
| .sda_pad_i(i2cm_data_i), |
| .sda_pad_o(i2cm_data_o), |
| .sda_padoen_o(i2cm_data_oen), |
| .spi_rstn(sspim_rst_n), |
| .sspim_sck(sspim_sck), |
| .sspim_si(sspim_si), |
| .sspim_so(sspim_so), |
| .usb_clk(usb_clk), |
| .usb_in_dn(usb_dn_i), |
| .usb_in_dp(usb_dp_i), |
| .usb_intr_o(usb_intr_o), |
| .usb_out_dn(usb_dn_o), |
| .usb_out_dp(usb_dp_o), |
| .usb_out_tx_oen(usb_oen), |
| .usb_rstn(usb_rst_n), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(wbd_clk_uart_rp), |
| .wbd_clk_uart(wbd_clk_uart_skew), |
| .cfg_cska_uart({\cfg_wcska_uart_rp[3] , |
| \cfg_wcska_uart_rp[2] , |
| \cfg_wcska_uart_rp[1] , |
| \cfg_wcska_uart_rp[0] }), |
| .reg_addr({\wbd_uart_adr_o[8] , |
| \wbd_uart_adr_o[7] , |
| \wbd_uart_adr_o[6] , |
| \wbd_uart_adr_o[5] , |
| \wbd_uart_adr_o[4] , |
| \wbd_uart_adr_o[3] , |
| \wbd_uart_adr_o[2] , |
| \wbd_uart_adr_o[1] , |
| \wbd_uart_adr_o[0] }), |
| .reg_be({\wbd_uart_sel_o[3] , |
| \wbd_uart_sel_o[2] , |
| \wbd_uart_sel_o[1] , |
| \wbd_uart_sel_o[0] }), |
| .reg_rdata({\wbd_uart_dat_i[31] , |
| \wbd_uart_dat_i[30] , |
| \wbd_uart_dat_i[29] , |
| \wbd_uart_dat_i[28] , |
| \wbd_uart_dat_i[27] , |
| \wbd_uart_dat_i[26] , |
| \wbd_uart_dat_i[25] , |
| \wbd_uart_dat_i[24] , |
| \wbd_uart_dat_i[23] , |
| \wbd_uart_dat_i[22] , |
| \wbd_uart_dat_i[21] , |
| \wbd_uart_dat_i[20] , |
| \wbd_uart_dat_i[19] , |
| \wbd_uart_dat_i[18] , |
| \wbd_uart_dat_i[17] , |
| \wbd_uart_dat_i[16] , |
| \wbd_uart_dat_i[15] , |
| \wbd_uart_dat_i[14] , |
| \wbd_uart_dat_i[13] , |
| \wbd_uart_dat_i[12] , |
| \wbd_uart_dat_i[11] , |
| \wbd_uart_dat_i[10] , |
| \wbd_uart_dat_i[9] , |
| \wbd_uart_dat_i[8] , |
| \wbd_uart_dat_i[7] , |
| \wbd_uart_dat_i[6] , |
| \wbd_uart_dat_i[5] , |
| \wbd_uart_dat_i[4] , |
| \wbd_uart_dat_i[3] , |
| \wbd_uart_dat_i[2] , |
| \wbd_uart_dat_i[1] , |
| \wbd_uart_dat_i[0] }), |
| .reg_wdata({\wbd_uart_dat_o[31] , |
| \wbd_uart_dat_o[30] , |
| \wbd_uart_dat_o[29] , |
| \wbd_uart_dat_o[28] , |
| \wbd_uart_dat_o[27] , |
| \wbd_uart_dat_o[26] , |
| \wbd_uart_dat_o[25] , |
| \wbd_uart_dat_o[24] , |
| \wbd_uart_dat_o[23] , |
| \wbd_uart_dat_o[22] , |
| \wbd_uart_dat_o[21] , |
| \wbd_uart_dat_o[20] , |
| \wbd_uart_dat_o[19] , |
| \wbd_uart_dat_o[18] , |
| \wbd_uart_dat_o[17] , |
| \wbd_uart_dat_o[16] , |
| \wbd_uart_dat_o[15] , |
| \wbd_uart_dat_o[14] , |
| \wbd_uart_dat_o[13] , |
| \wbd_uart_dat_o[12] , |
| \wbd_uart_dat_o[11] , |
| \wbd_uart_dat_o[10] , |
| \wbd_uart_dat_o[9] , |
| \wbd_uart_dat_o[8] , |
| \wbd_uart_dat_o[7] , |
| \wbd_uart_dat_o[6] , |
| \wbd_uart_dat_o[5] , |
| \wbd_uart_dat_o[4] , |
| \wbd_uart_dat_o[3] , |
| \wbd_uart_dat_o[2] , |
| \wbd_uart_dat_o[1] , |
| \wbd_uart_dat_o[0] }), |
| .sspim_ssn({\sspim_ssn[3] , |
| \sspim_ssn[2] , |
| \sspim_ssn[1] , |
| \sspim_ssn[0] }), |
| .uart_rstn({\uart_rst_n[1] , |
| \uart_rst_n[0] }), |
| .uart_rxd({\uart_rxd[1] , |
| \uart_rxd[0] }), |
| .uart_txd({\uart_txd[1] , |
| \uart_txd[0] })); |
| wb_host u_wb_host (.cfg_strap_pad_ctrl(cfg_strap_pad_ctrl), |
| .cpu_clk(cpu_clk), |
| .e_reset_n(e_reset_n), |
| .int_pll_clock(\pll_clk_out[0] ), |
| .p_reset_n(p_reset_n), |
| .s_reset_n(s_reset_n), |
| .sclk(sspis_sck), |
| .sdin(sspis_si), |
| .sdout(sspis_so), |
| .ssn(sspis_ssn), |
| .uartm_rxd(uartm_rxd), |
| .uartm_txd(uartm_txd), |
| .user_clock1(\ch_out_south[0] ), |
| .user_clock2(\ch_out_south[252] ), |
| .vccd1(vccd1), |
| .vssd1(vssd1), |
| .wbd_clk_int(wbd_clk_int), |
| .wbd_clk_wh(wbd_clk_wh), |
| .wbd_int_rst_n(\u_riscv_top.pwrup_rst_n ), |
| .wbd_pll_rst_n(wbd_pll_rst_n), |
| .wbm_ack_o(wbs_ack_int_o), |
| .wbm_clk_i(\ch_out_south[0] ), |
| .wbm_cyc_i(\ch_out_south[3] ), |
| .wbm_rst_i(\ch_out_south[1] ), |
| .wbm_stb_i(\ch_out_south[4] ), |
| .wbm_we_i(\ch_out_south[5] ), |
| .wbs_ack_i(wbd_int_ack_o), |
| .wbs_clk_i(wbd_clk_wh), |
| .wbs_clk_out(wbd_clk_int), |
| .wbs_cyc_o(wbd_int_cyc_i), |
| .wbs_err_i(wbd_int_err_o), |
| .wbs_stb_o(wbd_int_stb_i), |
| .wbs_we_o(wbd_int_we_i), |
| .xtal_clk(xtal_clk), |
| .cfg_clk_skew_ctrl1({\cfg_clk_skew_ctrl1[31] , |
| \cfg_clk_skew_ctrl1[30] , |
| \cfg_clk_skew_ctrl1[29] , |
| \cfg_clk_skew_ctrl1[28] , |
| \cfg_clk_skew_ctrl1[27] , |
| \cfg_clk_skew_ctrl1[26] , |
| \cfg_clk_skew_ctrl1[25] , |
| \cfg_clk_skew_ctrl1[24] , |
| \cfg_clk_skew_ctrl1[23] , |
| \cfg_clk_skew_ctrl1[22] , |
| \cfg_clk_skew_ctrl1[21] , |
| \cfg_clk_skew_ctrl1[20] , |
| \cfg_clk_skew_ctrl1[19] , |
| \cfg_clk_skew_ctrl1[18] , |
| \cfg_clk_skew_ctrl1[17] , |
| \cfg_clk_skew_ctrl1[16] , |
| \cfg_clk_skew_ctrl1[15] , |
| \cfg_clk_skew_ctrl1[14] , |
| \cfg_clk_skew_ctrl1[13] , |
| \cfg_clk_skew_ctrl1[12] , |
| \cfg_clk_skew_ctrl1[11] , |
| \cfg_clk_skew_ctrl1[10] , |
| \cfg_clk_skew_ctrl1[9] , |
| \cfg_clk_skew_ctrl1[8] , |
| \cfg_clk_skew_ctrl1[7] , |
| \cfg_clk_skew_ctrl1[6] , |
| \cfg_clk_skew_ctrl1[5] , |
| \cfg_clk_skew_ctrl1[4] , |
| \cfg_clk_skew_ctrl1[3] , |
| \cfg_clk_skew_ctrl1[2] , |
| \cfg_clk_skew_ctrl1[1] , |
| \cfg_clk_skew_ctrl1[0] }), |
| .cfg_clk_skew_ctrl2({\cfg_clk_skew_ctrl2[31] , |
| \cfg_clk_skew_ctrl2[30] , |
| \cfg_clk_skew_ctrl2[29] , |
| \cfg_clk_skew_ctrl2[28] , |
| \cfg_clk_skew_ctrl2[27] , |
| \cfg_clk_skew_ctrl2[26] , |
| \cfg_clk_skew_ctrl2[25] , |
| \cfg_clk_skew_ctrl2[24] , |
| \cfg_clk_skew_ctrl2[23] , |
| \cfg_clk_skew_ctrl2[22] , |
| \cfg_clk_skew_ctrl2[21] , |
| \cfg_clk_skew_ctrl2[20] , |
| \cfg_clk_skew_ctrl2[19] , |
| \cfg_clk_skew_ctrl2[18] , |
| \cfg_clk_skew_ctrl2[17] , |
| \cfg_clk_skew_ctrl2[16] , |
| \cfg_clk_skew_ctrl2[15] , |
| \cfg_clk_skew_ctrl2[14] , |
| \cfg_clk_skew_ctrl2[13] , |
| \cfg_clk_skew_ctrl2[12] , |
| \cfg_clk_skew_ctrl2[11] , |
| \cfg_clk_skew_ctrl2[10] , |
| \cfg_clk_skew_ctrl2[9] , |
| \cfg_clk_skew_ctrl2[8] , |
| \cfg_clk_skew_ctrl2[7] , |
| \cfg_clk_skew_ctrl2[6] , |
| \cfg_clk_skew_ctrl2[5] , |
| \cfg_clk_skew_ctrl2[4] , |
| \cfg_clk_skew_ctrl2[3] , |
| \cfg_clk_skew_ctrl2[2] , |
| \cfg_clk_skew_ctrl2[1] , |
| \cfg_clk_skew_ctrl2[0] }), |
| .cfg_cska_wh({\cfg_clk_skew_ctrl1[7] , |
| \cfg_clk_skew_ctrl1[6] , |
| \cfg_clk_skew_ctrl1[5] , |
| \cfg_clk_skew_ctrl1[4] }), |
| .la_data_in({\ch_out_south[140] , |
| \ch_out_south[138] , |
| \ch_out_south[136] , |
| \ch_out_south[134] , |
| \ch_out_south[132] , |
| \ch_out_south[130] , |
| \ch_out_south[128] , |
| \ch_out_south[126] , |
| \ch_out_south[124] , |
| \ch_out_south[122] , |
| \ch_out_south[120] , |
| \ch_out_south[118] , |
| \ch_out_south[116] , |
| \ch_out_south[114] , |
| \ch_out_south[112] , |
| \ch_out_south[110] , |
| \ch_out_south[108] , |
| \ch_out_south[106] }), |
| .strap_sticky({\strap_sticky_rp[31] , |
| \strap_sticky_rp[30] , |
| \strap_sticky_rp[29] , |
| \strap_sticky_rp[28] , |
| \strap_sticky_rp[27] , |
| \strap_sticky_rp[26] , |
| \strap_sticky_rp[25] , |
| \strap_sticky_rp[24] , |
| \strap_sticky_rp[23] , |
| \strap_sticky_rp[22] , |
| \strap_sticky_rp[21] , |
| \strap_sticky_rp[20] , |
| \strap_sticky_rp[19] , |
| \strap_sticky_rp[18] , |
| \strap_sticky_rp[17] , |
| \strap_sticky_rp[16] , |
| \strap_sticky_rp[15] , |
| \strap_sticky_rp[14] , |
| \strap_sticky_rp[13] , |
| \strap_sticky_rp[12] , |
| \strap_sticky_rp[11] , |
| \strap_sticky_rp[10] , |
| \strap_sticky_rp[9] , |
| \strap_sticky_rp[8] , |
| \strap_sticky_rp[7] , |
| \strap_sticky_rp[6] , |
| \strap_sticky_rp[5] , |
| \strap_sticky_rp[4] , |
| \strap_sticky_rp[3] , |
| \strap_sticky_rp[2] , |
| \strap_sticky_rp[1] , |
| \strap_sticky_rp[0] }), |
| .strap_uartm({\strap_uartm_rp[1] , |
| \strap_uartm_rp[0] }), |
| .system_strap({\system_strap[31] , |
| \system_strap[30] , |
| \system_strap[29] , |
| \system_strap[28] , |
| \system_strap[27] , |
| \system_strap[26] , |
| \system_strap[25] , |
| \system_strap[24] , |
| \system_strap[23] , |
| \system_strap[22] , |
| \system_strap[21] , |
| \system_strap[20] , |
| \system_strap[19] , |
| \system_strap[18] , |
| \system_strap[17] , |
| \system_strap[16] , |
| \system_strap[15] , |
| \system_strap[14] , |
| \system_strap[13] , |
| \system_strap[12] , |
| \system_strap[11] , |
| \system_strap[10] , |
| \system_strap[9] , |
| \system_strap[8] , |
| \system_strap[7] , |
| \system_strap[6] , |
| \system_strap[5] , |
| \system_strap[4] , |
| \system_strap[3] , |
| \system_strap[2] , |
| \system_strap[1] , |
| \system_strap[0] }), |
| .wbm_adr_i({\ch_out_south[103] , |
| \ch_out_south[100] , |
| \ch_out_south[97] , |
| \ch_out_south[94] , |
| \ch_out_south[91] , |
| \ch_out_south[88] , |
| \ch_out_south[85] , |
| \ch_out_south[82] , |
| \ch_out_south[79] , |
| \ch_out_south[76] , |
| \ch_out_south[73] , |
| \ch_out_south[70] , |
| \ch_out_south[67] , |
| \ch_out_south[64] , |
| \ch_out_south[61] , |
| \ch_out_south[58] , |
| \ch_out_south[55] , |
| \ch_out_south[52] , |
| \ch_out_south[49] , |
| \ch_out_south[46] , |
| \ch_out_south[43] , |
| \ch_out_south[40] , |
| \ch_out_south[37] , |
| \ch_out_south[34] , |
| \ch_out_south[31] , |
| \ch_out_south[28] , |
| \ch_out_south[25] , |
| \ch_out_south[22] , |
| \ch_out_south[18] , |
| \ch_out_south[14] , |
| \ch_out_south[10] , |
| \ch_out_south[6] }), |
| .wbm_dat_i({\ch_out_south[104] , |
| \ch_out_south[101] , |
| \ch_out_south[98] , |
| \ch_out_south[95] , |
| \ch_out_south[92] , |
| \ch_out_south[89] , |
| \ch_out_south[86] , |
| \ch_out_south[83] , |
| \ch_out_south[80] , |
| \ch_out_south[77] , |
| \ch_out_south[74] , |
| \ch_out_south[71] , |
| \ch_out_south[68] , |
| \ch_out_south[65] , |
| \ch_out_south[62] , |
| \ch_out_south[59] , |
| \ch_out_south[56] , |
| \ch_out_south[53] , |
| \ch_out_south[50] , |
| \ch_out_south[47] , |
| \ch_out_south[44] , |
| \ch_out_south[41] , |
| \ch_out_south[38] , |
| \ch_out_south[35] , |
| \ch_out_south[32] , |
| \ch_out_south[29] , |
| \ch_out_south[26] , |
| \ch_out_south[23] , |
| \ch_out_south[19] , |
| \ch_out_south[15] , |
| \ch_out_south[11] , |
| \ch_out_south[7] }), |
| .wbm_dat_o({\wbs_dat_int_o[31] , |
| \wbs_dat_int_o[30] , |
| \wbs_dat_int_o[29] , |
| \wbs_dat_int_o[28] , |
| \wbs_dat_int_o[27] , |
| \wbs_dat_int_o[26] , |
| \wbs_dat_int_o[25] , |
| \wbs_dat_int_o[24] , |
| \wbs_dat_int_o[23] , |
| \wbs_dat_int_o[22] , |
| \wbs_dat_int_o[21] , |
| \wbs_dat_int_o[20] , |
| \wbs_dat_int_o[19] , |
| \wbs_dat_int_o[18] , |
| \wbs_dat_int_o[17] , |
| \wbs_dat_int_o[16] , |
| \wbs_dat_int_o[15] , |
| \wbs_dat_int_o[14] , |
| \wbs_dat_int_o[13] , |
| \wbs_dat_int_o[12] , |
| \wbs_dat_int_o[11] , |
| \wbs_dat_int_o[10] , |
| \wbs_dat_int_o[9] , |
| \wbs_dat_int_o[8] , |
| \wbs_dat_int_o[7] , |
| \wbs_dat_int_o[6] , |
| \wbs_dat_int_o[5] , |
| \wbs_dat_int_o[4] , |
| \wbs_dat_int_o[3] , |
| \wbs_dat_int_o[2] , |
| \wbs_dat_int_o[1] , |
| \wbs_dat_int_o[0] }), |
| .wbm_sel_i({\ch_out_south[21] , |
| \ch_out_south[17] , |
| \ch_out_south[13] , |
| \ch_out_south[9] }), |
| .wbs_adr_o({\wbd_int_adr_i[31] , |
| \wbd_int_adr_i[30] , |
| \wbd_int_adr_i[29] , |
| \wbd_int_adr_i[28] , |
| \wbd_int_adr_i[27] , |
| \wbd_int_adr_i[26] , |
| \wbd_int_adr_i[25] , |
| \wbd_int_adr_i[24] , |
| \wbd_int_adr_i[23] , |
| \wbd_int_adr_i[22] , |
| \wbd_int_adr_i[21] , |
| \wbd_int_adr_i[20] , |
| \wbd_int_adr_i[19] , |
| \wbd_int_adr_i[18] , |
| \wbd_int_adr_i[17] , |
| \wbd_int_adr_i[16] , |
| \wbd_int_adr_i[15] , |
| \wbd_int_adr_i[14] , |
| \wbd_int_adr_i[13] , |
| \wbd_int_adr_i[12] , |
| \wbd_int_adr_i[11] , |
| \wbd_int_adr_i[10] , |
| \wbd_int_adr_i[9] , |
| \wbd_int_adr_i[8] , |
| \wbd_int_adr_i[7] , |
| \wbd_int_adr_i[6] , |
| \wbd_int_adr_i[5] , |
| \wbd_int_adr_i[4] , |
| \wbd_int_adr_i[3] , |
| \wbd_int_adr_i[2] , |
| \wbd_int_adr_i[1] , |
| \wbd_int_adr_i[0] }), |
| .wbs_dat_i({\wbd_int_dat_o[31] , |
| \wbd_int_dat_o[30] , |
| \wbd_int_dat_o[29] , |
| \wbd_int_dat_o[28] , |
| \wbd_int_dat_o[27] , |
| \wbd_int_dat_o[26] , |
| \wbd_int_dat_o[25] , |
| \wbd_int_dat_o[24] , |
| \wbd_int_dat_o[23] , |
| \wbd_int_dat_o[22] , |
| \wbd_int_dat_o[21] , |
| \wbd_int_dat_o[20] , |
| \wbd_int_dat_o[19] , |
| \wbd_int_dat_o[18] , |
| \wbd_int_dat_o[17] , |
| \wbd_int_dat_o[16] , |
| \wbd_int_dat_o[15] , |
| \wbd_int_dat_o[14] , |
| \wbd_int_dat_o[13] , |
| \wbd_int_dat_o[12] , |
| \wbd_int_dat_o[11] , |
| \wbd_int_dat_o[10] , |
| \wbd_int_dat_o[9] , |
| \wbd_int_dat_o[8] , |
| \wbd_int_dat_o[7] , |
| \wbd_int_dat_o[6] , |
| \wbd_int_dat_o[5] , |
| \wbd_int_dat_o[4] , |
| \wbd_int_dat_o[3] , |
| \wbd_int_dat_o[2] , |
| \wbd_int_dat_o[1] , |
| \wbd_int_dat_o[0] }), |
| .wbs_dat_o({\wbd_int_dat_i[31] , |
| \wbd_int_dat_i[30] , |
| \wbd_int_dat_i[29] , |
| \wbd_int_dat_i[28] , |
| \wbd_int_dat_i[27] , |
| \wbd_int_dat_i[26] , |
| \wbd_int_dat_i[25] , |
| \wbd_int_dat_i[24] , |
| \wbd_int_dat_i[23] , |
| \wbd_int_dat_i[22] , |
| \wbd_int_dat_i[21] , |
| \wbd_int_dat_i[20] , |
| \wbd_int_dat_i[19] , |
| \wbd_int_dat_i[18] , |
| \wbd_int_dat_i[17] , |
| \wbd_int_dat_i[16] , |
| \wbd_int_dat_i[15] , |
| \wbd_int_dat_i[14] , |
| \wbd_int_dat_i[13] , |
| \wbd_int_dat_i[12] , |
| \wbd_int_dat_i[11] , |
| \wbd_int_dat_i[10] , |
| \wbd_int_dat_i[9] , |
| \wbd_int_dat_i[8] , |
| \wbd_int_dat_i[7] , |
| \wbd_int_dat_i[6] , |
| \wbd_int_dat_i[5] , |
| \wbd_int_dat_i[4] , |
| \wbd_int_dat_i[3] , |
| \wbd_int_dat_i[2] , |
| \wbd_int_dat_i[1] , |
| \wbd_int_dat_i[0] }), |
| .wbs_sel_o({\wbd_int_sel_i[3] , |
| \wbd_int_sel_i[2] , |
| \wbd_int_sel_i[1] , |
| \wbd_int_sel_i[0] })); |
| endmodule |
