| /root/riscduino-dcore_d3_3/run_regress |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/timing.mk |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping-mpw2-calibre.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping-mpw2.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping-mpw5-calibre.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping-mpw7.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/env/common.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/env/f.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/env/s.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/env/t.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/compare_reports.py |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/generate_spef_mapping.py |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/get_macros.py |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/pdk_helpers.py |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/report.py |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/summarize_report.py |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/timing_path.py |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/verilog_parser.py |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/openroad/rcx.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/openroad/sdf.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/openroad/sta-gpio_control_block.tcl |
| /root/riscduino-dcore_d3_3/deps/timing-scripts/scripts/openroad/timing_top.tcl |
| /root/riscduino-dcore_d3_3/env/spef-mapping.tcl |
| /root/riscduino-dcore_d3_3/hacks/patch/pdngen.patch |
| /root/riscduino-dcore_d3_3/hacks/patch/resizer.patch |
| /root/riscduino-dcore_d3_3/hacks/src/OpenROAD/PdnGen.tcl |
| /root/riscduino-dcore_d3_3/hacks/src/OpenROAD/Resizer.cc |
| /root/riscduino-dcore_d3_3/hacks/src/OpenSTA/network/ConcreteNetwork.cc |
| /root/riscduino-dcore_d3_3/hacks/src/OpenSTA/tcl/NetworkEdit.tcl |
| /root/riscduino-dcore_d3_3/hacks/src/OpenSTA/tcl/Sta.tcl |
| /root/riscduino-dcore_d3_3/hacks/src/openlane/io_place.py |
| /root/riscduino-dcore_d3_3/hacks/src/openlane/synth.tcl |
| /root/riscduino-dcore_d3_3/hacks/src/openlane/synth_top.tcl |
| /root/riscduino-dcore_d3_3/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib |
| /root/riscduino-dcore_d3_3/openlane/aes_top/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/bus_rep_east/interactive.tcl |
| /root/riscduino-dcore_d3_3/openlane/bus_rep_north/interactive.tcl |
| /root/riscduino-dcore_d3_3/openlane/bus_rep_south/interactive.tcl |
| /root/riscduino-dcore_d3_3/openlane/bus_rep_west/interactive.tcl |
| /root/riscduino-dcore_d3_3/openlane/dg_pll/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/dg_pll/interactive.tcl |
| /root/riscduino-dcore_d3_3/openlane/fpu_wrapper/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/peri_top/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/pinmux_top/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/qspim_top/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/sar_adc/pdn.tcl |
| /root/riscduino-dcore_d3_3/openlane/uart_i2c_usb_spi_top/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/user_project_wrapper/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/user_project_wrapper/interactive.tcl |
| /root/riscduino-dcore_d3_3/openlane/user_project_wrapper/pdn.tcl |
| /root/riscduino-dcore_d3_3/openlane/user_project_wrapper/pdn_cfg.tcl |
| /root/riscduino-dcore_d3_3/openlane/user_project_wrapper/mpw5/pdn_cfg.tcl |
| /root/riscduino-dcore_d3_3/openlane/user_project_wrapper/mpw6/pdn_cfg.tcl |
| /root/riscduino-dcore_d3_3/openlane/wb_host/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/wb_interconnect/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/wb_interconnect/interactive.tcl |
| /root/riscduino-dcore_d3_3/openlane/ycr2_iconnect/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/ycr2_iconnect/drc_exclude.cells |
| /root/riscduino-dcore_d3_3/openlane/ycr_core_top/base.sdc |
| /root/riscduino-dcore_d3_3/openlane/ycr_intf/base.sdc |
| /root/riscduino-dcore_d3_3/scripts/klayout_drc.sh |
| /root/riscduino-dcore_d3_3/sdc/aes_top.sdc |
| /root/riscduino-dcore_d3_3/sdc/bus_rep_east.sdc |
| /root/riscduino-dcore_d3_3/sdc/bus_rep_north.sdc |
| /root/riscduino-dcore_d3_3/sdc/bus_rep_south.sdc |
| /root/riscduino-dcore_d3_3/sdc/bus_rep_west.sdc |
| /root/riscduino-dcore_d3_3/sdc/caravel.sdc |
| /root/riscduino-dcore_d3_3/sdc/dg_pll.sdc |
| /root/riscduino-dcore_d3_3/sdc/digital_pll.sdc |
| /root/riscduino-dcore_d3_3/sdc/fpu_wrapper.sdc |
| /root/riscduino-dcore_d3_3/sdc/peri_top.sdc |
| /root/riscduino-dcore_d3_3/sdc/pinmux.sdc |
| /root/riscduino-dcore_d3_3/sdc/pinmux_top.sdc |
| /root/riscduino-dcore_d3_3/sdc/qspim_top.sdc |
| /root/riscduino-dcore_d3_3/sdc/uart_i2c_usb_spi_top.sdc |
| /root/riscduino-dcore_d3_3/sdc/user_project_wrapper.sdc |
| /root/riscduino-dcore_d3_3/sdc/wb_host.sdc |
| /root/riscduino-dcore_d3_3/sdc/wb_interconnect.sdc |
| /root/riscduino-dcore_d3_3/sdc/ycr2_iconnect.sdc |
| /root/riscduino-dcore_d3_3/sdc/ycr_core_top.sdc |
| /root/riscduino-dcore_d3_3/sdc/ycr_intf.sdc |
| /root/riscduino-dcore_d3_3/sta/base.sdc |
| /root/riscduino-dcore_d3_3/sta/run_sta |
| /root/riscduino-dcore_d3_3/sta/scripts/caravel_timing.tcl |
| /root/riscduino-dcore_d3_3/sta/scripts/or_write_verilog.tcl |
| /root/riscduino-dcore_d3_3/sta/scripts/qspim_timing.tcl |
| /root/riscduino-dcore_d3_3/sta/scripts/riscdunio.tcl |
| /root/riscduino-dcore_d3_3/sta/scripts/statistic.tcl |
| /root/riscduino-dcore_d3_3/sta/scripts/uart_i2c_usb_spi_timing.tcl |
| /root/riscduino-dcore_d3_3/sta/scripts/ycr2_iconnect_timing.tcl |
| /root/riscduino-dcore_d3_3/sta/scripts/ycr_core_timing.tcl |
| /root/riscduino-dcore_d3_3/sta/scripts/ycr_intf.tcl |
| /root/riscduino-dcore_d3_3/sta/sdc/caravel.sdc |
| /root/riscduino-dcore_d3_3/sta/sdc/qspim_top.sdc |
| /root/riscduino-dcore_d3_3/sta/sdc/uart_i2c_usb_spi_top.sdc |
| /root/riscduino-dcore_d3_3/sta/sdc/ycr2_iconnect.sdc |
| /root/riscduino-dcore_d3_3/sta/sdc/ycr_core_top.sdc |
| /root/riscduino-dcore_d3_3/sta/sdc/ycr_intf.sdc |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_arrays/arduino_arrays.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_arrays/arduino_arrays.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_hello_world/arduino_hello_world.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_hello_world/arduino_hello_world.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_string/arduino_string.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_string/arduino_string.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_ws281x/arduino_ws281x.ino |
| /root/riscduino-dcore_d3_3/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/agents/caravel_task.sv |
| /root/riscduino-dcore_d3_3/verilog/dv/common/agents/test_control.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/agents/uart_master_tasks.sv |
| /root/riscduino-dcore_d3_3/verilog/dv/common/agents/usb_agents.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/agents/user_tasks.sv |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/bfm_ad5205.sv |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/bfm_spim.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/bfm_ws281x.sv |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb1d_defines.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usbd_files.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_core.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_crc16.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_crc5.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_fifo2.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_generic_dpram.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_generic_fifo.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_idma.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_pa.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_pd.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_pe.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_pl.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_rom1.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_sync_fifo.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_utmi_if.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/phy/usb1d_phy.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/phy/usb1d_rx_phy.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/phy/usb1d_tx_phy.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/top/usb1d_top.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/firmware/common_bthread.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/firmware/common_bthread.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/firmware/common_misc.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/firmware/ext_reg_map.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/firmware/int_reg_map.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/model/is62wvs1288.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/model/spiram.v |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/package_riscduino_index.json |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/CHANGELOG |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/installed.json |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Arduino.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/HardwareSerial.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Print.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Print.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Printable.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Stream.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Stream.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/TIMERClass.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/TIMERClass.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/UARTClass.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/UARTClass.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WCharacter.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WInterrupts.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WInterrupts.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WMath.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WMath.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WString.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WString.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/abi.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/binary.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/entry.S |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/hooks.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/init.S |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/itoa.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/itoa.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/main.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/malloc.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/new.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/sbrk.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/start.S |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_analog.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_analog.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_constants.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_digital.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_digital.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_private.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_pulse.cpp |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_pulse.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_shift.c |
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| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/drivers/plic/plic_driver.c |
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| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/drivers/plic/plic_driver.c |
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| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/wire.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/ws281x.h |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/libwrap.mk |
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| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/stdlib/malloc.c |
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| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/isatty.c |
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| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/dhrystone/Makefile |
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| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/dhrystone/dhry_printf.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/dhrystone/dhry_stubs.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/double_tap_dontboot/Makefile |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/double_tap_dontboot/double_tap_dontboot.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/hello/Makefile |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/hello/hello.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/led_fade/Makefile |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/led_fade/led_fade.c |
| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/system/include/riscv/_fpmath.h |
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| /root/riscduino-dcore_d3_3/verilog/dv/common/riscduino_board/custom_board/riscduino/variants/standard/pins_arduino.h |
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| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/Makefile |
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| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/run_iverilog |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/benchmarks/coremark/Makefile |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.c |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/Makefile |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_1.c |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_2.c |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/hello/Makefile |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/hello/hello.c |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/isr_sample/Makefile |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/isr_sample/timer.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_compliance/Makefile |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_compliance/aw_test_macros.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_io.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_test.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test_macros.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_compliance/test_macros.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_isa/Makefile |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_isa/riscv_test.h |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_isa/rv32_tests.inc |
| /root/riscduino-dcore_d3_3/verilog/dv/riscv_regress/tests/riscv_isa/test_macros.h |
| /root/riscduino-dcore_d3_3/verilog/dv/user_aes/aes.c |
| /root/riscduino-dcore_d3_3/verilog/dv/user_aes/aes.h |
| /root/riscduino-dcore_d3_3/verilog/dv/user_rtc/pli_rtc.c |
| /root/riscduino-dcore_d3_3/verilog/dv/user_sspi/sspi_task.v |
| /root/riscduino-dcore_d3_3/verilog/dv/user_usb/tests/usb_test1.v |
| /root/riscduino-dcore_d3_3/verilog/dv/user_usb/tests/usb_test2.v |
| /root/riscduino-dcore_d3_3/verilog/dv/user_usb/tests/usb_test3.v |
| /root/riscduino-dcore_d3_3/verilog/includes/includes.gl.caravel_user_project |
| /root/riscduino-dcore_d3_3/verilog/includes/includes.gl.lib |
| /root/riscduino-dcore_d3_3/verilog/includes/includes.rtl.caravel_user_project |
| /root/riscduino-dcore_d3_3/verilog/includes/includes.rtl.lib |
| /root/riscduino-dcore_d3_3/verilog/rtl/bus_repeater.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/user_params.svh |
| /root/riscduino-dcore_d3_3/verilog/rtl/user_reg_map.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/dac/src/dac_top.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/openlane/fpu_sp_top/base.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/openlane/fpu_top/base.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/synth/base.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/synth/scripts/libtrim.pl |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/verilog/dv/filelist_gate.f |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/verilog/dv/filelist_rtl.f |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/verilog/dv/fpu_sp.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/verilog/dv/fpu_sp_tc.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/verilog/dv/tb_top.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/verilog/dv/test_fpu_sp.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/fpu/verilog/rtl/fpu_parms.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/gpio/src/gpio_intr.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/lib/ctech_cells.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/lib/pulse_gen_type1.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/lib/pulse_gen_type2.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/mbist/run_iverilog |
| /root/riscduino-dcore_d3_3/verilog/rtl/mbist/run_verilator |
| /root/riscduino-dcore_d3_3/verilog/rtl/pwm/src/pwm.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/pwm/src/pwm_cfg_dglitch.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/qspim/lib/ctech_cells.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/qspim/model/cy15b104qs.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/qspim/model/s25fl256s.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/qspim/model/spiram.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/qspim/openlane/qspim_top/base.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/qspim/openlane/qspim_top/interactive.tcl |
| /root/riscduino-dcore_d3_3/verilog/rtl/qspim/sdc/qspim_top.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/qspim/tb/run_iverilog |
| /root/riscduino-dcore_d3_3/verilog/rtl/rtc/openlane/rtc_top/base.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/rtc/verilog/dv/user_rtc/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/rtc/verilog/dv/user_rtc/pli_rtc.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/rtc/verilog/rtl/lib/ctech_cells.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/sar_adc/ACMP.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/sar_adc/ACMP_HVL.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/sar_adc/DAC_8BIT.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/sar_adc/SAR.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/sar_adc/sar_adc.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/security_core/openlane/aes_top/base.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/security_core/openlane/aes_top/interactive.tcl |
| /root/riscduino-dcore_d3_3/verilog/rtl/security_core/verilog/dv/user_aes/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/security_core/verilog/includes/includes.rtl |
| /root/riscduino-dcore_d3_3/verilog/rtl/security_core/verilog/rtl/lib/ctech_cells.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/sspim/src/filelist_spi.f |
| /root/riscduino-dcore_d3_3/verilog/rtl/sspim/src/sspim_cfg.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/sspim/src/sspim_clkgen.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/sspim/src/sspim_ctl.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/sspim/src/sspim_if.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/timer/src/timer.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/uart2wb/src/run_verilog |
| /root/riscduino-dcore_d3_3/verilog/rtl/uart2wb/src/uart_auto_det.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/uart2wb/src/uart_msg_handler.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/usb1_host/src/filelist.f |
| /root/riscduino-dcore_d3_3/verilog/rtl/ws281x/src/ws281x_driver.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/run_iverilog |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/openlane/ycr2_core/base.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/openlane/ycr2_intf/base.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/openlane/ycr2c/base.sdc |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/iverilog_vpi/system.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/coremark/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/coremark/core_portme.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/coremark/core_portme.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/dhry.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/dhry_1.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/dhry_2.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/hello/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/hello/hello.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/isr_sample/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/isr_sample/isr_sample.S |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/isr_sample/timer.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/aw_test_macros.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/compliance_io.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/compliance_test.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/riscv_test.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/riscv_test_macros.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/test_macros.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/Makefile |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/riscv_test.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/rv32_tests.inc |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/test_macros.h |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/verilator_wrap/ycr_ahb_wrapper.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/verilator_wrap/ycr_axi_wrapper.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/sim/verilator_wrap/ycr_wb_wrapper.c |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/src/core.files |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/src/wb_top.files |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/src/cache/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/src/cache/src/core/ycr_cache_defs.svh |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/src/cache/src/model/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/src/includes/ycr_cache_defs.svh |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/ahb_tb.files |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/axi_tb.files |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/uprj_netlists.v |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/wb_tb.files |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_ahb.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_axi.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_wb.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_ahb.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_axi.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_runtests.sv |
| /root/riscduino-dcore_d3_3/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_wb.sv |