| 2022-12-13 16:17:21 - [INFO] - {{Project Git Info}} Repository: https://github.com/dineshannayya/riscduino_dcore.git | Branch: main | Commit: ff7fa67219f0525ec8b83b3f155fad905b9af6cc |
| 2022-12-13 16:17:21 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: riscduino-dcore_d3_3 |
| 2022-12-13 16:17:24 - [INFO] - {{Project Type Info}} digital |
| 2022-12-13 16:17:25 - [INFO] - {{Project GDS Info}} user_project_wrapper: 2d5104bdc37eb211f6c12b362954099753608366 |
| 2022-12-13 16:17:25 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340 |
| 2022-12-13 16:17:25 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f |
| 2022-12-13 16:17:25 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/logs' |
| 2022-12-13 16:17:25 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea] |
| 2022-12-13 16:17:25 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License |
| 2022-12-13 16:17:26 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dcore_d3_3. |
| 2022-12-13 16:17:26 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root. |
| 2022-12-13 16:17:27 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dcore_d3_3. |
| 2022-12-13 16:17:27 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules |
| 2022-12-13 16:17:27 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dcore_d3_3/verilog/dv/common/bfm/usb_device/core/usb1d_ctrl.v): 'utf-8' codec can't decode byte 0x96 in position 5130: invalid start byte |
| 2022-12-13 16:17:27 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dcore_d3_3/verilog/dv/common/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte |
| 2022-12-13 16:17:27 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 460 non-compliant file(s) with the SPDX Standard. |
| 2022-12-13 16:17:27 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino-dcore_d3_3/run_regress', 'riscduino-dcore_d3_3/deps/timing-scripts/timing.mk', 'riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping-mpw2-calibre.tcl', 'riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping-mpw2.tcl', 'riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping-mpw5-calibre.tcl', 'riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping-mpw7.tcl', 'riscduino-dcore_d3_3/deps/timing-scripts/env/caravel_spef_mapping.tcl', 'riscduino-dcore_d3_3/deps/timing-scripts/env/common.tcl', 'riscduino-dcore_d3_3/deps/timing-scripts/env/f.tcl', 'riscduino-dcore_d3_3/deps/timing-scripts/env/s.tcl', 'riscduino-dcore_d3_3/deps/timing-scripts/env/t.tcl', 'riscduino-dcore_d3_3/deps/timing-scripts/scripts/compare_reports.py', 'riscduino-dcore_d3_3/deps/timing-scripts/scripts/generate_spef_mapping.py', 'riscduino-dcore_d3_3/deps/timing-scripts/scripts/get_macros.py', 'riscduino-dcore_d3_3/deps/timing-scripts/scripts/pdk_helpers.py'] |
| 2022-12-13 16:17:27 - [INFO] - For the full SPDX compliance report check: riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/logs/spdx_compliance_report.log |
| 2022-12-13 16:17:27 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile |
| 2022-12-13 16:17:27 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid. |
| 2022-12-13 16:17:27 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default |
| 2022-12-13 16:17:27 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md' |
| 2022-12-13 16:17:29 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds' |
| 2022-12-13 16:17:29 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation |
| 2022-12-13 16:17:30 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate. |
| 2022-12-13 16:17:30 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency |
| 2022-12-13 16:17:38 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power |
| 2022-12-13 16:17:38 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks. |
| 2022-12-13 16:17:38 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports |
| 2022-12-13 16:17:38 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (21 instances). |
| 2022-12-13 16:17:38 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural. |
| 2022-12-13 16:17:38 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist. |
| 2022-12-13 16:17:38 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power |
| 2022-12-13 16:17:38 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types. |
| 2022-12-13 16:17:38 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks. |
| 2022-12-13 16:17:39 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid. |
| 2022-12-13 16:17:39 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines |
| 2022-12-13 16:17:39 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'riscduino-dcore_d3_3/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v'] |
| 2022-12-13 16:17:40 - [INFO] - GPIO-DEFINES report path: riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/outputs/reports/gpio_defines.report |
| 2022-12-13 16:17:40 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid. |
| 2022-12-13 16:17:40 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR |
| 2022-12-13 16:21:55 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/outputs/user_project_wrapper.xor.gds |
| 2022-12-13 16:21:55 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations. |
| 2022-12-13 16:21:55 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC |
| 2022-12-13 17:02:46 - [INFO] - 0 DRC violations |
| 2022-12-13 17:02:46 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-13 17:02:46 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL |
| 2022-12-13 17:02:46 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-13 17:02:46 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-dcore_d3_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/outputs/reports/klayout_feol_check.xml -rd feol=true >& riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/logs/klayout_feol_check.log |
| 2022-12-13 17:06:27 - [INFO] - No DRC Violations found |
| 2022-12-13 17:06:27 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-13 17:06:27 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL |
| 2022-12-13 17:06:27 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-13 17:06:27 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-dcore_d3_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/outputs/reports/klayout_beol_check.xml -rd beol=true >& riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/logs/klayout_beol_check.log |
| 2022-12-13 17:34:42 - [INFO] - No DRC Violations found |
| 2022-12-13 17:34:42 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-13 17:34:42 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid |
| 2022-12-13 17:34:42 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-13 17:34:42 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-dcore_d3_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true >& riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/logs/klayout_offgrid_check.log |
| 2022-12-13 17:40:13 - [INFO] - No DRC Violations found |
| 2022-12-13 17:40:13 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-13 17:40:13 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density |
| 2022-12-13 17:40:13 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-13 17:40:13 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=riscduino-dcore_d3_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/outputs/reports/klayout_met_min_ca_density_check.xml >& riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/logs/klayout_met_min_ca_density_check.log |
| 2022-12-13 17:42:30 - [INFO] - No DRC Violations found |
| 2022-12-13 17:42:30 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-13 17:42:30 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing |
| 2022-12-13 17:42:30 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-13 17:42:30 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=riscduino-dcore_d3_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=user_project_wrapper >& riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/logs/klayout_pin_label_purposes_overlapping_drawing_check.log |
| 2022-12-13 17:43:16 - [INFO] - No DRC Violations found |
| 2022-12-13 17:43:16 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-13 17:43:16 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea |
| 2022-12-13 17:43:16 - [INFO] - in CUSTOM klayout_gds_drc_check |
| 2022-12-13 17:43:16 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=riscduino-dcore_d3_3/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/outputs/reports/klayout_zeroarea_check.xml -rd cleaned_output=riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/outputs/user_project_wrapper_no_zero_areas.gds >& riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/logs/klayout_zeroarea_check.log |
| 2022-12-13 17:43:42 - [INFO] - No DRC Violations found |
| 2022-12-13 17:43:42 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-12-13 17:43:42 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino-dcore_d3_3/jobs/mpw_precheck/b9c6eb6b-aee6-4953-9615-93621c3e1680/logs' |
| 2022-12-13 17:43:42 - [INFO] - {{SUCCESS}} All Checks Passed !!! |
