Update openlane/user_proj_example/config.json

openlane/user_proj_example/config.json

diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 370d74c..9fb9914 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -1,7 +1,7 @@
 {
     "DESIGN_NAME": "user_proj_example",
     "DESIGN_IS_CORE": 0,
-    "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
+    "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/yonga_can_top.v", "dir::../../verilog/rtl/yonga_can_controller.v", "dir::../../verilog/rtl/yonga_can_packetizer.v", "dir::../../verilog/rtl/yonga_can_pulse_gen.v", "dir::../../verilog/rtl/user_proj_example.v"],
     "CLOCK_PERIOD": 10,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_NET": "counter.clk",