Update includes.rtl.caravel_user_project

verilog/includes/includes.rtl.caravel_user_project

diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..561ac87 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,8 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
 -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-
+-v $(USER_PROJECT_VERILOG)/rtl/yonga_can_top.v
+-v $(USER_PROJECT_VERILOG)/rtl/yonga_can_controller.v
+-v $(USER_PROJECT_VERILOG)/rtl/yonga_can_packetizer.v
+-v $(USER_PROJECT_VERILOG)/rtl/yonga_can_pulse_gen.v
  
\ No newline at end of file