verilog/includes/includes.rtl.caravel_user_project

# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-v $(USER_PROJECT_VERILOG)/rtl/yonga_can_top.v
-v $(USER_PROJECT_VERILOG)/rtl/yonga_can_controller.v
-v $(USER_PROJECT_VERILOG)/rtl/yonga_can_packetizer.v
-v $(USER_PROJECT_VERILOG)/rtl/yonga_can_pulse_gen.v