update config.json
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json index 3c446f2..8f0d82d 100644 --- a/openlane/user_proj_example/config.json +++ b/openlane/user_proj_example/config.json
@@ -1,13 +1,13 @@ { "DESIGN_NAME": "user_proj_example", "DESIGN_IS_CORE": 0, - "VERILOG_FILES": "/home/jeffdi/caravel-gf180mcu/verilog/rtl/defines.v /home/jeffdi/caravel_user_project_gf/verilog/rtl/user_proj_example.v", + "VERILOG_FILES": ["dir::project_root/verilog/rtl/defines.v", "dir::project_root/verilog/rtl/user_proj_example.v"], "CLOCK_PERIOD": 10, "CLOCK_PORT": "wb_clk_i", "CLOCK_NET": "counter.clk", "FP_SIZING": "absolute", "DIE_AREA": "0 0 900 600", - "FP_PIN_ORDER_CFG": "/home/jeffdi/caravel_user_project_gf/openlane/user_proj_example/pin_order.cfg", + "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", "PL_BASIC_PLACEMENT": 0, "PL_TARGET_DENSITY": 0.55, "VDD_NETS": ["vccd1"],
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json index b141a47..3379f46 100644 --- a/openlane/user_project_wrapper/config.json +++ b/openlane/user_project_wrapper/config.json
@@ -1,14 +1,14 @@ { "DESIGN_NAME": "user_project_wrapper", - "VERILOG_FILES": "/home/jeffdi/caravel-gf180mcu/verilog/rtl/defines.v /home/jeffdi/caravel_user_project_gf/verilog/rtl/user_project_wrapper.v", + "VERILOG_FILES": ["dir::project_root/verilog/rtl/defines.v", "dir::project_root/verilog/rtl/user_project_wrapper.v"], "CLOCK_PERIOD": 10, "CLOCK_PORT": "user_clock2", "CLOCK_NET": "mprj.clk", "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1", - "MACRO_PLACEMENT_CFG": "/home/jeffdi/caravel_user_project_gf/openlane/user_project_wrapper/macro.cfg", - "VERILOG_FILES_BLACKBOX": "/home/jeffdi/caravel-gf180mcu/verilog/rtl/defines.v /home/jeffdi/caravel_user_project_gf/verilog/rtl/user_proj_example.v", - "EXTRA_LEFS": "/home/jeffdi/caravel_user_project_gf/lef/user_proj_example.lef", - "EXTRA_GDS_FILES": "/home/jeffdi/caravel_user_project_gf/gds/user_proj_example.gds", + "MACRO_PLACEMENT_CFG": "dir::macro.cfg", + "VERILOG_FILES_BLACKBOX": ["dir::project_root/verilog/rtl/defines.v", "dir::project_root/verilog/rtl/user_proj_example.v"], + "EXTRA_LEFS": "dir::project_root/lef/user_proj_example.lef", + "EXTRA_GDS_FILES": "dir::project_root/gds/user_proj_example.gds", "FP_PDN_CHECK_NODES": 0, "SYNTH_ELABORATE_ONLY": 1, "PL_RANDOM_GLB_PLACEMENT": 1, @@ -74,7 +74,7 @@ "FP_PDN_ENABLE_RAILS": 0, "RT_MAX_LAYER": "Metal4", "DIE_AREA": "0 0 3000 3000", - "FP_PIN_ORDER_CFG": "/home/jeffdi/caravel_user_project_gf/openlane/user_project_wrapper/pin_order.cfg", + "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", "PL_OPENPHYSYN_OPTIMIZATIONS": 0, "DIODE_INSERTION_STRATEGY": 0, "FP_PDN_CHECK_NODES": 0,
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v new file mode 100644 index 0000000..44a29a0 --- /dev/null +++ b/verilog/rtl/defines.v
@@ -0,0 +1,66 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`ifndef __GLOBAL_DEFINE_H +// Global parameters +`define __GLOBAL_DEFINE_H + +`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */ +`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */ +`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2) + +`define MPRJ_PWR_PADS_1 2 /* vdda1, vccd1 enable/disable control */ +`define MPRJ_PWR_PADS_2 2 /* vdda2, vccd2 enable/disable control */ +`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2) + +// Analog pads are only used by the "caravan" module and associated +// modules such as user_analog_project_wrapper and chip_io_alt. + +`define ANALOG_PADS_1 5 +`define ANALOG_PADS_2 6 + +`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2) + +// Size of soc_mem_synth + +// Type and size of soc_mem +// `define USE_OPENRAM +`define USE_CUSTOM_DFFRAM +// don't change the following without double checking addr widths +`define MEM_WORDS 256 + +// Number of columns in the custom memory; takes one of three values: +// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB +`define DFFRAM_WSIZE 4 +`define DFFRAM_USE_LATCH 0 + +// not really parameterized but just to easily keep track of the number +// of ram_block across different modules +`define RAM_BLOCKS 1 + +// Clock divisor default value +`define CLK_DIV 3'b010 + +// GPIO control default mode and enable for most I/Os +// Most I/Os set to be user input pins on startup. +// NOTE: To be modified, with GPIOs 5 to 35 being set from a build-time- +// programmable block. +`define MGMT_INIT 1'b0 +`define OENB_INIT 1'b0 +`define DM_INIT 3'b001 + +`endif // __GLOBAL_DEFINE_H \ No newline at end of file