Update sim tests to match how caravel now does them
diff --git a/verilog/dv/microwatt/jtag/jtag_tb.v b/verilog/dv/microwatt/jtag/jtag_tb.v index 440c3ce..4e63175 100644 --- a/verilog/dv/microwatt/jtag/jtag_tb.v +++ b/verilog/dv/microwatt/jtag/jtag_tb.v
@@ -21,10 +21,6 @@ `timescale 1 ns / 1 ps -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" - module jtag_expect_idcode ( input tdo, input tck, @@ -232,7 +228,7 @@ .resetb (RSTB) ); - spiflash #( + spiflash_microwatt #( .FILENAME("microwatt.hex") ) spiflash_microwatt ( .csb(user_flash_csb),
diff --git a/verilog/dv/microwatt/make.env b/verilog/dv/microwatt/make.env index 5ada673..eae0f2b 100644 --- a/verilog/dv/microwatt/make.env +++ b/verilog/dv/microwatt/make.env
@@ -15,22 +15,16 @@ # SPDX-License-Identifier: Apache-2.0 ## PDK -PDK_PATH = $(PDK_ROOT)/sky130A +export PDK ?= sky130A +export PDK_PATH = $(PDK_ROOT)/$(PDK) ## Caravel Pointers -CARAVEL_ROOT ?= ../../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) +export CARAVEL_ROOT ?= ../../../../caravel +export CARAVEL_PATH = $(CARAVEL_ROOT)/verilog -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_MGMT_VERILOG_PATH = ../../../../mgmt_core_wrapper/verilog -CARAVEL_MGMT_RTL_PATH = $(CARAVEL_MGMT_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +export VERILOG_PATH = $(CARAVEL_ROOT)/../mgmt_core_wrapper/verilog -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_BEHAVIOURAL_MODELS = ../ +export USER_PROJECT_VERILOG = $(CARAVEL_ROOT)/../verilog POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu- POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include
diff --git a/verilog/dv/microwatt/make.rules b/verilog/dv/microwatt/make.rules index 3d17955..ec00c93 100644 --- a/verilog/dv/microwatt/make.rules +++ b/verilog/dv/microwatt/make.rules
@@ -21,16 +21,16 @@ %.vvp: %_tb.v microwatt.hex check-env ifeq ($(SIM),RTL) - iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(CARAVEL_MGMT_RTL_PATH) \ + iverilog $(SIM_DEFINES) \ + -l$(USER_PROJECT_VERILOG)/rtl/user_defines.v \ + -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.caravel_user_project \ $< -o $@ else - iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(CARAVEL_MGMT_RTL_PATH) -I $(CARAVEL_MGMT_VERILOG_PATH) \ + iverilog $(SIM_DEFINES) -DGL \ + -l$(USER_PROJECT_VERILOG)/rtl/user_defines.v \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.caravel_user_project \ $< -o $@ endif @@ -41,8 +41,8 @@ ifndef PDK_ROOT $(error PDK_ROOT is undefined, please export it before running make) endif -ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) - $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) +ifeq (,$(wildcard $(PDK_ROOT)/$(PDK))) + $(error $(PDK_ROOT)/$(PDK) not found, please install pdk before running make) endif clean:
diff --git a/verilog/dv/microwatt/memory_test/memory_test_tb.v b/verilog/dv/microwatt/memory_test/memory_test_tb.v index 99929ce..c73f812 100644 --- a/verilog/dv/microwatt/memory_test/memory_test_tb.v +++ b/verilog/dv/microwatt/memory_test/memory_test_tb.v
@@ -20,11 +20,6 @@ `timescale 1 ns / 1 ps -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" -`include "tbuart_modified.v" - module memory_test; reg clock; reg RSTB; @@ -146,7 +141,7 @@ .resetb (RSTB) ); - spiflash #( + spiflash_microwatt #( .FILENAME("microwatt.hex") ) spiflash_microwatt ( .csb(user_flash_csb), @@ -157,7 +152,7 @@ .io3() // not used ); - tbuart_modified #( + tbuart_microwatt #( .baud_rate(115200) ) tbuart ( .ser_rx(uart_tx)
diff --git a/verilog/dv/microwatt/minimal/minimal_tb.v b/verilog/dv/microwatt/minimal/minimal_tb.v index 9fdfebf..d00f86f 100644 --- a/verilog/dv/microwatt/minimal/minimal_tb.v +++ b/verilog/dv/microwatt/minimal/minimal_tb.v
@@ -20,10 +20,6 @@ `timescale 1 ns / 1 ps -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" - module minimal; reg clock; reg RSTB; @@ -147,7 +143,7 @@ .resetb (RSTB) ); - spiflash #( + spiflash_microwatt #( .FILENAME("microwatt.hex") ) spiflash_microwatt ( .csb(user_flash_csb),
diff --git a/verilog/dv/microwatt/multiply/multiply_tb.v b/verilog/dv/microwatt/multiply/multiply_tb.v index 2e72a5a..7249897 100644 --- a/verilog/dv/microwatt/multiply/multiply_tb.v +++ b/verilog/dv/microwatt/multiply/multiply_tb.v
@@ -20,11 +20,6 @@ `timescale 1 ns / 1 ps -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" -`include "tbuart_modified.v" - module multiply_test; reg clock; reg RSTB; @@ -146,7 +141,7 @@ .resetb (RSTB) ); - spiflash #( + spiflash_microwatt #( .FILENAME("microwatt.hex") ) spiflash_microwatt ( .csb(user_flash_csb), @@ -157,7 +152,7 @@ .io3() // not used ); - tbuart_modified #( + tbuart_microwatt #( .baud_rate(115200) ) tbuart ( .ser_rx(uart_tx)
diff --git a/verilog/dv/microwatt/multiply/tbuart_modified.v b/verilog/dv/microwatt/multiply/tbuart_modified.v deleted file mode 100644 index ad9b8f9..0000000 --- a/verilog/dv/microwatt/multiply/tbuart_modified.v +++ /dev/null
@@ -1,83 +0,0 @@ -`default_nettype none -/* - * PicoSoC - A simple example SoC using PicoRV32 - * - * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -`timescale 1 ns / 1 ps - -/* tbuart --- mimic an external UART display, operating at 9600 baud */ -/* and accepting ASCII characters for display. */ - -/* To do: Match a known UART 3.3V 16x2 LCD display. However, it */ -/* should be possible on a testing system to interface to the UART */ -/* pins on a Raspberry Pi, also running at 3.3V. */ - -module tbuart_modified # ( - parameter baud_rate = 115200 -) ( - input ser_rx -); - reg [3:0] recv_state; - reg [2:0] recv_divcnt; - reg [7:0] recv_pattern; - - reg clk; - - initial begin - clk <= 1'b0; - recv_state <= 0; - recv_divcnt <= 0; - recv_pattern <= 0; - end - - // Our simulation is in nanosecond steps and we want 5 clocks per bit, - // ie 10 clock transitions - always #(1000000000/baud_rate/10) clk <= (clk === 1'b0); - - always @(posedge clk) begin - recv_divcnt <= recv_divcnt + 1; - case (recv_state) - 0: begin - if (!ser_rx) - recv_state <= 1; - recv_divcnt <= 0; - end - 1: begin - if (2*recv_divcnt > 3'd3) begin - recv_state <= 2; - recv_divcnt <= 0; - end - end - 10: begin - if (recv_divcnt > 3'd3) begin - recv_state <= 0; - $write("%c", recv_pattern); - $fflush(); - end - end - default: begin - if (recv_divcnt > 3'd3) begin - recv_pattern <= {ser_rx, recv_pattern[7:1]}; - recv_state <= recv_state + 1; - recv_divcnt <= 0; - end - end - endcase - end - -endmodule
diff --git a/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v b/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v index 51f647e..48fad39 100644 --- a/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v +++ b/verilog/dv/microwatt/simplebus_micropython/simplebus_micropython_tb.v
@@ -20,11 +20,6 @@ `timescale 1 ns / 1 ps -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" -`include "tbuart_modified.v" - module RAM_tb #( parameter BITS = 64, parameter WORDS = 512*1024/8, @@ -379,7 +374,7 @@ .resetb (RSTB) ); - spiflash #( + spiflash_microwatt #( .FILENAME("microwatt.hex") ) spiflash_microwatt ( .csb(user_flash_csb), @@ -398,7 +393,7 @@ .ext_bus_pty_out(ext_bus_pty_out) ); - tbuart_modified #( + tbuart_microwatt #( .baud_rate(115200) ) tbuart ( .ser_rx(uart_tx)
diff --git a/verilog/dv/microwatt/simplebus_micropython/tbuart_modified.v b/verilog/dv/microwatt/simplebus_micropython/tbuart_modified.v deleted file mode 100644 index ad9b8f9..0000000 --- a/verilog/dv/microwatt/simplebus_micropython/tbuart_modified.v +++ /dev/null
@@ -1,83 +0,0 @@ -`default_nettype none -/* - * PicoSoC - A simple example SoC using PicoRV32 - * - * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -`timescale 1 ns / 1 ps - -/* tbuart --- mimic an external UART display, operating at 9600 baud */ -/* and accepting ASCII characters for display. */ - -/* To do: Match a known UART 3.3V 16x2 LCD display. However, it */ -/* should be possible on a testing system to interface to the UART */ -/* pins on a Raspberry Pi, also running at 3.3V. */ - -module tbuart_modified # ( - parameter baud_rate = 115200 -) ( - input ser_rx -); - reg [3:0] recv_state; - reg [2:0] recv_divcnt; - reg [7:0] recv_pattern; - - reg clk; - - initial begin - clk <= 1'b0; - recv_state <= 0; - recv_divcnt <= 0; - recv_pattern <= 0; - end - - // Our simulation is in nanosecond steps and we want 5 clocks per bit, - // ie 10 clock transitions - always #(1000000000/baud_rate/10) clk <= (clk === 1'b0); - - always @(posedge clk) begin - recv_divcnt <= recv_divcnt + 1; - case (recv_state) - 0: begin - if (!ser_rx) - recv_state <= 1; - recv_divcnt <= 0; - end - 1: begin - if (2*recv_divcnt > 3'd3) begin - recv_state <= 2; - recv_divcnt <= 0; - end - end - 10: begin - if (recv_divcnt > 3'd3) begin - recv_state <= 0; - $write("%c", recv_pattern); - $fflush(); - end - end - default: begin - if (recv_divcnt > 3'd3) begin - recv_pattern <= {ser_rx, recv_pattern[7:1]}; - recv_state <= recv_state + 1; - recv_divcnt <= 0; - end - end - endcase - end - -endmodule
diff --git a/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v b/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v index 8045e0a..6e646b0 100644 --- a/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v +++ b/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v
@@ -20,11 +20,6 @@ `timescale 1 ns / 1 ps -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" - - module simplebus_tb ( input clk, @@ -314,7 +309,7 @@ .resetb (RSTB) ); - spiflash #( + spiflash_microwatt #( .FILENAME("microwatt.hex") ) spiflash_microwatt ( .csb(user_flash_csb),
diff --git a/verilog/dv/microwatt/spi_flash/spi_flash_tb.v b/verilog/dv/microwatt/spi_flash/spi_flash_tb.v index 20cdbbb..904e9e7 100644 --- a/verilog/dv/microwatt/spi_flash/spi_flash_tb.v +++ b/verilog/dv/microwatt/spi_flash/spi_flash_tb.v
@@ -20,11 +20,6 @@ `timescale 1 ns / 1 ps -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" -`include "tbuart_modified.v" - module spi_flash; reg clock; reg RSTB; @@ -147,7 +142,7 @@ .resetb (RSTB) ); - spiflash #( + spiflash_microwatt #( .FILENAME("microwatt.hex") ) spiflash_microwatt ( .csb(user_flash_csb), @@ -156,7 +151,7 @@ .io1(user_flash_io1) ); - tbuart_modified #( + tbuart_microwatt #( .baud_rate(115200) ) tbuart ( .ser_rx(uart_tx)
diff --git a/verilog/dv/microwatt/spi_flash/tbuart_modified.v b/verilog/dv/microwatt/spi_flash/tbuart_modified.v deleted file mode 100644 index ad9b8f9..0000000 --- a/verilog/dv/microwatt/spi_flash/tbuart_modified.v +++ /dev/null
@@ -1,83 +0,0 @@ -`default_nettype none -/* - * PicoSoC - A simple example SoC using PicoRV32 - * - * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -`timescale 1 ns / 1 ps - -/* tbuart --- mimic an external UART display, operating at 9600 baud */ -/* and accepting ASCII characters for display. */ - -/* To do: Match a known UART 3.3V 16x2 LCD display. However, it */ -/* should be possible on a testing system to interface to the UART */ -/* pins on a Raspberry Pi, also running at 3.3V. */ - -module tbuart_modified # ( - parameter baud_rate = 115200 -) ( - input ser_rx -); - reg [3:0] recv_state; - reg [2:0] recv_divcnt; - reg [7:0] recv_pattern; - - reg clk; - - initial begin - clk <= 1'b0; - recv_state <= 0; - recv_divcnt <= 0; - recv_pattern <= 0; - end - - // Our simulation is in nanosecond steps and we want 5 clocks per bit, - // ie 10 clock transitions - always #(1000000000/baud_rate/10) clk <= (clk === 1'b0); - - always @(posedge clk) begin - recv_divcnt <= recv_divcnt + 1; - case (recv_state) - 0: begin - if (!ser_rx) - recv_state <= 1; - recv_divcnt <= 0; - end - 1: begin - if (2*recv_divcnt > 3'd3) begin - recv_state <= 2; - recv_divcnt <= 0; - end - end - 10: begin - if (recv_divcnt > 3'd3) begin - recv_state <= 0; - $write("%c", recv_pattern); - $fflush(); - end - end - default: begin - if (recv_divcnt > 3'd3) begin - recv_pattern <= {ser_rx, recv_pattern[7:1]}; - recv_state <= recv_state + 1; - recv_divcnt <= 0; - end - end - endcase - end - -endmodule
diff --git a/verilog/dv/microwatt/uart/uart_tb.v b/verilog/dv/microwatt/uart/uart_tb.v index f39e3c5..b67f8fb 100644 --- a/verilog/dv/microwatt/uart/uart_tb.v +++ b/verilog/dv/microwatt/uart/uart_tb.v
@@ -20,10 +20,6 @@ `timescale 1 ns / 1 ps -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" - module tbuart_expect_seven # ( parameter baud_rate = 115200 ) ( @@ -214,7 +210,7 @@ .resetb (RSTB) ); - spiflash #( + spiflash_microwatt #( .FILENAME("microwatt.hex") ) spiflash_microwatt ( .csb(user_flash_csb),
diff --git a/verilog/rtl/Microwatt_FP_DFFRFile.v b/verilog/dv/vip/Microwatt_FP_DFFRFile.v similarity index 100% rename from verilog/rtl/Microwatt_FP_DFFRFile.v rename to verilog/dv/vip/Microwatt_FP_DFFRFile.v
diff --git a/verilog/rtl/RAM32_1RW1R.v b/verilog/dv/vip/RAM32_1RW1R.v similarity index 100% rename from verilog/rtl/RAM32_1RW1R.v rename to verilog/dv/vip/RAM32_1RW1R.v
diff --git a/verilog/rtl/RAM512.v b/verilog/dv/vip/RAM512.v similarity index 100% rename from verilog/rtl/RAM512.v rename to verilog/dv/vip/RAM512.v
diff --git a/verilog/rtl/multiply_add_64x64.v b/verilog/dv/vip/multiply_add_64x64.v similarity index 100% rename from verilog/rtl/multiply_add_64x64.v rename to verilog/dv/vip/multiply_add_64x64.v
diff --git a/verilog/dv/vip/spiflash_microwatt.v b/verilog/dv/vip/spiflash_microwatt.v new file mode 100644 index 0000000..fcff00a --- /dev/null +++ b/verilog/dv/vip/spiflash_microwatt.v
@@ -0,0 +1,447 @@ +`default_nettype none +/* + * SPDX-FileCopyrightText: 2017 Clifford Wolf + * + * PicoSoC - A simple example SoC using PicoRV32 + * + * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * SPDX-License-Identifier: ISC + */ + +`timescale 1 ns / 1 ps + +// +// Simple SPI flash simulation model +// +// This model samples io input signals 1ns before the SPI clock edge and +// updates output signals 1ns after the SPI clock edge. +// +// Supported commands: +// AB, B9, FF, 03, BB, EB, ED +// +// Well written SPI flash data sheets: +// Cypress S25FL064L http://www.cypress.com/file/316661/download +// Cypress S25FL128L http://www.cypress.com/file/316171/download +// + +module spiflash_microwatt #( + parameter FILENAME = "firmware.hex" +)( + input csb, + input clk, + inout io0, // MOSI + inout io1, // MISO + inout io2, + inout io3 +); + localparam verbose = 0; + localparam integer latency = 8; + + reg [7:0] buffer; + reg [3:0] reset_count = 0; + reg [3:0] reset_monitor = 0; + integer bitcount = 0; + integer bytecount = 0; + integer dummycount = 0; + + reg [7:0] spi_cmd; + reg [7:0] xip_cmd = 0; + reg [23:0] spi_addr; + + reg [7:0] spi_in; + reg [7:0] spi_out; + reg spi_io_vld; + + reg powered_up = 1; + + localparam [3:0] mode_spi = 1; + localparam [3:0] mode_dspi_rd = 2; + localparam [3:0] mode_dspi_wr = 3; + localparam [3:0] mode_qspi_rd = 4; + localparam [3:0] mode_qspi_wr = 5; + localparam [3:0] mode_qspi_ddr_rd = 6; + localparam [3:0] mode_qspi_ddr_wr = 7; + + reg [3:0] mode = 0; + reg [3:0] next_mode = 0; + + reg io0_oe = 0; + reg io1_oe = 0; + reg io2_oe = 0; + reg io3_oe = 0; + + reg io0_dout = 0; + reg io1_dout = 0; + reg io2_dout = 0; + reg io3_dout = 0; + + assign #1 io0 = io0_oe ? io0_dout : 1'bz; + assign #1 io1 = io1_oe ? io1_dout : 1'bz; + assign #1 io2 = io2_oe ? io2_dout : 1'bz; + assign #1 io3 = io3_oe ? io3_dout : 1'bz; + + wire io0_delayed; + wire io1_delayed; + wire io2_delayed; + wire io3_delayed; + + assign #1 io0_delayed = io0; + assign #1 io1_delayed = io1; + assign #1 io2_delayed = io2; + assign #1 io3_delayed = io3; + + // 16 MB (128Mb) Flash + reg [7:0] memory [0:16*1024*1024-1]; + + initial begin + $display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x", + memory[1048576], memory[1048577], memory[1048578], + memory[1048579], memory[1048580]); + $display("Reading %s", FILENAME); + $readmemh(FILENAME, memory); + $display("%s loaded into memory", FILENAME); + $display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x", + memory[1048576], memory[1048577], memory[1048578], + memory[1048579], memory[1048580]); + end + + task spi_action; + begin + spi_in = buffer; + + if (bytecount == 1) begin + spi_cmd = buffer; + + if (spi_cmd == 8'h ab) + powered_up = 1; + + if (spi_cmd == 8'h b9) + powered_up = 0; + + if (spi_cmd == 8'h ff) + xip_cmd = 0; + end + + if (powered_up && spi_cmd == 'h 03) begin + if (bytecount == 2) + spi_addr[23:16] = buffer; + + if (bytecount == 3) + spi_addr[15:8] = buffer; + + if (bytecount == 4) + spi_addr[7:0] = buffer; + + if (bytecount >= 4) begin + buffer = memory[spi_addr]; + spi_addr = spi_addr + 1; + end + end + + if (powered_up && spi_cmd == 'h bb) begin + if (bytecount == 1) + mode = mode_dspi_rd; + + if (bytecount == 2) + spi_addr[23:16] = buffer; + + if (bytecount == 3) + spi_addr[15:8] = buffer; + + if (bytecount == 4) + spi_addr[7:0] = buffer; + + if (bytecount == 5) begin + xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00; + mode = mode_dspi_wr; + dummycount = latency; + end + + if (bytecount >= 5) begin + buffer = memory[spi_addr]; + spi_addr = spi_addr + 1; + end + end + + if (powered_up && spi_cmd == 'h eb) begin + if (bytecount == 1) + mode = mode_qspi_rd; + + if (bytecount == 2) + spi_addr[23:16] = buffer; + + if (bytecount == 3) + spi_addr[15:8] = buffer; + + if (bytecount == 4) + spi_addr[7:0] = buffer; + + if (bytecount == 5) begin + xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00; + mode = mode_qspi_wr; + dummycount = latency; + end + + if (bytecount >= 5) begin + buffer = memory[spi_addr]; + spi_addr = spi_addr + 1; + end + end + + if (powered_up && spi_cmd == 'h ed) begin + if (bytecount == 1) + next_mode = mode_qspi_ddr_rd; + + if (bytecount == 2) + spi_addr[23:16] = buffer; + + if (bytecount == 3) + spi_addr[15:8] = buffer; + + if (bytecount == 4) + spi_addr[7:0] = buffer; + + if (bytecount == 5) begin + xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00; + mode = mode_qspi_ddr_wr; + dummycount = latency; + end + + if (bytecount >= 5) begin + buffer = memory[spi_addr]; + spi_addr = spi_addr + 1; + end + end + + spi_out = buffer; + spi_io_vld = 1; + + if (verbose) begin + if (bytecount == 1) + $write("<SPI-START>"); + $write("<SPI:%02x:%02x>", spi_in, spi_out); + end + + end + endtask + + task ddr_rd_edge; + begin + buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed}; + bitcount = bitcount + 4; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + endtask + + task ddr_wr_edge; + begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 1; + io3_oe = 1; + + io0_dout = buffer[4]; + io1_dout = buffer[5]; + io2_dout = buffer[6]; + io3_dout = buffer[7]; + + buffer = {buffer, 4'h 0}; + bitcount = bitcount + 4; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + endtask + + always @(csb) begin + if (csb) begin + if (verbose) begin + $display(""); + $fflush; + end + buffer = 0; + bitcount = 0; + bytecount = 0; + mode = mode_spi; + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + + // Handle MBR. If in XIP continuous mode, the following + // 8 clock cycles are normally not expected to be a command. + // If followed by CSB high, however, if the address bits + // are consistent with io0 == 1 for 8 clk cycles, then an + // MBR has been issued and the system must exit XIP + // continuous mode. + if (xip_cmd == 8'hbb || xip_cmd == 8'heb + || xip_cmd == 8'hed) begin + if (reset_count == 4'h8 && reset_monitor == 4'h8) begin + xip_cmd = 8'h00; + spi_cmd = 8'h03; + end + end + end else + if (xip_cmd) begin + buffer = xip_cmd; + bitcount = 0; + bytecount = 1; + spi_action; + end + end + + always @(posedge clk or posedge csb) begin + if (csb == 1'b1) begin + reset_count = 0; + reset_monitor = 0; + end else begin + if (reset_count < 4'h9) begin + reset_count = reset_count + 1; + if (io0_delayed == 1'b1) begin + reset_monitor = reset_monitor + 1; + end + end + end + end + + always @(csb, clk) begin + spi_io_vld = 0; + if (!csb && !clk) begin + if (dummycount > 0) begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end else + case (mode) + mode_spi: begin + io0_oe = 0; + io1_oe = 1; + io2_oe = 0; + io3_oe = 0; + io1_dout = buffer[7]; + end + mode_dspi_rd: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_dspi_wr: begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 0; + io3_oe = 0; + io0_dout = buffer[6]; + io1_dout = buffer[7]; + end + mode_qspi_rd: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_qspi_wr: begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 1; + io3_oe = 1; + io0_dout = buffer[4]; + io1_dout = buffer[5]; + io2_dout = buffer[6]; + io3_dout = buffer[7]; + end + mode_qspi_ddr_rd: begin + ddr_rd_edge; + end + mode_qspi_ddr_wr: begin + ddr_wr_edge; + end + endcase + if (next_mode) begin + case (next_mode) + mode_qspi_ddr_rd: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_qspi_ddr_wr: begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 1; + io3_oe = 1; + io0_dout = buffer[4]; + io1_dout = buffer[5]; + io2_dout = buffer[6]; + io3_dout = buffer[7]; + end + endcase + mode = next_mode; + next_mode = 0; + end + end + end + + always @(posedge clk) begin + if (!csb) begin + if (dummycount > 0) begin + dummycount = dummycount - 1; + end else + case (mode) + mode_spi: begin + buffer = {buffer, io0}; + bitcount = bitcount + 1; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + mode_dspi_rd, mode_dspi_wr: begin + buffer = {buffer, io1, io0}; + bitcount = bitcount + 2; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + mode_qspi_rd, mode_qspi_wr: begin + buffer = {buffer, io3, io2, io1, io0}; + bitcount = bitcount + 4; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + mode_qspi_ddr_rd: begin + ddr_rd_edge; + end + mode_qspi_ddr_wr: begin + ddr_wr_edge; + end + endcase + end + end +endmodule
diff --git a/verilog/dv/microwatt/memory_test/tbuart_modified.v b/verilog/dv/vip/tbuart_microwatt.v similarity index 97% rename from verilog/dv/microwatt/memory_test/tbuart_modified.v rename to verilog/dv/vip/tbuart_microwatt.v index ad9b8f9..ef9bb85 100644 --- a/verilog/dv/microwatt/memory_test/tbuart_modified.v +++ b/verilog/dv/vip/tbuart_microwatt.v
@@ -27,7 +27,7 @@ /* should be possible on a testing system to interface to the UART */ /* pins on a Raspberry Pi, also running at 3.3V. */ -module tbuart_modified # ( +module tbuart_microwatt # ( parameter baud_rate = 115200 ) ( input ser_rx
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index f5047d5..0ce90cc 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -1,3 +1,10 @@ # Caravel user project includes --v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v --v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v + +-v $(USER_PROJECT_VERILOG)/dv/vip/spiflash_microwatt.v +-v $(USER_PROJECT_VERILOG)/dv/vip/tbuart_microwatt.v + +-v $(USER_PROJECT_VERILOG)/gl/Microwatt_FP_DFFRFile.v +-v $(USER_PROJECT_VERILOG)/gl/multiply_add_64x64.v +-v $(USER_PROJECT_VERILOG)/gl/RAM32_1RW1R.v +-v $(USER_PROJECT_VERILOG)/gl/RAM512.v +-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index 31ab09b..5b6b7ae 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,30 @@ # Caravel user project includes --v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v --v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v - \ No newline at end of file +-v $(USER_PROJECT_VERILOG)/dv/vip/spiflash_microwatt.v +-v $(USER_PROJECT_VERILOG)/dv/vip/tbuart_microwatt.v +-v $(USER_PROJECT_VERILOG)/dv/vip/Microwatt_FP_DFFRFile.v +-v $(USER_PROJECT_VERILOG)/dv/vip/multiply_add_64x64.v +-v $(USER_PROJECT_VERILOG)/dv/vip/RAM32_1RW1R.v +-v $(USER_PROJECT_VERILOG)/dv/vip/RAM512.v + +# JTAG +-v $(USER_PROJECT_VERILOG)/rtl/tap_top.v + +# UART +-v $(USER_PROJECT_VERILOG)/rtl/raminfr.v +-v $(USER_PROJECT_VERILOG)/rtl/uart_defines.v +-v $(USER_PROJECT_VERILOG)/rtl/uart_receiver.v +-v $(USER_PROJECT_VERILOG)/rtl/uart_regs.v +-v $(USER_PROJECT_VERILOG)/rtl/uart_rfifo.v +-v $(USER_PROJECT_VERILOG)/rtl/uart_sync_flops.v +-v $(USER_PROJECT_VERILOG)/rtl/uart_tfifo.v +-v $(USER_PROJECT_VERILOG)/rtl/uart_top.v +-v $(USER_PROJECT_VERILOG)/rtl/uart_transmitter.v +-v $(USER_PROJECT_VERILOG)/rtl/uart_wb.v + +# Simplebus +-v $(USER_PROJECT_VERILOG)/rtl/simplebus_host.v + +# Microwatt +-v $(USER_PROJECT_VERILOG)/rtl/microwatt.v +-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
diff --git a/verilog/rtl/microwatt.v b/verilog/rtl/microwatt.v index eab3507..5e6352f 100644 --- a/verilog/rtl/microwatt.v +++ b/verilog/rtl/microwatt.v
@@ -1,19 +1,3 @@ - -/* JTAG */ -`include "tap_top.v" - -/* UART */ -`include "raminfr.v" -`include "uart_receiver.v" -`include "uart_rfifo.v" -`include "uart_tfifo.v" -`include "uart_transmitter.v" -`include "uart_defines.v" -`include "uart_regs.v" -`include "uart_sync_flops.v" -`include "uart_wb.v" -`include "uart_top.v" -`include "simplebus_host.v" module plru_1 (input clk, input rst,
diff --git a/verilog/rtl/uart_receiver.v b/verilog/rtl/uart_receiver.v index 44c2936..8c6f128 100644 --- a/verilog/rtl/uart_receiver.v +++ b/verilog/rtl/uart_receiver.v
@@ -189,8 +189,6 @@ // // -`include "uart_defines.v" - module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
diff --git a/verilog/rtl/uart_regs.v b/verilog/rtl/uart_regs.v index 931632c..b0773a5 100644 --- a/verilog/rtl/uart_regs.v +++ b/verilog/rtl/uart_regs.v
@@ -219,8 +219,6 @@ // // -`include "uart_defines.v" - `define UART_DL1 7:0 `define UART_DL2 15:8
diff --git a/verilog/rtl/uart_rfifo.v b/verilog/rtl/uart_rfifo.v index 59a29b9..213f99d 100644 --- a/verilog/rtl/uart_rfifo.v +++ b/verilog/rtl/uart_rfifo.v
@@ -141,8 +141,6 @@ // // -`include "uart_defines.v" - module uart_rfifo (clk, wb_rst_i, data_in, data_out, // Control signals
diff --git a/verilog/rtl/uart_tfifo.v b/verilog/rtl/uart_tfifo.v index 5b254cb..33d3ea0 100644 --- a/verilog/rtl/uart_tfifo.v +++ b/verilog/rtl/uart_tfifo.v
@@ -135,8 +135,6 @@ // // -`include "uart_defines.v" - module uart_tfifo (clk, wb_rst_i, data_in, data_out, // Control signals
diff --git a/verilog/rtl/uart_top.v b/verilog/rtl/uart_top.v index 528f2f7..45d1b8a 100644 --- a/verilog/rtl/uart_top.v +++ b/verilog/rtl/uart_top.v
@@ -132,8 +132,6 @@ // // -`include "uart_defines.v" - module uart_top ( wb_clk_i,
diff --git a/verilog/rtl/uart_transmitter.v b/verilog/rtl/uart_transmitter.v index e2e8cf3..0ccddae 100644 --- a/verilog/rtl/uart_transmitter.v +++ b/verilog/rtl/uart_transmitter.v
@@ -145,8 +145,6 @@ // // -`include "uart_defines.v" - module uart_transmitter #(parameter SIM = 0) (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
diff --git a/verilog/rtl/uart_wb.v b/verilog/rtl/uart_wb.v index d537b70..719f360 100644 --- a/verilog/rtl/uart_wb.v +++ b/verilog/rtl/uart_wb.v
@@ -134,8 +134,6 @@ // Company: Flextronics Semiconductor // -`include "uart_defines.v" - module uart_wb (clk, wb_rst_i, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i, wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v deleted file mode 100644 index 821e748..0000000 --- a/verilog/rtl/uprj_netlists.v +++ /dev/null
@@ -1,35 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -// Include caravel global defines for the number of the user project IO pads -`include "defines.v" -`define USE_POWER_PINS - -`ifdef GL - // Assume default net type to be wire because GL netlists don't have the wire definitions - `default_nettype wire - `include "gl/user_project_wrapper.v" - `include "gl/Microwatt_FP_DFFRFile.v" - `include "gl/multiply_add_64x64.v" - `include "gl/RAM32_1RW1R.v" - `include "gl/RAM512.v" -`else - `include "user_project_wrapper.v" - `include "Microwatt_FP_DFFRFile.v" - `include "multiply_add_64x64.v" - `include "RAM32_1RW1R.v" - `include "RAM512.v" - `include "microwatt.v" -`endif
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v deleted file mode 100644 index 26081e9..0000000 --- a/verilog/rtl/user_proj_example.v +++ /dev/null
@@ -1,165 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none -/* - *------------------------------------------------------------- - * - * user_proj_example - * - * This is an example of a (trivially simple) user project, - * showing how the user project can connect to the logic - * analyzer, the wishbone bus, and the I/O pads. - * - * This project generates an integer count, which is output - * on the user area GPIO pads (digital output only). The - * wishbone connection allows the project to be controlled - * (start and stop) from the management SoC program. - * - * See the testbenches in directory "mprj_counter" for the - * example programs that drive this user project. The three - * testbenches are "io_ports", "la_test1", and "la_test2". - * - *------------------------------------------------------------- - */ - -module user_proj_example #( - parameter BITS = 32 -)( -`ifdef USE_POWER_PINS - inout vccd1, // User area 1 1.8V supply - inout vssd1, // User area 1 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oenb, - - // IOs - input [`MPRJ_IO_PADS-1:0] io_in, - output [`MPRJ_IO_PADS-1:0] io_out, - output [`MPRJ_IO_PADS-1:0] io_oeb, - - // IRQ - output [2:0] irq -); - wire clk; - wire rst; - - wire [`MPRJ_IO_PADS-1:0] io_in; - wire [`MPRJ_IO_PADS-1:0] io_out; - wire [`MPRJ_IO_PADS-1:0] io_oeb; - - wire [31:0] rdata; - wire [31:0] wdata; - wire [BITS-1:0] count; - - wire valid; - wire [3:0] wstrb; - wire [31:0] la_write; - - // WB MI A - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & {4{wbs_we_i}}; - assign wbs_dat_o = rdata; - assign wdata = wbs_dat_i; - - // IO - assign io_out = count; - assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; - - // IRQ - assign irq = 3'b000; // Unused - - // LA - assign la_data_out = {{(127-BITS){1'b0}}, count}; - // Assuming LA probes [63:32] are for controlling the count register - assign la_write = ~la_oenb[63:32] & ~{BITS{valid}}; - // Assuming LA probes [65:64] are for controlling the count clk & reset - assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i; - assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i; - - counter #( - .BITS(BITS) - ) counter( - .clk(clk), - .reset(rst), - .ready(wbs_ack_o), - .valid(valid), - .rdata(rdata), - .wdata(wbs_dat_i), - .wstrb(wstrb), - .la_write(la_write), - .la_input(la_data_in[63:32]), - .count(count) - ); - -endmodule - -module counter #( - parameter BITS = 32 -)( - input clk, - input reset, - input valid, - input [3:0] wstrb, - input [BITS-1:0] wdata, - input [BITS-1:0] la_write, - input [BITS-1:0] la_input, - output ready, - output [BITS-1:0] rdata, - output [BITS-1:0] count -); - reg ready; - reg [BITS-1:0] count; - reg [BITS-1:0] rdata; - - always @(posedge clk) begin - if (reset) begin - count <= 0; - ready <= 0; - end else begin - ready <= 1'b0; - if (~|la_write) begin - count <= count + 1; - end - if (valid && !ready) begin - ready <= 1'b1; - rdata <= count; - if (wstrb[0]) count[7:0] <= wdata[7:0]; - if (wstrb[1]) count[15:8] <= wdata[15:8]; - if (wstrb[2]) count[23:16] <= wdata[23:16]; - if (wstrb[3]) count[31:24] <= wdata[31:24]; - end else if (|la_write) begin - count <= la_write & la_input; - end - end - end - -endmodule -`default_nettype wire