removed config.json files
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json deleted file mode 100644 index c3de8af..0000000 --- a/openlane/user_proj_example/config.json +++ /dev/null
@@ -1,21 +0,0 @@ -{ - "PDK" : "sky130A", - "STD_CELL_LIBRARY" : "sky130_fd_sc_hd", - "CARAVEL_ROOT" : "../../caravel", - "CLOCK_NET" : "counter.clk", - "CLOCK_PERIOD" : "10", - "CLOCK_PORT" : "wb_clk_i", - "DESIGN_IS_CORE" : "0", - "DESIGN_NAME" : "user_proj_example", - "DIE_AREA" : "0 0 900 600", - "DIODE_INSERTION_STRATEGY" : "4", - "FP_PIN_ORDER_CFG" : "pin_order.cfg", - "FP_SIZING" : "absolute", - "GLB_RT_MAXLAYER" : "5", - "GND_NETS" : "vssd1", - "PL_BASIC_PLACEMENT" : "1", - "PL_TARGET_DENSITY" : "0.05", - "RUN_CVC" : "1", - "VDD_NETS" : "vccd1", - "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v"] -}
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json deleted file mode 100644 index d83d5bb..0000000 --- a/openlane/user_project_wrapper/config.json +++ /dev/null
@@ -1,58 +0,0 @@ -{ - "PDK" : "sky130A", - "STD_CELL_LIBRARY" : "sky130_fd_sc_hd", - "CARAVEL_ROOT" : "../../caravel", - "CLOCK_NET" : "mprj.clk", - "CLOCK_PERIOD" : "10", - "CLOCK_PORT" : "user_clock2", - "CLOCK_TREE_SYNTH" : "0", - "DESIGN_NAME" : "user_project_wrapper", - "DIE_AREA" : "0 0 2920 3520", - "DIODE_INSERTION_STRATEGY" : "0", - "EXTRA_GDS_FILES" : "../../gds/user_proj_example.gds", - "EXTRA_LEFS" : "../../lef/user_proj_example.lef", - "FILL_INSERTION" : "0", - "FP_IO_HEXTEND" : "4.8", - "FP_IO_HLENGTH" : "2.4", - "FP_IO_HTHICKNESS_MULT" : "4", - "FP_IO_VEXTEND" : "4.8", - "FP_IO_VLENGTH" : "2.4", - "FP_IO_VTHICKNESS_MULT" : "4", - "FP_PDN_CHECK_NODES" : "0", - "FP_PDN_CORE_RING" : "1", - "FP_PDN_CORE_RING_HOFFSET" : "14", - "FP_PDN_CORE_RING_HSPACING" : "1.7", - "FP_PDN_CORE_RING_HWIDTH" : "3.1", - "FP_PDN_CORE_RING_VOFFSET" : "14", - "FP_PDN_CORE_RING_VSPACING" : "1.7", - "FP_PDN_CORE_RING_VWIDTH" : "3.1", - "FP_PDN_ENABLE_RAILS" : "0", - "FP_PDN_HOFFSET" : "5", - "FP_PDN_HPITCH" : "180", - "FP_PDN_HSPACING" : "15.5", - "FP_PDN_HWIDTH" : "3.1", - "FP_PDN_MACRO_HOOKS" : "mprj vccd1 vssd1", - "FP_PDN_VOFFSET" : "5", - "FP_PDN_VPITCH" : "180", - "FP_PDN_VSPACING" : "15.5", - "FP_PDN_VWIDTH" : "3.1", - "FP_PIN_ORDER_CFG" : "../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg", - "FP_SIZING" : "absolute", - "GLB_RT_MAXLAYER" : "5", - "GND_NETS" : "vssd1 vssd2 vssa1 vssa2", - "MACRO_PLACEMENT_CFG" : "macro.cfg", - "MAGIC_ZEROIZE_ORIGIN" : "0", - "PL_RANDOM_GLB_PLACEMENT" : "1", - "PL_RESIZER_BUFFER_INPUT_PORTS" : "0", - "PL_RESIZER_BUFFER_OUTPUT_PORTS" : "0", - "PL_RESIZER_DESIGN_OPTIMIZATIONS" : "0", - "PL_RESIZER_TIMING_OPTIMIZATIONS" : "0", - "RUN_CVC" : "0", - "SYNTH_TOP_LEVEL" : "1", - "SYNTH_USE_PG_PINS_DEFINES" : "USE_POWER_PINS", - "TAP_DECAP_INSERTION" : "0", - "VDD_NETS" : "vccd1 vccd2 vdda1 vdda2", - "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"], - "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_proj_example.v"] -} -