Matt Venn | 53f4216 | 2022-08-31 17:49:41 +0200 | [diff] [blame] | 1 | `default_nettype none |
| 2 | /* |
| 3 | `ifdef COCOTB |
| 4 | `define UNIT_DELAY #1 |
| 5 | `define FUNCTIONAL |
| 6 | `define USE_POWER_PINS |
| 7 | `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v" |
| 8 | `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" |
| 9 | `endif |
| 10 | */ |
| 11 | |
| 12 | module scan_wrapper_341432030163108435 ( |
| 13 | input wire clk_in, |
| 14 | input wire data_in, |
| 15 | input wire scan_select_in, |
| 16 | input wire latch_enable_in, |
| 17 | output wire clk_out, |
| 18 | output wire data_out, |
| 19 | output wire scan_select_out, |
| 20 | output wire latch_enable_out |
| 21 | ); |
Matt Venn | 1f81eb4 | 2022-09-03 20:16:04 +0200 | [diff] [blame] | 22 | |
| 23 | // input buffers |
| 24 | // Looking at results from multiple projects the bufferring is a bit |
| 25 | // inconsistent. So instead, we ensure at least clk buf |
| 26 | wire clk; |
| 27 | |
| 28 | sky130_fd_sc_hd__clkbuf_2 input_buf_clk ( |
| 29 | .A (clk_in), |
| 30 | .X (clk), |
| 31 | .VPWR (1'b1), |
| 32 | .VGND (1'b0) |
| 33 | ); |
| 34 | |
| 35 | // output buffers |
| 36 | // Same as for input, to try and be more consistent, we make our own |
| 37 | wire data_out_i; |
| 38 | |
| 39 | sky130_fd_sc_hd__buf_4 output_buffers[3:0] ( |
| 40 | .A ({clk, data_out_i, scan_select_in, latch_enable_in }), |
| 41 | .X ({clk_out, data_out, scan_select_out, latch_enable_out }), |
| 42 | .VPWR (1'b1), |
| 43 | .VGND (1'b0) |
| 44 | ); |
Matt Venn | 53f4216 | 2022-08-31 17:49:41 +0200 | [diff] [blame] | 45 | |
| 46 | /* |
| 47 | `ifdef COCOTB |
| 48 | initial begin |
| 49 | $dumpfile ("scan_wrapper.vcd"); |
| 50 | $dumpvars (0, scan_wrapper_lesson_1); |
| 51 | #1; |
| 52 | end |
| 53 | `endif |
| 54 | */ |
| 55 | |
| 56 | parameter NUM_IOS = 8; |
| 57 | |
| 58 | // wires needed |
| 59 | wire [NUM_IOS-1:0] scan_data_out; // output of the each scan chain flop |
| 60 | wire [NUM_IOS-1:0] scan_data_in; // input of each scan chain flop |
| 61 | wire [NUM_IOS-1:0] module_data_in; // the data that enters the user module |
| 62 | wire [NUM_IOS-1:0] module_data_out; // the data from the user module |
| 63 | |
| 64 | // scan chain - link all the flops, with data coming from data_in |
| 65 | assign scan_data_in = {scan_data_out[NUM_IOS-2:0], data_in}; |
Matt Venn | 1f81eb4 | 2022-09-03 20:16:04 +0200 | [diff] [blame] | 66 | |
| 67 | // end of the chain is a negedge FF to increase hold margin between blocks |
| 68 | sky130_fd_sc_hd__dfrtn_1 out_flop ( |
| 69 | .RESET_B (1'b1), |
| 70 | .CLK_N (clk), |
| 71 | .D (scan_data_out[NUM_IOS-1]), |
| 72 | .Q (data_out_i), |
| 73 | .VPWR (1'b1), |
| 74 | .VGND (1'b0) |
| 75 | ); |
Matt Venn | 53f4216 | 2022-08-31 17:49:41 +0200 | [diff] [blame] | 76 | |
| 77 | // scan flops have a mux on their inputs to choose either data from the user module or the previous flop's output |
| 78 | // https://antmicro-skywater-pdk-docs.readthedocs.io/en/test-submodules-in-rtd/contents/libraries/sky130_fd_sc_ls/cells/sdfxtp/README.html |
| 79 | `ifndef FORMAL |
| 80 | `ifndef FORMAL_COMPAT |
| 81 | sky130_fd_sc_hd__sdfxtp_1 scan_flop [NUM_IOS-1:0] ( |
| 82 | .CLK (clk), |
| 83 | .D (scan_data_in), |
| 84 | .SCD (module_data_out), |
| 85 | .SCE (scan_select_in), |
| 86 | .Q (scan_data_out), |
| 87 | .VPWR (1'b1), |
| 88 | .VGND (1'b0) |
| 89 | ); |
| 90 | |
| 91 | // latch is used to latch the input data of the user module while the scan chain is used to capture the user module's outputs |
| 92 | // https://antmicro-skywater-pdk-docs.readthedocs.io/en/test-submodules-in-rtd/contents/libraries/sky130_fd_sc_hd/cells/dlxtp/README.html |
| 93 | sky130_fd_sc_hd__dlxtp_1 latch [NUM_IOS-1:0] ( |
| 94 | .D (scan_data_out), |
| 95 | .GATE (latch_enable_in), |
| 96 | .Q (module_data_in), |
| 97 | .VPWR (1'b1), |
| 98 | .VGND (1'b0) |
| 99 | ); |
| 100 | `endif |
| 101 | `endif |
| 102 | |
| 103 | // instantiate the wokwi module |
| 104 | user_module_341432030163108435 user_module( |
| 105 | .io_in (module_data_in), |
| 106 | .io_out (module_data_out) |
| 107 | ); |
| 108 | |
| 109 | endmodule |