hardened all submissions
diff --git a/verilog/rtl/scan_wrapper_341432030163108435.v b/verilog/rtl/scan_wrapper_341432030163108435.v
index 7eda6ce..ed6468d 100644
--- a/verilog/rtl/scan_wrapper_341432030163108435.v
+++ b/verilog/rtl/scan_wrapper_341432030163108435.v
@@ -19,11 +19,29 @@
output wire scan_select_out,
output wire latch_enable_out
);
-
- assign scan_select_out = scan_select_in;
- assign latch_enable_out = latch_enable_in;
- assign clk_out = clk_in;
- wire clk = clk_in;
+
+ // input buffers
+ // Looking at results from multiple projects the bufferring is a bit
+ // inconsistent. So instead, we ensure at least clk buf
+ wire clk;
+
+ sky130_fd_sc_hd__clkbuf_2 input_buf_clk (
+ .A (clk_in),
+ .X (clk),
+ .VPWR (1'b1),
+ .VGND (1'b0)
+ );
+
+ // output buffers
+ // Same as for input, to try and be more consistent, we make our own
+ wire data_out_i;
+
+ sky130_fd_sc_hd__buf_4 output_buffers[3:0] (
+ .A ({clk, data_out_i, scan_select_in, latch_enable_in }),
+ .X ({clk_out, data_out, scan_select_out, latch_enable_out }),
+ .VPWR (1'b1),
+ .VGND (1'b0)
+ );
/*
`ifdef COCOTB
@@ -45,9 +63,16 @@
// scan chain - link all the flops, with data coming from data_in
assign scan_data_in = {scan_data_out[NUM_IOS-2:0], data_in};
-
- // end of the chain is the last scan flop's out
- assign data_out = scan_data_out[NUM_IOS-1];
+
+ // end of the chain is a negedge FF to increase hold margin between blocks
+ sky130_fd_sc_hd__dfrtn_1 out_flop (
+ .RESET_B (1'b1),
+ .CLK_N (clk),
+ .D (scan_data_out[NUM_IOS-1]),
+ .Q (data_out_i),
+ .VPWR (1'b1),
+ .VGND (1'b0)
+ );
// scan flops have a mux on their inputs to choose either data from the user module or the previous flop's output
// https://antmicro-skywater-pdk-docs.readthedocs.io/en/test-submodules-in-rtd/contents/libraries/sky130_fd_sc_ls/cells/sdfxtp/README.html
