blob: dad8fc6b68c0e1a999486c8ddb6c97d0d9635524 [file] [log] [blame]
dineshannayya52e8a342022-02-15 14:19:56 +05301//////////////////////////////////////////////////////////////////////////////
2// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
3//
4// Licensed under the Apache License, Version 2.0 (the "License");
5// you may not use this file except in compliance with the License.
6// You may obtain a copy of the License at
7//
8// http://www.apache.org/licenses/LICENSE-2.0
9//
10// Unless required by applicable law or agreed to in writing, software
11// distributed under the License is distributed on an "AS IS" BASIS,
12// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13// See the License for the specific language governing permissions and
14// limitations under the License.
15// SPDX-License-Identifier: Apache-2.0
16// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
17//
18//////////////////////////////////////////////////////////////////////
19//// ////
20//// Clk Buf ////
21//// ////
22//// This file is part of the YIFive cores project ////
23//// https://github.com/dineshannayya/yifive_r0.git ////
24//// http://www.opencores.org/cores/yifive/ ////
25//// ////
26//// Description ////
27//// Adding clock buf for manual clock tree at SOC level ////
28//// To Do: ////
29//// nothing ////
30//// ////
31//// Author(s): ////
32//// - Dinesh Annayya, dinesha@opencores.org ////
33//// ////
34//// Revision : ////
35//////////////////////////////////////////////////////////////////////
36//// ////
37//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
38//// ////
39//// This source file may be used and distributed without ////
40//// restriction provided that this copyright statement is not ////
41//// removed from the file and that any derivative work contains ////
42//// the original copyright notice and the associated disclaimer. ////
43//// ////
44//// This source file is free software; you can redistribute it ////
45//// and/or modify it under the terms of the GNU Lesser General ////
46//// Public License as published by the Free Software Foundation; ////
47//// either version 2.1 of the License, or (at your option) any ////
48//// later version. ////
49//// ////
50//// This source is distributed in the hope that it will be ////
51//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
52//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
53//// PURPOSE. See the GNU Lesser General Public License for more ////
54//// details. ////
55//// ////
56//// You should have received a copy of the GNU Lesser General ////
57//// Public License along with this source; if not, download it ////
58//// from http://www.opencores.org/lgpl.shtml ////
59//// ////
60//////////////////////////////////////////////////////////////////////
61
62
63module clk_buf (
64 // Outputs
65 clk_o,
66 // Inputs
67 clk_i
68 );
69
70//---------------------------------------------
71// All the input to this block are declared here
72// --------------------------------------------
73 input clk_i ;//
74
75//---------------------------------------------
76// All the output to this block are declared here
77// --------------------------------------------
78 output clk_o ; // clock out
79
80
81
82sky130_fd_sc_hd__clkbuf_16 u_buf (.A(clk_i),.X(clk_o));
83
84endmodule
85