.gitmodules

[submodule "verilog/rtl/yifive/ycr4c"]
	path = verilog/rtl/yifive/ycr4c
	url = https://github.com/dineshannayya/ycr4c.git
[submodule "verilog/rtl/qspim1"]
	path = verilog/rtl/qspim
	url = https://github.com/dineshannayya/qspim.git