commit: 93970d2c6e32900623fd95864eaf26f1025ed11a
[log]
author: getziadz <getziadz@pm.me>
Wed May 11 11:41:41 2022 -0400
committer: getziadz <getziadz@pm.me>
Wed May 11 11:41:41 2022 -0400
tree: 2c7c25805b2bc702b34cb5d85bb784e6bb4893e9
parent: a11292b5ad1ffdb085a7884807f9d9569dce13f5 [diff]

Add PRGA top and tile_clb Verilog and configuration files

openlane/prga/config.tcl[Added - diff]
openlane/prga/constraint.sdc[Added - diff]
openlane/prga/gen_placement.py[Added - diff]
openlane/prga/macro_placement.cfg[Added - diff]
openlane/prga/pdn_cfg.tcl[Added - diff]
openlane/prga/pin_order.cfg[Added - diff]
openlane/tile_clb/config.tcl[Added - diff]
openlane/tile_clb/constraint.sdc[Added - diff]
openlane/tile_clb/pdn_cfg.tcl[Added - diff]
openlane/tile_clb/pin_order.cfg[Added - diff]
verilog/rtl/tile_clb.bb.v[Added - diff]
verilog/rtl/tile_clb.pickled.v[Added - diff]
verilog/rtl/top.bb.v[Added - diff]
verilog/rtl/top.pickled.v[Added - diff]

14 files changed

tree: 2c7c25805b2bc702b34cb5d85bb784e6bb4893e9

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.