Added the 3 user IRQ lines to the project wrapper and zeroed them
in the project example RTL.
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 7741210..177a733 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -69,7 +69,10 @@
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // IRQ
+ output [2:0] irq
);
wire clk;
wire rst;
@@ -96,6 +99,9 @@
assign io_out = count;
assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+ // IRQ
+ assigin irq = 3'b000; // Unused
+
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
// Assuming LA probes [63:32] are for controlling the count register
