added missing rtl
1 file changed
tree: fb187f35d2fe67f98f7ad6f0bf4ba8bb7e15ac53
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. LICENSE
  14. Makefile
  15. README.md
README.md

Soc Now

License UPRJ_CI Caravel Build

Soc NOW is a chisel based core. It has RV32I ISA support, 32 GPIO pins and UART to program the SoC.