)]}'
{
  "commit": "322e6f543677d946dcf1108e4015b4eea462979a",
  "tree": "fb187f35d2fe67f98f7ad6f0bf4ba8bb7e15ac53",
  "parents": [
    "9f883650b6c395b8e60404a940fd761951801a00"
  ],
  "author": {
    "name": "Usman",
    "email": "usmanzain95@gmail.com",
    "time": "Wed Jun 08 13:23:47 2022 +0500"
  },
  "committer": {
    "name": "Usman",
    "email": "usmanzain95@gmail.com",
    "time": "Wed Jun 08 13:23:47 2022 +0500"
  },
  "message": "added missing rtl\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "23016daa7212103d276fc56994ad1293865eba1b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/uart_rx_prog.v"
    }
  ]
}