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foss-eda-tools
/
third_party
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shuttle
/
sky130
/
mpw-006
/
slot-035
/
refs/heads/main
/
.
/
verilog
/
rtl
/
clock_divider.v
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module
ClockDividerPow
(
input clk
,
output clk_out
);
parameter POW2DIV
=
2
;
reg
[
POW2DIV
:
0
]
counter
=
0
;
always
@
(
posedge clk
)
begin
counter
<=
counter
+
1
;
end
assign clk_out
=
counter
[
POW2DIV
];
endmodule