mpw_precheck/logs/spdx_compliance_report.log

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/root/efabless_mpw6_riscduino/verilog/rtl/mbist/run_verilator
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/include/mbist_def.svh
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/core/mbist_addr_gen.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/core/mbist_data_cmp.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/core/mbist_fsm.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/core/mbist_mux.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/core/mbist_op_sel.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/core/mbist_pat_sel.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/core/mbist_sti_sel.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/top/mbist_top.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/top/mbist_top1.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist/src/top/mbist_top2.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist_wrapper/src/mbist_wb.sv
/root/efabless_mpw6_riscduino/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
/root/efabless_mpw6_riscduino/verilog/rtl/pinmux/src/gpio_control.sv
/root/efabless_mpw6_riscduino/verilog/rtl/pinmux/src/gpio_intr.sv
/root/efabless_mpw6_riscduino/verilog/rtl/pinmux/src/pinmux.sv
/root/efabless_mpw6_riscduino/verilog/rtl/pinmux/src/pinmux_reg.sv
/root/efabless_mpw6_riscduino/verilog/rtl/pinmux/src/pwm.sv
/root/efabless_mpw6_riscduino/verilog/rtl/pinmux/src/timer.sv
/root/efabless_mpw6_riscduino/verilog/rtl/sar_adc/ACMP.sv
/root/efabless_mpw6_riscduino/verilog/rtl/sar_adc/ACMP_HVL.v
/root/efabless_mpw6_riscduino/verilog/rtl/sar_adc/DAC_8BIT.v
/root/efabless_mpw6_riscduino/verilog/rtl/sar_adc/SAR.sv
/root/efabless_mpw6_riscduino/verilog/rtl/sar_adc/adc_reg.sv
/root/efabless_mpw6_riscduino/verilog/rtl/sar_adc/sar_adc.sv
/root/efabless_mpw6_riscduino/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
/root/efabless_mpw6_riscduino/verilog/rtl/sspim/src/filelist_spi.f
/root/efabless_mpw6_riscduino/verilog/rtl/sspim/src/sspim_cfg.sv
/root/efabless_mpw6_riscduino/verilog/rtl/sspim/src/sspim_ctl.sv
/root/efabless_mpw6_riscduino/verilog/rtl/sspim/src/sspim_if.sv
/root/efabless_mpw6_riscduino/verilog/rtl/sspim/src/sspim_top.sv
/root/efabless_mpw6_riscduino/verilog/rtl/uart/src/uart_cfg.sv
/root/efabless_mpw6_riscduino/verilog/rtl/uart/src/uart_core.sv
/root/efabless_mpw6_riscduino/verilog/rtl/uart/src/uart_rxfsm.sv
/root/efabless_mpw6_riscduino/verilog/rtl/uart/src/uart_txfsm.sv
/root/efabless_mpw6_riscduino/verilog/rtl/uart2wb/src/run_verilog
/root/efabless_mpw6_riscduino/verilog/rtl/uart2wb/src/uart2_core.sv
/root/efabless_mpw6_riscduino/verilog/rtl/uart2wb/src/uart2wb.sv
/root/efabless_mpw6_riscduino/verilog/rtl/uart2wb/src/uart_msg_handler.v
/root/efabless_mpw6_riscduino/verilog/rtl/uart_i2c/src/uart_i2c_top.sv
/root/efabless_mpw6_riscduino/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv
/root/efabless_mpw6_riscduino/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/filelist.f
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/core/usbh_core.sv
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/core/usbh_crc16.sv
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/core/usbh_crc5.sv
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/core/usbh_fifo.sv
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/core/usbh_sie.sv
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/includes/usbh_host_defs.v
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/phy/usb_transceiver.v
/root/efabless_mpw6_riscduino/verilog/rtl/usb1_host/src/top/usb1_host.sv
/root/efabless_mpw6_riscduino/verilog/rtl/wb_host/src/wb_host.sv
/root/efabless_mpw6_riscduino/verilog/rtl/wb_interconnect/src/wb_arb.sv
/root/efabless_mpw6_riscduino/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
/root/efabless_mpw6_riscduino/verilog/rtl/wb_interconnect/src/wb_slave_port.sv