commit	78fa95c940c3cee407228efc6232177b99a4bf85	[log] [tgz]
author	ranan-usp <oe23ranan@ec.usp.ac.jp>	Mon May 16 06:53:57 2022 +0900
committer	ranan-usp <oe23ranan@ec.usp.ac.jp>	Mon May 16 06:53:57 2022 +0900
tree	135112eee96cd491f4c7db68ed80f18cf8d39c81
parent	cc08105187ec004beeec23d4cd6965548a9eb16b [diff]

update

Makefile[diff]
caravel[diff]
verilog/dv/mprj_por/Makefile[diff]
verilog/dv/mprj_por/make[Added - diff]
verilog/dv/mprj_por/mprj_por.elf[Added - diff]
verilog/dv/mprj_por/mprj_por.hex[Added - diff]
verilog/dv/mprj_por/mprj_por.vvp[Added - diff]
xschem/analog_wrapper_tb.spice[diff]
xschem/bsim4v5.out[Added - diff]
xschem/example_por_tb.spice[diff]
xschem/my_comparator.sch[Added - diff]
xschem/my_comparator.spice[Added - diff]
xschem/my_comparator.sym[Added - diff]
xschem/tb_my_comparator.sch[Added - diff]
xschem/tb_my_comparator.spice[Added - diff]
xschem/untitled.spice[Added - diff]
xschem/user_analog_project_wrapper.spice[diff]
xschem/xschemrc[diff]

18 files changed

tree: 135112eee96cd491f4c7db68ed80f18cf8d39c81

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.