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foss-eda-tools
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third_party
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shuttle
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sky130
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mpw-006
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slot-033
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78fa95c940c3cee407228efc6232177b99a4bf85
commit
78fa95c940c3cee407228efc6232177b99a4bf85
[
log
]
[
tgz
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author
ranan-usp <oe23ranan@ec.usp.ac.jp>
Mon May 16 06:53:57 2022 +0900
committer
ranan-usp <oe23ranan@ec.usp.ac.jp>
Mon May 16 06:53:57 2022 +0900
tree
135112eee96cd491f4c7db68ed80f18cf8d39c81
parent
cc08105187ec004beeec23d4cd6965548a9eb16b
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diff
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update
Makefile
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diff
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caravel
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verilog/dv/mprj_por/Makefile
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verilog/dv/mprj_por/make
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verilog/dv/mprj_por/mprj_por.elf
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verilog/dv/mprj_por/mprj_por.hex
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verilog/dv/mprj_por/mprj_por.vvp
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xschem/analog_wrapper_tb.spice
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xschem/bsim4v5.out
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xschem/example_por_tb.spice
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xschem/my_comparator.sch
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xschem/my_comparator.spice
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xschem/my_comparator.sym
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xschem/tb_my_comparator.sch
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xschem/tb_my_comparator.spice
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xschem/untitled.spice
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xschem/user_analog_project_wrapper.spice
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xschem/xschemrc
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18 files changed
tree: 135112eee96cd491f4c7db68ed80f18cf8d39c81
.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
LICENSE
Makefile
README.md
README.md
Caravel Analog User
:exclamation: Important Note
Please fill in your project documentation in this README.md file
:warning:
Use this sample project for analog user projects.
Refer to
README
for this sample project documentation.
