- bcdb9c9 Updated art macro so that it can pass prechecks. by Charlie · 2 years, 7 months ago
- 9f21750 Updated Art macro to possibly pass prechecks. by Charlie · 2 years, 7 months ago
- bda2da0 Rebuilt with recent fixes. Also re-added GL simulation to GitHub workflow. by Charlie · 2 years, 7 months ago
- 7e13152 Removed art from art module so that it doesn't cause DRC errors (this will be changed back when a fix for this is found). Also added set, clear, and toggle registers to gpio for easier control. This also makes it easier for both cores to write to gpio without clearing what the other core has set. by Charlie · 2 years, 7 months ago
- 9cc2031 Reverted to older OpenLane version, as it seems this is a requirement for MPW submission. by Charlie · 2 years, 7 months ago
- 794a27c Rebuilt with recent changes. by Charlie · 2 years, 7 months ago
- ff79e92 Got user_project_wrapper to build successfully. There are still problems to be resolved, but this is now a by Charlie · 2 years, 7 months ago
- 025b919 Fixed user macros not being connected to PDN. Rotated SRAM macros are still not connected, so the full build still fails. by Charlie · 2 years, 7 months ago
- b8c7bb2 Made some small changes to try to get PDN to connect to macros. Also fixed some missing logic in the core macro. However, most of the macro still does not get built. by Charlie · 2 years, 7 months ago
- c8a9669 Fixed management core not being able to access the wishbone bus in user space. This was caused by a bug in the management core only allowing the use a reduced address. Until that is fixed, a separate write is required to set the upper address bits, before the read/write is performed. Also fixed wishbone slaves not waiting for a clock cycle before allowing another access. Full build still fails due to routing congestion being too high. by Charlie · 2 years, 7 months ago
- bf8e57d Moved macros placement so that PDN can be placed, as move past step 6. Currently routing congestion is too high so user_project_wrapper build fails at step 9. by Charlie · 2 years, 7 months ago
- a41bb8b Updated to having the flash controller on the wishbone bus. Also added more sram to cores and video device. by Charlie · 2 years, 7 months ago
- 5d5650c Major update that should have been split up. Got close to first build of full SoC. Still need flash controller, and to fix a number of issues with the build. by Charlie · 2 years, 7 months ago
- cfad368 Finished initial build of peripheral macro. This has a lot of timing issues, and possibly also some logic issues. by Charlie · 2 years, 8 months ago
- 67633a8 Updated config for project wrapper. by Charlie · 2 years, 8 months ago
- f7da1ed Added SPI peripheral. This builds, but has some timing issues. by Charlie · 2 years, 8 months ago
- f8ca4e7 Added PWM peripheral. This builds, but has timing issues. by Charlie · 2 years, 8 months ago
- 3c43215 Updated IOMultiplexer to take enable inputs rather than have an internal config register. by Charlie · 2 years, 8 months ago
- 8a0b8d0 Removed test Blink macro, as it will be included in the IOMultiplexer. by Charlie · 2 years, 8 months ago
- 04d13eb Added IO multiplexer module to control pin access for peripherals. The project wrapper has skew violations on IO pins when this is included. by Charlie · 2 years, 8 months ago
- 1178880 Hardened blink test module. by Charlie · 2 years, 8 months ago
- de408b7 Tested hardening ExperiarCore module. This has errors and doesn't complete by Charlie · 2 years, 8 months ago
- eb39ce3 Compiled default project examples. by Charlie · 2 years, 8 months ago