blob: 974c18b96674c83872e0c2c92dad7a17b51b7b7f [file] [log] [blame]
Charlieeb39ce32022-04-21 23:50:59 +01001###############################################################################
2# Created by write_sdc
Charlie04d13eb2022-04-24 17:41:32 +01003# Sat Apr 23 15:59:52 2022
Charlieeb39ce32022-04-21 23:50:59 +01004###############################################################################
5current_design user_proj_example
6###############################################################################
7# Timing Constraints
8###############################################################################
9create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
10set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
11set_clock_uncertainty 0.2500 wb_clk_i
12set_propagated_clock [get_clocks {wb_clk_i}]
13set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}]
14set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}]
15set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}]
16set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}]
17set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}]
18set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}]
19set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}]
20set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}]
21set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}]
22set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}]
23set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}]
24set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}]
25set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}]
26set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}]
27set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}]
28set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}]
29set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}]
30set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}]
31set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}]
32set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}]
33set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}]
34set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}]
35set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}]
36set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}]
37set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}]
38set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}]
39set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}]
40set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}]
41set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}]
42set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}]
43set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}]
44set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}]
45set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}]
46set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}]
47set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}]
48set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}]
49set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}]
50set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}]
51set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[0]}]
52set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[100]}]
53set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[101]}]
54set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[102]}]
55set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[103]}]
56set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[104]}]
57set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[105]}]
58set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[106]}]
59set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[107]}]
60set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[108]}]
61set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[109]}]
62set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[10]}]
63set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[110]}]
64set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[111]}]
65set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[112]}]
66set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[113]}]
67set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[114]}]
68set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[115]}]
69set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[116]}]
70set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[117]}]
71set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[118]}]
72set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[119]}]
73set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[11]}]
74set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[120]}]
75set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[121]}]
76set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[122]}]
77set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[123]}]
78set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[124]}]
79set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[125]}]
80set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[126]}]
81set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[127]}]
82set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[12]}]
83set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[13]}]
84set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[14]}]
85set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[15]}]
86set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[16]}]
87set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[17]}]
88set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[18]}]
89set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[19]}]
90set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[1]}]
91set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[20]}]
92set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[21]}]
93set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[22]}]
94set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[23]}]
95set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[24]}]
96set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[25]}]
97set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[26]}]
98set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[27]}]
99set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[28]}]
100set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[29]}]
101set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[2]}]
102set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[30]}]
103set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[31]}]
104set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[32]}]
105set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[33]}]
106set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[34]}]
107set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[35]}]
108set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[36]}]
109set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[37]}]
110set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[38]}]
111set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[39]}]
112set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[3]}]
113set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[40]}]
114set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[41]}]
115set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[42]}]
116set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[43]}]
117set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[44]}]
118set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[45]}]
119set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[46]}]
120set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[47]}]
121set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[48]}]
122set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[49]}]
123set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[4]}]
124set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[50]}]
125set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[51]}]
126set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[52]}]
127set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[53]}]
128set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[54]}]
129set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[55]}]
130set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[56]}]
131set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[57]}]
132set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[58]}]
133set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[59]}]
134set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[5]}]
135set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[60]}]
136set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[61]}]
137set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[62]}]
138set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[63]}]
139set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[64]}]
140set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[65]}]
141set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[66]}]
142set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[67]}]
143set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[68]}]
144set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[69]}]
145set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[6]}]
146set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[70]}]
147set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[71]}]
148set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[72]}]
149set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[73]}]
150set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[74]}]
151set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[75]}]
152set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[76]}]
153set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[77]}]
154set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[78]}]
155set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[79]}]
156set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[7]}]
157set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[80]}]
158set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[81]}]
159set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[82]}]
160set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[83]}]
161set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[84]}]
162set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[85]}]
163set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[86]}]
164set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[87]}]
165set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[88]}]
166set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[89]}]
167set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[8]}]
168set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[90]}]
169set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[91]}]
170set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[92]}]
171set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[93]}]
172set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[94]}]
173set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[95]}]
174set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[96]}]
175set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[97]}]
176set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[98]}]
177set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[99]}]
178set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[9]}]
179set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[0]}]
180set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[100]}]
181set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[101]}]
182set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[102]}]
183set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[103]}]
184set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[104]}]
185set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[105]}]
186set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[106]}]
187set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[107]}]
188set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[108]}]
189set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[109]}]
190set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[10]}]
191set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[110]}]
192set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[111]}]
193set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[112]}]
194set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[113]}]
195set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[114]}]
196set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[115]}]
197set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[116]}]
198set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[117]}]
199set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[118]}]
200set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[119]}]
201set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[11]}]
202set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[120]}]
203set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[121]}]
204set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[122]}]
205set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[123]}]
206set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[124]}]
207set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[125]}]
208set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[126]}]
209set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[127]}]
210set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[12]}]
211set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[13]}]
212set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[14]}]
213set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[15]}]
214set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[16]}]
215set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[17]}]
216set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[18]}]
217set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[19]}]
218set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[1]}]
219set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[20]}]
220set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[21]}]
221set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[22]}]
222set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[23]}]
223set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[24]}]
224set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[25]}]
225set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[26]}]
226set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[27]}]
227set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[28]}]
228set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[29]}]
229set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[2]}]
230set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[30]}]
231set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[31]}]
232set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[32]}]
233set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[33]}]
234set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[34]}]
235set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[35]}]
236set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[36]}]
237set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[37]}]
238set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[38]}]
239set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[39]}]
240set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[3]}]
241set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[40]}]
242set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[41]}]
243set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[42]}]
244set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[43]}]
245set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[44]}]
246set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[45]}]
247set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[46]}]
248set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[47]}]
249set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[48]}]
250set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[49]}]
251set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[4]}]
252set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[50]}]
253set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[51]}]
254set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[52]}]
255set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[53]}]
256set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[54]}]
257set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[55]}]
258set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[56]}]
259set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[57]}]
260set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[58]}]
261set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[59]}]
262set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[5]}]
263set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[60]}]
264set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[61]}]
265set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[62]}]
266set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[63]}]
267set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[64]}]
268set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[65]}]
269set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[66]}]
270set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[67]}]
271set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[68]}]
272set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[69]}]
273set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[6]}]
274set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[70]}]
275set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[71]}]
276set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[72]}]
277set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[73]}]
278set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[74]}]
279set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[75]}]
280set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[76]}]
281set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[77]}]
282set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[78]}]
283set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[79]}]
284set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[7]}]
285set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[80]}]
286set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[81]}]
287set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[82]}]
288set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[83]}]
289set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[84]}]
290set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[85]}]
291set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[86]}]
292set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[87]}]
293set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[88]}]
294set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[89]}]
295set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[8]}]
296set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[90]}]
297set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[91]}]
298set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[92]}]
299set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[93]}]
300set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[94]}]
301set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[95]}]
302set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[96]}]
303set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[97]}]
304set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[98]}]
305set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[99]}]
306set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[9]}]
307set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}]
308set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}]
309set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}]
310set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}]
311set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}]
312set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}]
313set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}]
314set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}]
315set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}]
316set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}]
317set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}]
318set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}]
319set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}]
320set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}]
321set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}]
322set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}]
323set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}]
324set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}]
325set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}]
326set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}]
327set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}]
328set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}]
329set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}]
330set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}]
331set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}]
332set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}]
333set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}]
334set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}]
335set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}]
336set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}]
337set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}]
338set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}]
339set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}]
340set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
341set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
342set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
343set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
344set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
345set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
346set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
347set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
348set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
349set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
350set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
351set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
352set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
353set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
354set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
355set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
356set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
357set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
358set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
359set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
360set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
361set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
362set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
363set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
364set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
365set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
366set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
367set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
368set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
369set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
370set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
371set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
372set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
373set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}]
374set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}]
375set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}]
376set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}]
377set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_stb_i}]
378set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_we_i}]
379set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}]
380set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}]
381set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}]
382set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}]
383set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}]
384set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}]
385set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}]
386set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}]
387set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}]
388set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}]
389set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}]
390set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}]
391set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}]
392set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}]
393set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}]
394set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}]
395set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}]
396set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}]
397set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}]
398set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}]
399set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}]
400set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}]
401set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}]
402set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}]
403set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}]
404set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}]
405set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}]
406set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}]
407set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}]
408set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}]
409set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}]
410set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}]
411set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}]
412set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}]
413set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}]
414set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}]
415set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}]
416set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}]
417set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}]
418set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}]
419set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}]
420set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}]
421set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}]
422set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}]
423set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}]
424set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}]
425set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}]
426set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}]
427set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}]
428set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}]
429set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}]
430set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}]
431set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}]
432set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}]
433set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}]
434set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}]
435set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}]
436set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}]
437set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}]
438set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}]
439set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}]
440set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}]
441set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}]
442set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}]
443set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}]
444set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}]
445set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}]
446set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}]
447set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}]
448set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}]
449set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}]
450set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}]
451set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}]
452set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}]
453set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}]
454set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}]
455set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}]
456set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}]
457set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}]
458set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[0]}]
459set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[100]}]
460set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[101]}]
461set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[102]}]
462set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[103]}]
463set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[104]}]
464set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[105]}]
465set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[106]}]
466set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[107]}]
467set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[108]}]
468set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[109]}]
469set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[10]}]
470set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[110]}]
471set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[111]}]
472set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[112]}]
473set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[113]}]
474set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[114]}]
475set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[115]}]
476set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[116]}]
477set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[117]}]
478set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[118]}]
479set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[119]}]
480set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[11]}]
481set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[120]}]
482set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[121]}]
483set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[122]}]
484set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[123]}]
485set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[124]}]
486set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[125]}]
487set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[126]}]
488set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[127]}]
489set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[12]}]
490set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[13]}]
491set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[14]}]
492set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[15]}]
493set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[16]}]
494set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[17]}]
495set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[18]}]
496set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[19]}]
497set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[1]}]
498set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[20]}]
499set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[21]}]
500set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[22]}]
501set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[23]}]
502set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[24]}]
503set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[25]}]
504set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[26]}]
505set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[27]}]
506set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[28]}]
507set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[29]}]
508set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[2]}]
509set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[30]}]
510set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[31]}]
511set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[32]}]
512set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[33]}]
513set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[34]}]
514set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[35]}]
515set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[36]}]
516set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[37]}]
517set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[38]}]
518set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[39]}]
519set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[3]}]
520set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[40]}]
521set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[41]}]
522set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[42]}]
523set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[43]}]
524set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[44]}]
525set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[45]}]
526set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[46]}]
527set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[47]}]
528set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[48]}]
529set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[49]}]
530set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[4]}]
531set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[50]}]
532set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[51]}]
533set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[52]}]
534set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[53]}]
535set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[54]}]
536set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[55]}]
537set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[56]}]
538set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[57]}]
539set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[58]}]
540set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[59]}]
541set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[5]}]
542set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[60]}]
543set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[61]}]
544set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[62]}]
545set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[63]}]
546set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[64]}]
547set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[65]}]
548set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[66]}]
549set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[67]}]
550set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[68]}]
551set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[69]}]
552set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[6]}]
553set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[70]}]
554set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[71]}]
555set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[72]}]
556set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[73]}]
557set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[74]}]
558set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[75]}]
559set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[76]}]
560set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[77]}]
561set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[78]}]
562set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[79]}]
563set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[7]}]
564set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[80]}]
565set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[81]}]
566set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[82]}]
567set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[83]}]
568set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[84]}]
569set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[85]}]
570set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[86]}]
571set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[87]}]
572set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[88]}]
573set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[89]}]
574set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[8]}]
575set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[90]}]
576set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[91]}]
577set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[92]}]
578set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[93]}]
579set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[94]}]
580set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[95]}]
581set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[96]}]
582set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[97]}]
583set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[98]}]
584set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[99]}]
585set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[9]}]
586set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_ack_o}]
587set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
588set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
589set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
590set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
591set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
592set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
593set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
594set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
595set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
596set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
597set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
598set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
599set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
600set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
601set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
602set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
603set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
604set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
605set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
606set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
607set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
608set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
609set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
610set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
611set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
612set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
613set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
614set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
615set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
616set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
617set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
618set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
619###############################################################################
620# Environment
621###############################################################################
622set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
623set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
624set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
625set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
626set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
627set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
628set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
629set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
630set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
631set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
632set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
633set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
634set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
635set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
636set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
637set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
638set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
639set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
640set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
641set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
642set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
643set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
644set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
645set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
646set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
647set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
648set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
649set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
650set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
651set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
652set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
653set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
654set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
655set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
656set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
657set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
658set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
659set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
660set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
661set_load -pin_load 0.0334 [get_ports {io_out[37]}]
662set_load -pin_load 0.0334 [get_ports {io_out[36]}]
663set_load -pin_load 0.0334 [get_ports {io_out[35]}]
664set_load -pin_load 0.0334 [get_ports {io_out[34]}]
665set_load -pin_load 0.0334 [get_ports {io_out[33]}]
666set_load -pin_load 0.0334 [get_ports {io_out[32]}]
667set_load -pin_load 0.0334 [get_ports {io_out[31]}]
668set_load -pin_load 0.0334 [get_ports {io_out[30]}]
669set_load -pin_load 0.0334 [get_ports {io_out[29]}]
670set_load -pin_load 0.0334 [get_ports {io_out[28]}]
671set_load -pin_load 0.0334 [get_ports {io_out[27]}]
672set_load -pin_load 0.0334 [get_ports {io_out[26]}]
673set_load -pin_load 0.0334 [get_ports {io_out[25]}]
674set_load -pin_load 0.0334 [get_ports {io_out[24]}]
675set_load -pin_load 0.0334 [get_ports {io_out[23]}]
676set_load -pin_load 0.0334 [get_ports {io_out[22]}]
677set_load -pin_load 0.0334 [get_ports {io_out[21]}]
678set_load -pin_load 0.0334 [get_ports {io_out[20]}]
679set_load -pin_load 0.0334 [get_ports {io_out[19]}]
680set_load -pin_load 0.0334 [get_ports {io_out[18]}]
681set_load -pin_load 0.0334 [get_ports {io_out[17]}]
682set_load -pin_load 0.0334 [get_ports {io_out[16]}]
683set_load -pin_load 0.0334 [get_ports {io_out[15]}]
684set_load -pin_load 0.0334 [get_ports {io_out[14]}]
685set_load -pin_load 0.0334 [get_ports {io_out[13]}]
686set_load -pin_load 0.0334 [get_ports {io_out[12]}]
687set_load -pin_load 0.0334 [get_ports {io_out[11]}]
688set_load -pin_load 0.0334 [get_ports {io_out[10]}]
689set_load -pin_load 0.0334 [get_ports {io_out[9]}]
690set_load -pin_load 0.0334 [get_ports {io_out[8]}]
691set_load -pin_load 0.0334 [get_ports {io_out[7]}]
692set_load -pin_load 0.0334 [get_ports {io_out[6]}]
693set_load -pin_load 0.0334 [get_ports {io_out[5]}]
694set_load -pin_load 0.0334 [get_ports {io_out[4]}]
695set_load -pin_load 0.0334 [get_ports {io_out[3]}]
696set_load -pin_load 0.0334 [get_ports {io_out[2]}]
697set_load -pin_load 0.0334 [get_ports {io_out[1]}]
698set_load -pin_load 0.0334 [get_ports {io_out[0]}]
699set_load -pin_load 0.0334 [get_ports {irq[2]}]
700set_load -pin_load 0.0334 [get_ports {irq[1]}]
701set_load -pin_load 0.0334 [get_ports {irq[0]}]
702set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
703set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
704set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
705set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
706set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
707set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
708set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
709set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
710set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
711set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
712set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
713set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
714set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
715set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
716set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
717set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
718set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
719set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
720set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
721set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
722set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
723set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
724set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
725set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
726set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
727set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
728set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
729set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
730set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
731set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
732set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
733set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
734set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
735set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
736set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
737set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
738set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
739set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
740set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
741set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
742set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
743set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
744set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
745set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
746set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
747set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
748set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
749set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
750set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
751set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
752set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
753set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
754set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
755set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
756set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
757set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
758set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
759set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
760set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
761set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
762set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
763set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
764set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
765set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
766set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
767set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
768set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
769set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
770set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
771set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
772set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
773set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
774set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
775set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
776set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
777set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
778set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
779set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
780set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
781set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
782set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
783set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
784set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
785set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
786set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
787set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
788set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
789set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
790set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
791set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
792set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
793set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
794set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
795set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
796set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
797set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
798set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
799set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
800set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
801set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
802set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
803set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
804set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
805set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
806set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
807set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
808set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
809set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
810set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
811set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
812set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
813set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
814set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
815set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
816set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
817set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
818set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
819set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
820set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
821set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
822set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
823set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
824set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
825set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
826set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
827set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
828set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
829set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
830set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
831set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
832set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
833set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
834set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
835set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
836set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
837set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
838set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
839set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
840set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
841set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
842set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
843set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
844set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
845set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
846set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
847set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
848set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
849set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
850set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
851set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
852set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
853set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
854set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
855set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
856set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
857set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
858set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
859set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
860set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
861set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
862set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
863set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
864set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
865set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
866set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
867set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
868set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
869set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
870set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
871set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
872set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
873set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
874set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
875set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
876set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
877set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
878set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
879set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
880set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
881set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
882set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
883set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
884set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
885set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
886set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
887set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
888set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
889set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
890set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
891set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
892set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
893set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
894set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
895set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
896set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
897set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
898set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
899set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
900set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
901set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
902set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
903set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
904set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
905set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
906set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
907set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
908set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
909set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
910set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}]
911set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}]
912set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}]
913set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
914set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}]
915set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}]
916set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}]
917set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}]
918set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}]
919set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}]
920set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}]
921set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}]
922set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}]
923set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}]
924set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}]
925set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}]
926set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}]
927set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}]
928set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}]
929set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}]
930set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}]
931set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}]
932set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}]
933set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}]
934set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}]
935set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}]
936set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}]
937set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}]
938set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}]
939set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}]
940set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}]
941set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}]
942set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}]
943set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}]
944set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}]
945set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}]
946set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}]
947set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}]
948set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}]
949set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}]
950set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}]
951set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}]
952set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}]
953set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}]
954set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[78]}]
955set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[77]}]
956set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[76]}]
957set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[75]}]
958set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[74]}]
959set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[73]}]
960set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[72]}]
961set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[71]}]
962set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[70]}]
963set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[69]}]
964set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[68]}]
965set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[67]}]
966set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[66]}]
967set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[65]}]
968set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[64]}]
969set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[63]}]
970set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[62]}]
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978set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[54]}]
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980set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[52]}]
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1116set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[44]}]
1117set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[43]}]
1118set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[42]}]
1119set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[41]}]
1120set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[40]}]
1121set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[39]}]
1122set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[38]}]
1123set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[37]}]
1124set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[36]}]
1125set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[35]}]
1126set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[34]}]
1127set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[33]}]
1128set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[32]}]
1129set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[31]}]
1130set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}]
1131set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}]
1132set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}]
1133set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}]
1134set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}]
1135set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[25]}]
1136set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[24]}]
1137set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}]
1138set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}]
1139set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}]
1140set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}]
1141set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}]
1142set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}]
1143set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}]
1144set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}]
1145set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}]
1146set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}]
1147set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}]
1148set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
1149set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
1150set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}]
1151set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}]
1152set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
1153set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
1154set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
1155set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
1156set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
1157set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
1158set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
1159set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
1160set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
1161set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
1162set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
1163set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
1164set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
1165set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
1166set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
1167set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
1168set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
1169set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
1170set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
1171set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
1172set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
1173set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
1174set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
1175set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
1176set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
1177set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
1178set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
1179set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
1180set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
1181set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
1182set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
1183set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
1184set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
1185set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
1186set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
1187set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
1188set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
1189set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
1190set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
1191set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
1192set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
1193set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
1194set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
1195set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
1196set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
1197set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
1198set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
1199set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
1200set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
1201set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
1202set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
1203set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
1204set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
1205set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
1206set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
1207set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
1208set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
1209set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
1210set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
1211set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
1212set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
1213set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
1214set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
1215set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
1216set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
1217set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
1218set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
1219set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
1220set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
1221set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
1222set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
1223set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
1224set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
1225set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
1226set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
1227set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
1228set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
1229set_timing_derate -early 0.9500
1230set_timing_derate -late 1.0500
1231###############################################################################
1232# Design Rules
1233###############################################################################
1234set_max_fanout 5.0000 [current_design]