Fixed off by one error on the default PWM top compare value.
diff --git a/verilog/rtl/Peripherals/PWM/PWMDevice.v b/verilog/rtl/Peripherals/PWM/PWMDevice.v
index d9a43c9..d20a219 100644
--- a/verilog/rtl/Peripherals/PWM/PWMDevice.v
+++ b/verilog/rtl/Peripherals/PWM/PWMDevice.v
@@ -91,9 +91,9 @@
assign riseInterruptEnable = configuration[(1 + CLOCK_BITS + (OUTPUTS * 3))-1:1 + CLOCK_BITS + (OUTPUTS * 2)];
assign fallInterruptEnable = configuration[(1 + CLOCK_BITS + (OUTPUTS * 4))-1:1 + CLOCK_BITS + (OUTPUTS * 3)];
- // Counter top compare Default 0x1388 (for .WIDTH(16))
+ // Counter top compare Default 0x1387 (for .WIDTH(16))
// With clockScale=0x03, this gives a 1kHz signal with a 200ns resolution
- localparam DEFAULT_TOP_COMPARE_VALUE = 'h1388;
+ localparam DEFAULT_TOP_COMPARE_VALUE = 'h1387;
wire[31:0] topCompareRegisterOutputData;
wire topCompareRegisterOutputRequest;
wire topCompareRegisterBusBusy_nc;
