commit	f243118ddda6f76255cfb8607a15bfe075ea0596	[log] [tgz]
author	Charlie <charlie.david.smith@hotmail.co.uk>	Sat May 07 19:34:04 2022 +0100
committer	Charlie <charlie.david.smith@hotmail.co.uk>	Sat May 07 19:34:04 2022 +0100
tree	a0706160cc87b1fc67fa54c969c6064db73e78b6
parent	d62bdfee38975ffd7b1839f8110f60d5e562b44d [diff]

Updated collate errors script to include all log and report files. Also disabled a number of warnings. However, a better method of disabling warnings is needed.

docs/Logs/CollateErrors.py[diff]

1 file changed

tree: a0706160cc87b1fc67fa54c969c6064db73e78b6

README.md

ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program.

Features

Block diagram of Experiar SoC

Dual RV32I cores
Per core SRAM
External flash controller
Larger shared block SRAM
VGA output using frame buffer in block SRAM
4x UART ports + 1 internal to caravel
2x SPI ports
4x PWM counters with 4x seperate outputs
DMA for UART peripheral

ToDo

Flash controller
DMA
Block SRAM
VGA
Multi core controller
Fix all of the timeing errors
Test

Reference work and inspiration

Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.
Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
Caravel Documentation: Reference for caravel and configuration.