commit	d62bdfee38975ffd7b1839f8110f60d5e562b44d	[log] [tgz]
author	Charlie <charlie.david.smith@hotmail.co.uk>	Sat May 07 19:31:28 2022 +0100
committer	Charlie <charlie.david.smith@hotmail.co.uk>	Sat May 07 19:31:28 2022 +0100
tree	ebe1c6ff42c59bb839d777260293d9e7694b54f1
parent	14a14af2b1bf4567a600968bf3d3f984a8c45186 [diff]

Updated readme to add block diagram, features list, and ToDo list.

README.md[diff]

1 file changed

tree: ebe1c6ff42c59bb839d777260293d9e7694b54f1

README.md

ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program.

Features

Block diagram of Experiar SoC

Dual RV32I cores
Per core SRAM
External flash controller
Larger shared block SRAM
VGA output using frame buffer in block SRAM
4x UART ports + 1 internal to caravel
2x SPI ports
4x PWM counters with 4x seperate outputs
DMA for UART peripheral

ToDo

Flash controller
DMA
Block SRAM
VGA
Multi core controller
Fix all of the timeing errors
Test

Reference work and inspiration

Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.
Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
Caravel Documentation: Reference for caravel and configuration.