Fixed UART sending a single bit of data on reset.

verilog/rtl/Peripherals/UART/UART_tx.v

diff --git a/verilog/rtl/Peripherals/UART/UART_tx.v b/verilog/rtl/Peripherals/UART/UART_tx.v
index be0e7cd..6c78d5b 100644
--- a/verilog/rtl/Peripherals/UART/UART_tx.v
+++ b/verilog/rtl/Peripherals/UART/UART_tx.v
@@ -32,7 +32,7 @@
 			delayCounter = {CLOCK_SCALE_BITS{1'b0}};
 			bitCounter = 3'b0;
 			savedData = 8'b0;
-			outputBuffer = 1'b0;
+			outputBuffer = 1'b1;
 		end else begin
 			busy = 1'b1;