commit e851b8afcd11bd89694aa53c39a0442f2c15ed60
author Charlie <charlie.david.smith@hotmail.co.uk> Sat May 21 18:41:48 2022 +0100
committer Charlie <charlie.david.smith@hotmail.co.uk> Sat May 21 18:41:48 2022 +0100
tree b4d777ee89c83bbdba260b9a3918daa3675dae7d
parent aeb29be39dde00816e99bc4e953e19e82af39668

Fixed UART sending a single bit of data on reset.

verilog/rtl/Peripherals/UART/UART_tx.v

diff --git a/verilog/rtl/Peripherals/UART/UART_tx.v b/verilog/rtl/Peripherals/UART/UART_tx.v
index be0e7cd..6c78d5b 100644
--- a/verilog/rtl/Peripherals/UART/UART_tx.v
+++ b/verilog/rtl/Peripherals/UART/UART_tx.v
@@ -32,7 +32,7 @@
 			delayCounter = {CLOCK_SCALE_BITS{1'b0}};
 			bitCounter = 3'b0;
 			savedData = 8'b0;
-			outputBuffer = 1'b0;
+			outputBuffer = 1'b1;
 		end else begin
 			busy = 1'b1;