Fixed arithmetic right shifts not sign extending correctly.

verilog/rtl/ExperiarCore/RV32ICore.v

diff --git a/verilog/rtl/ExperiarCore/RV32ICore.v b/verilog/rtl/ExperiarCore/RV32ICore.v
index ef8d754..4017da8 100644
--- a/verilog/rtl/ExperiarCore/RV32ICore.v
+++ b/verilog/rtl/ExperiarCore/RV32ICore.v
@@ -254,7 +254,8 @@
 
 	wire isLeftShift = funct3 == 3'b001;
 	wire[31:0] shiftInput = isLeftShift ? flipBits32(inputA) : inputA;
-	wire[31:0] aluShifter = $signed({ aluAlt && shiftInput[31] && !isLeftShift, shiftInput } >>> inputB[4:0]);
+	wire signed[32:0] signedShiftInput = { aluAlt && shiftInput[31] && !isLeftShift, shiftInput };
+	wire[32:0] aluShifter = $signed(signedShiftInput >>> inputB[4:0]);
 	wire[31:0] rightShift = aluShifter[31:0];
 	wire[31:0] leftShift = flipBits32(rightShift);