Fixed that the PWM device was using a wildly wrong reset value.

verilog/rtl/Peripherals/PWM/PWMDevice.v

diff --git a/verilog/rtl/Peripherals/PWM/PWMDevice.v b/verilog/rtl/Peripherals/PWM/PWMDevice.v
index 7e3402d..4bbff18 100644
--- a/verilog/rtl/Peripherals/PWM/PWMDevice.v
+++ b/verilog/rtl/Peripherals/PWM/PWMDevice.v
@@ -69,6 +69,7 @@
 	wire[31:0] configurationRegisterOutputData;
 	wire configurationRegisterOutputRequest;
 	ConfigurationRegister #(.WIDTH(CONFIG_WIDTH), .ADDRESS(12'h000), .DEFAULT({CONFIG_WIDTH{12'h3DC}})) configurationRegister(
+	ConfigurationRegister #(.WIDTH(CONFIG_WIDTH), .ADDRESS(12'h000), .DEFAULT({ {(CONFIG_WIDTH-5){1'b0}}, 5'h0E })) configurationRegister(
 		.clk(clk),
 		.rst(rst),
 		.enable(deviceEnable),