Fixed a number of small issues.
diff --git a/verilog/dv/coreArch/coreArch_tb.v b/verilog/dv/coreArch/coreArch_tb.v index c83f4aa..a5ebb34 100644 --- a/verilog/dv/coreArch/coreArch_tb.v +++ b/verilog/dv/coreArch/coreArch_tb.v
@@ -30,17 +30,19 @@ wire[31:0] memoryDataWrite; wire[31:0] memoryDataRead; wire memoryBusy = 1'b0; + wire memoryAccessFault = 1'b0; wire management_run = 1'b1; wire management_trapEnable = 1'b1; + wire management_interruptEnable = 1'b1; wire management_writeEnable = 1'b0; wire[3:0] management_byteSelect = 4'b0000; wire[15:0] management_address = 'b0; wire[31:0] management_writeData = 'b0; wire[31:0] management_readData; - wire eCall; - wire eBreak; + wire isAddressBreakpoint = 1'b0; + wire[15:0] userInterrupts = 16'b0; wire[1:0] probe_state; wire[1:0] probe_env; @@ -71,7 +73,6 @@ $display("CODE_END: 0x%h", 32'h`CODE_END); wait((probe_programCounter == 32'h`CODE_END) || (|probe_errorCode)); - //wait(eBreak || (|probe_errorCode)); #50 @@ -184,8 +185,10 @@ .memoryDataWrite(memoryDataWrite), .memoryDataRead(memoryDataRead), .memoryBusy(memoryBusy), + .memoryAccessFault(memoryAccessFault), .management_run(management_run), .management_trapEnable(management_trapEnable), + .management_interruptEnable(management_interruptEnable), .management_writeEnable(management_writeEnable), .management_byteSelect(management_byteSelect), .management_address(management_address), @@ -196,8 +199,8 @@ .partID(16'hCD55), .versionID(4'h0), .extensions(CORE_EXTENSIONS), - .eCall(eCall), - .eBreak(eBreak), + .isAddressBreakpoint(isAddressBreakpoint), + .userInterrupts(userInterrupts), .probe_state(probe_state), .probe_env(probe_env), .probe_programCounter(probe_programCounter),
diff --git a/verilog/dv/peripheralsGPIO/peripheralsGPIO.c b/verilog/dv/peripheralsGPIO/peripheralsGPIO.c index d722d5b..c9705cb 100644 --- a/verilog/dv/peripheralsGPIO/peripheralsGPIO.c +++ b/verilog/dv/peripheralsGPIO/peripheralsGPIO.c
@@ -115,7 +115,7 @@ reg_wb_enable = 1; // Enable GPIO - reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL; reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
diff --git a/verilog/rtl/CaravelHost/CaravelHost_top.v b/verilog/rtl/CaravelHost/CaravelHost_top.v index 88d699a..d3df1ba 100644 --- a/verilog/rtl/CaravelHost/CaravelHost_top.v +++ b/verilog/rtl/CaravelHost/CaravelHost_top.v
@@ -33,7 +33,7 @@ output wire caravel_uart_tx, // Caravel IRQ - output wire[2:0] caravel_irq, + output wire[3:0] caravel_irq, // Configuration constants output wire[7:0] core0Index,
diff --git a/verilog/rtl/ExperiarCore/ExperiarCore_top.v b/verilog/rtl/ExperiarCore/ExperiarCore_top.v index 6723dc8..a3881c5 100644 --- a/verilog/rtl/ExperiarCore/ExperiarCore_top.v +++ b/verilog/rtl/ExperiarCore/ExperiarCore_top.v
@@ -109,6 +109,7 @@ wire[31:0] coreMemoryDataWrite; wire[31:0] coreMemoryDataRead; wire coreMemoryBusy; + wire coreMemoryAccessFault = 1'b0; // Memory interface from core to local memory wire coreLocalMemoryWriteEnable; @@ -226,6 +227,7 @@ .memoryDataWrite(coreMemoryDataWrite), .memoryDataRead(coreMemoryDataRead), .memoryBusy(coreMemoryBusy), + .memoryAccessFault(coreMemoryAccessFault), .management_run(management_run), .management_trapEnable(management_trapEnable), .management_interruptEnable(management_interruptEnable), @@ -239,8 +241,6 @@ .partID(partID), .versionID(versionID), .extensions(CORE_EXTENSIONS), - .eCall(eCall), - .eBreak(eBreak), .isAddressBreakpoint(isAddressBreakpoint), .userInterrupts(irq), .probe_state(probe_state),
diff --git a/verilog/rtl/ExperiarCore/RV32ICore.v b/verilog/rtl/ExperiarCore/RV32ICore.v index babbaf4..640f073 100644 --- a/verilog/rtl/ExperiarCore/RV32ICore.v +++ b/verilog/rtl/ExperiarCore/RV32ICore.v
@@ -15,6 +15,7 @@ output wire[31:0] memoryDataWrite, input wire[31:0] memoryDataRead, input wire memoryBusy, + input wire memoryAccessFault, // Management interface input wire management_run, @@ -33,10 +34,6 @@ input wire[3:0] versionID, input wire[25:0] extensions, - // System commands - output wire eCall, - output wire eBreak, - // Traps input wire isAddressBreakpoint, input wire[15:0] userInterrupts, @@ -512,6 +509,10 @@ assign eBreak = isEBREAK && (state == STATE_EXECUTE); wire trapReturn = isRET && (state == STATE_EXECUTE); + wire isMachineTimerInterrupt = 1'b0; + wire isMachineExternalInterrupt = 1'b0; + wire isMachineSoftwareInterrupt = 1'b0; + // CSRs wire instructionCompleted = (state == STATE_EXECUTE) && progressExecute; CSR csr( @@ -538,7 +539,7 @@ .isMachineSoftwareInterrupt(isMachineSoftwareInterrupt), .isAddressMisaligned(isAddressMisaligned), .isJumpMissaligned(jumpMissaligned), - .isAccessFault(isAccessFault), + .isAccessFault(memoryAccessFault), .isInvalidInstruction(isInvalidInstruction), .isEBREAK(eBreak), .isECALL(eCall),
diff --git a/verilog/rtl/ExperiarSoC/ExperiarSoC_top.v b/verilog/rtl/ExperiarSoC/ExperiarSoC_top.v index 409a830..7c7d51d 100644 --- a/verilog/rtl/ExperiarSoC/ExperiarSoC_top.v +++ b/verilog/rtl/ExperiarSoC/ExperiarSoC_top.v
@@ -27,7 +27,7 @@ // Caravel input wire caravel_uart_rx, output wire caravel_uart_tx, - input wire[2:0] caravel_irq, + input wire[3:0] caravel_irq, // Logic Analyzer Signals input wire[127:0] la_data_in,
diff --git a/verilog/rtl/Flash/Flash_top.v b/verilog/rtl/Flash/Flash_top.v index 9675922..16370a2 100644 --- a/verilog/rtl/Flash/Flash_top.v +++ b/verilog/rtl/Flash/Flash_top.v
@@ -109,8 +109,8 @@ // QSPI controller QSPIDevice #(.CLOCK_WIDTH(8)) qspiDevice ( - .clk(clk), - .rst(rst), + .clk(wb_clk_i), + .rst(wb_rst_i), .dataRequest_address(dataRequest_address), .dataRequest_enable(dataRequest_enable), .dataRequest_data(dataRequest_data),
diff --git a/verilog/rtl/Video/Video_top.v b/verilog/rtl/Video/Video_top.v index 940776c..c7bd6ad 100644 --- a/verilog/rtl/Video/Video_top.v +++ b/verilog/rtl/Video/Video_top.v
@@ -104,6 +104,7 @@ wire videoMemoryBusBusy; wire[31:0] videoMemoryDataRead; wire videoMemoryRequestOutput; + wire vga_fetchData; VideoMemory videoMemory( `ifdef USE_POWER_PINS .vccd1(vccd1), // User area 1 1.8V power