blob: f4747b15f36a01b78eefea2aa417a80ed85e79df [file] [log] [blame]
# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarSoC/ExperiarSoC_top.v
-v $(USER_PROJECT_VERILOG)/rtl/CaravelHost/CaravelHost_top.v
-v $(USER_PROJECT_VERILOG)/rtl/CaravelHost/WBAddressExtension.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/ExperiarCore_top.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/CoreManagement.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/RV32ICore.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/JTAG.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/JTAGRegister.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/Memory/MemoryController.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/Wishbone/Core_WBInterface.v
-v $(USER_PROJECT_VERILOG)/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
-v $(USER_PROJECT_VERILOG)/rtl/Flash/Flash_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Flash/FlashBuffer.v
-v $(USER_PROJECT_VERILOG)/rtl/Flash/QSPIDevice.v
-v $(USER_PROJECT_VERILOG)/rtl/Flash/WBFlashInterface.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/Peripherals_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/GPIO/GPIO_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/GPIO/GPIODevice.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/IOMultiplexer/IOMultiplexer_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/PWM/PWM_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/PWM/PWMDevice.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/PWM/PWMOutput.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/SPI/SPI_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/SPI/SPIDevice.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/UART/UART_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/UART/UARTDevice.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/UART/UART_rx.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/UART/UART_tx.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/Registers/ConfigurationRegister.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/Registers/DataRegister.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/Registers/DeviceSelect.v
-v $(USER_PROJECT_VERILOG)/rtl/Peripherals/Registers/PeripheralSelect.v
-v $(USER_PROJECT_VERILOG)/rtl/Video/Video_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Video/VideoMemory_top.v
-v $(USER_PROJECT_VERILOG)/rtl/Video/VGA_top.v
-v $(USER_PROJECT_VERILOG)/rtl/WishboneInterconnect/WishboneInterconnect_top.v
-v $(USER_PROJECT_VERILOG)/rtl/WishboneInterconnect/WishboneMultiMasterSlave.v
-v $(USER_PROJECT_VERILOG)/rtl/WishboneInterconnect/MasterArbiter.v
-v $(USER_PROJECT_VERILOG)/rtl/Utility/FIFO.v
-v $(USER_PROJECT_VERILOG)/rtl/Utility/Mux.v
-v $(USER_PROJECT_VERILOG)/rtl/Utility/ShiftRegister.v
-v $(USER_PROJECT_VERILOG)/rtl/Utility/Counter.v
-v $(USER_PROJECT_VERILOG)/rtl/Art/Art_top.v
# Make sure there is a blank line at the end, otherwise things wont work