verilog/dv/coreArch/riscof/ExperiarSoC/ExperiarSoC_isa.yaml

hart_ids: [0]
hart0:
  ISA: RV32I_Zicsr
  physical_addr_sz: 32
  User_Spec_Version: '2.3'
  supported_xlen: [32]
  hw_data_misaligned_support: false
  misa:
    reset-val: 0x40000100
    rv32:
      accessible: true
      mxl:
        implemented: true
        type:
            warl:
              dependency_fields: []
              legal:
                - mxl[1:0] in [0x1]
              wr_illegal:
                - Unchanged
      extensions:
        implemented: true
        type:
            warl:
              dependency_fields: []
              legal:
                - extensions[25:0] bitmask [0x0001104, 0x0000000]
              wr_illegal:
                - Unchanged