sdc/Video.sdc

###############################################################################
# Created by write_sdc
# Thu May 19 20:43:39 2022
###############################################################################
current_design Video
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name wb_clk_i -period 25.0000 [get_ports {wb_clk_i}]
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
set_clock_uncertainty 0.2500 wb_clk_i
set_propagated_clock [get_clocks {wb_clk_i}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[100]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[101]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[102]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[103]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[104]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[105]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[106]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[107]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[108]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[109]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[110]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[111]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[112]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[113]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[114]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[115]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[116]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[117]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[118]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[119]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[120]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[121]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[122]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[123]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[124]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[125]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[126]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[127]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[32]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[33]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[34]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[35]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[36]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[37]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[38]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[39]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[40]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[41]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[42]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[43]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[44]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[45]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[46]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[47]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[48]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[49]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[50]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[51]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[52]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[53]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[54]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[55]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[56]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[57]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[58]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[59]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[60]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[61]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[62]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[63]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[64]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[65]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[66]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[67]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[68]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[69]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[70]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[71]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[72]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[73]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[74]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[75]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[76]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[77]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[78]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[79]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[80]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[81]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[82]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[83]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[84]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[85]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[86]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[87]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[88]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[89]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[90]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[91]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[92]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[93]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[94]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[95]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[96]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[97]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[98]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[99]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout0[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[100]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[101]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[102]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[103]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[104]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[105]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[106]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[107]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[108]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[109]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[110]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[111]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[112]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[113]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[114]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[115]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[116]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[117]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[118]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[119]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[120]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[121]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[122]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[123]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[124]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[125]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[126]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[127]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[32]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[33]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[34]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[35]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[36]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[37]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[38]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[39]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[40]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[41]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[42]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[43]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[44]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[45]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[46]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[47]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[48]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[49]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[50]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[51]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[52]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[53]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[54]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[55]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[56]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[57]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[58]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[59]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[60]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[61]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[62]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[63]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[64]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[65]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[66]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[67]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[68]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[69]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[70]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[71]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[72]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[73]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[74]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[75]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[76]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[77]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[78]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[79]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[80]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[81]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[82]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[83]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[84]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[85]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[86]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[87]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[88]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[89]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[90]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[91]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[92]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[93]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[94]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[95]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[96]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[97]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[98]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[99]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_dout1[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[10]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[11]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[12]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[13]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[14]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[15]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[16]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[17]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[18]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[19]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[20]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[21]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[22]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[23]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[24]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[25]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[26]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[27]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[28]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[29]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[30]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[31]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[4]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[5]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[6]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[7]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[8]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[9]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[0]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[1]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[2]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[3]}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr0[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr0[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr0[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr0[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr0[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr0[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr0[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr0[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr0[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr1[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr1[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr1[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr1[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr1[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr1[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr1[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr1[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_addr1[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_clk0}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_clk1}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_csb0[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_csb0[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_csb0[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_csb0[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_csb1[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_csb1[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_csb1[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_csb1[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_din0[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_web0}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_wmask0[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_wmask0[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_wmask0[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_wmask0[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_b[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_b[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_g[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_g[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_hsync}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_r[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_r[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_vsync}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[0]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[10]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[11]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[12]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[13]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[14]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[15]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[16]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[17]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[18]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[19]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[1]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[20]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[21]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[22]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[23]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[24]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[25]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[26]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[27]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[28]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[29]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[2]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[30]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[31]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[3]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[4]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[5]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[6]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[7]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[8]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[9]}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_error_o}]
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stall_o}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {sram_clk0}]
set_load -pin_load 0.0334 [get_ports {sram_clk1}]
set_load -pin_load 0.0334 [get_ports {sram_web0}]
set_load -pin_load 0.0334 [get_ports {vga_hsync}]
set_load -pin_load 0.0334 [get_ports {vga_vsync}]
set_load -pin_load 0.0334 [get_ports {wb_ack_o}]
set_load -pin_load 0.0334 [get_ports {wb_error_o}]
set_load -pin_load 0.0334 [get_ports {wb_stall_o}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[8]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[7]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[6]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[5]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[4]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[3]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[2]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[1]}]
set_load -pin_load 0.0334 [get_ports {sram_addr0[0]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[8]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[7]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[6]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[5]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[4]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[3]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[2]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[1]}]
set_load -pin_load 0.0334 [get_ports {sram_addr1[0]}]
set_load -pin_load 0.0334 [get_ports {sram_csb0[3]}]
set_load -pin_load 0.0334 [get_ports {sram_csb0[2]}]
set_load -pin_load 0.0334 [get_ports {sram_csb0[1]}]
set_load -pin_load 0.0334 [get_ports {sram_csb0[0]}]
set_load -pin_load 0.0334 [get_ports {sram_csb1[3]}]
set_load -pin_load 0.0334 [get_ports {sram_csb1[2]}]
set_load -pin_load 0.0334 [get_ports {sram_csb1[1]}]
set_load -pin_load 0.0334 [get_ports {sram_csb1[0]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[31]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[30]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[29]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[28]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[27]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[26]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[25]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[24]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[23]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[22]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[21]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[20]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[19]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[18]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[17]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[16]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[15]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[14]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[13]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[12]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[11]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[10]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[9]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[8]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[7]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[6]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[5]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[4]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[3]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[2]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[1]}]
set_load -pin_load 0.0334 [get_ports {sram_din0[0]}]
set_load -pin_load 0.0334 [get_ports {sram_wmask0[3]}]
set_load -pin_load 0.0334 [get_ports {sram_wmask0[2]}]
set_load -pin_load 0.0334 [get_ports {sram_wmask0[1]}]
set_load -pin_load 0.0334 [get_ports {sram_wmask0[0]}]
set_load -pin_load 0.0334 [get_ports {vga_b[1]}]
set_load -pin_load 0.0334 [get_ports {vga_b[0]}]
set_load -pin_load 0.0334 [get_ports {vga_g[1]}]
set_load -pin_load 0.0334 [get_ports {vga_g[0]}]
set_load -pin_load 0.0334 [get_ports {vga_r[1]}]
set_load -pin_load 0.0334 [get_ports {vga_r[0]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[31]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[30]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[29]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[28]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[27]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[26]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[25]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[24]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[23]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[22]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[21]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[20]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[19]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[18]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[17]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[16]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[15]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[14]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[13]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[12]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[11]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[10]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[9]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[8]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[7]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[6]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[5]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[4]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[3]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[2]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[1]}]
set_load -pin_load 0.0334 [get_ports {wb_data_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_stb_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[127]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[126]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[125]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[124]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[123]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[122]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[121]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[120]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[119]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[118]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[117]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[116]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[115]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[114]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[113]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[112]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[111]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[110]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[109]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[108]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[107]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[106]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[105]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[104]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[103]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[102]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[101]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[100]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[99]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[98]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[97]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[96]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[95]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[94]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[93]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[92]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[91]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[90]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[89]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[88]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[87]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[86]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[85]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[84]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[83]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[82]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[81]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[80]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[79]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[78]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[77]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[76]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[75]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[74]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[73]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[72]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[71]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[70]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[69]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[68]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[67]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[66]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[65]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[64]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[63]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[62]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[61]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[60]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[59]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[58]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[57]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[56]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[55]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[54]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[53]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[52]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[51]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[50]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[49]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[48]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[47]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[46]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[45]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[44]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[43]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[42]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[41]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[40]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[39]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[38]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[127]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[126]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[125]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[124]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[123]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[122]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[121]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[120]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[119]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[118]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[117]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[116]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[115]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[114]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[113]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[112]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[111]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[110]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[109]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[108]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[107]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[106]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[105]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[104]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[103]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[102]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[101]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[100]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[99]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[98]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[97]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[96]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[95]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[94]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[93]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[92]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[91]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[90]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[89]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[88]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[87]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[86]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[85]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[84]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[83]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[82]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[81]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[80]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[79]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[78]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[77]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[76]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[75]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[74]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[73]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[72]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[71]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[70]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[69]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[68]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[67]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[66]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[65]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[64]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[63]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[62]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[61]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[60]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[59]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[58]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[57]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[56]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[55]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[54]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[53]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[52]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[51]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[50]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[49]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[48]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[47]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[46]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[45]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[44]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[43]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[42]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[41]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[40]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[39]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[38]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]