Added SPI test.
diff --git a/verilog/dv/peripheralsSPI/Makefile b/verilog/dv/peripheralsSPI/Makefile new file mode 100644 index 0000000..3fd0b56 --- /dev/null +++ b/verilog/dv/peripheralsSPI/Makefile
@@ -0,0 +1,32 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + + +include $(MCW_ROOT)/verilog/dv/make/env.makefile +include $(MCW_ROOT)/verilog/dv/make/var.makefile +include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +include $(MCW_ROOT)/verilog/dv/make/sim.makefile + +
diff --git a/verilog/dv/peripheralsSPI/peripheralsSPI.c b/verilog/dv/peripheralsSPI/peripheralsSPI.c new file mode 100644 index 0000000..cf20f1f --- /dev/null +++ b/verilog/dv/peripheralsSPI/peripheralsSPI.c
@@ -0,0 +1,174 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include <defs.h> +#include <stub.c> + +#define GPIO0_OE_WRITE_ADDR ((uint32_t*)0x33031000) +#define GPIO0_OE_SET_ADDR ((uint32_t*)0x33031004) +#define GPIO0_OE_CLEAR_ADDR ((uint32_t*)0x33031008) +#define GPIO0_OE_TOGGLE_ADDR ((uint32_t*)0x3303100C) +#define GPIO0_OUTPUT_WRITE_ADDR ((uint32_t*)0x33031010) +#define GPIO0_OUTPUT_SET_ADDR ((uint32_t*)0x33031014) +#define GPIO0_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33031018) +#define GPIO0_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303101C) +#define GPIO0_INPUT_ADDR ((uint32_t*)0x33031020) +#define GPIO1_OE_WRITE_ADDR ((uint32_t*)0x33032000) +#define GPIO1_OE_SET_ADDR ((uint32_t*)0x33032004) +#define GPIO1_OE_CLEAR_ADDR ((uint32_t*)0x33032008) +#define GPIO1_OE_TOGGLE_ADDR ((uint32_t*)0x3303200C) +#define GPIO1_OUTPUT_WRITE_ADDR ((uint32_t*)0x33032010) +#define GPIO1_OUTPUT_SET_ADDR ((uint32_t*)0x33032014) +#define GPIO1_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33032018) +#define GPIO1_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303201C) +#define GPIO1_INPUT_ADDR ((uint32_t*)0x33032020) + +#define SPI0_CONFIGURATION_REGISTER ((uint32_t*)0x33011000) +#define SPI0_STATUS_REGISTER ((uint32_t*)0x33011004) +#define SPI0_DATA ((uint32_t*)0x33011008) + +#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000) +#define MPRJ_WB_DATA_LOCATION 0x30008000 + +void wbWrite (uint32_t* location, uint32_t value) +{ + // Write the address + uint32_t locationData = (uint32_t)location; + MPRJ_WB_ADDRESS = locationData & 0xFFFF8000; + + // Write the data + uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION; + *((volatile uint32_t*)writeAddress) = value; +} + +uint32_t wbRead (uint32_t* location) +{ + // Write the address + uint32_t locationData = (uint32_t)location; + MPRJ_WB_ADDRESS = locationData & 0xFFFF8000; + + // Write the data + uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION; + return *((volatile uint32_t*)writeAddress); +} + +void nextTest (bool testPassing) +{ + if (testPassing) + { + wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x03000); + } + else + { + wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x01000); + wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x02000); + } + + wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000); +} + +void main () +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* Set up the housekeeping SPI to be connected internally so */ + /* that external pin changes don't affect it. */ + + // Connect the housekeeping SPI to the SPI master + // so that the CSB line is not left floating. This allows + // all of the GPIO pins to be used for user functions. + + // https://github.com/efabless/caravel/blob/main/docs/other/gpio.txt + + // Enable the wishbone bus + reg_wb_enable = 1; + + // Enable GPIO + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1) {} + + // Setup test output + bool testPass = true; + wbWrite (GPIO0_OUTPUT_WRITE_ADDR, 0x01000); + wbWrite (GPIO0_OE_WRITE_ADDR, ~0x03000); + + // Write clock high and low to test target is correctly using chip select + // Set chip select high first for its default value + wbWrite (GPIO1_OE_WRITE_ADDR, ~0x48); + wbWrite (GPIO1_OUTPUT_SET_ADDR, 0x40); + wbWrite (GPIO1_OUTPUT_SET_ADDR, 0x08); + wbWrite (GPIO1_OUTPUT_CLEAR_ADDR, 0x08); + + // Check device 0 config + // b00-b02: clockScale Default 0x4 + // b03-04: spiMode Default 0x0 + // b05: msbFirst Default 0x1 + // b06: useCS Default 0x1 + // b07: activeHighCS Default 0x0 + // b08: enable Default 0x0 + uint32_t device0Config = (0b1 << 8) | (0b11 << 5) | 0x04; + wbWrite (SPI0_CONFIGURATION_REGISTER, device0Config); + if (wbRead (SPI0_CONFIGURATION_REGISTER) != device0Config) testPass = false; + nextTest (testPass); + + // Write fist test byte + wbWrite (SPI0_DATA, 0x1F); + + // Check device isn't busy + if (wbRead (SPI0_STATUS_REGISTER) != 0) testPass = false; + nextTest (testPass); + + // Check data data was received + if (wbRead (SPI0_DATA) != 0xC5) testPass = false; + nextTest (testPass); + + // Write second test byte + wbWrite (SPI0_DATA, 0xA3); + + // Check data received back is correct + // This should be the first test byte + if (wbRead (SPI0_DATA) != 0x1F) testPass = false; + + // Write third test byte for timing test + wbWrite (SPI0_DATA, 0x9B); + + // Finish test + nextTest (testPass); +}
diff --git a/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v b/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v new file mode 100644 index 0000000..7ab770f --- /dev/null +++ b/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v
@@ -0,0 +1,262 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 1 ps + +module peripheralsSPI_tb; + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + + wire sck = mprj_io[22]; + wire mosi = mprj_io[23]; + wire miso; + assign mprj_io[24] = miso; + wire chipSelect = mprj_io[25]; + + reg[7:0] shiftValue; + assign miso = shiftValue[7]; + + wire succesOutput = mprj_io[12]; + wire nextTestOutput = mprj_io[13]; + reg timingValid = 1'b1; + + pullup(mprj_io[3]); + assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + always #12.5 clock <= (clock === 1'b0); + + // Need to add pulls (can be up or down) to all unsed io so that input data is known + assign mprj_io[2:0] = 3'b0; + assign mprj_io[11:4] = 8'b0; + assign mprj_io[21:17] = 5'b0; + assign mprj_io[37:26] = 12'b0; + + always @(posedge sck) begin + if (!chipSelect) shiftValue <= { shiftValue[7:1], mosi }; + end + + initial begin + clock = 0; + timingValid = 1'b1; + shiftValue = 8'hC5; + end + + realtime timerStart; + realtime timerLength; + + initial begin + $dumpfile("peripheralsSPI.vcd"); + +`ifdef SIM + $dumpvars(0, peripheralsSPI_tb); +`else + $dumpvars(1, peripheralsSPI_tb); + $dumpvars(2, peripheralsSPI_tb.uut.mprj); +`endif + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (200) begin + repeat (1000) @(posedge clock); + //$display("+1000 cycles"); + end + $display("%c[1;35m",27); + `ifdef GL + $display ("Monitor: Timeout, Peripherals SPI Test (GL) Failed"); + `else + $display ("Monitor: Timeout, Peripherals SPI Test (RTL) Failed"); + `endif + $display("%c[0m",27); + $finish; + end + + initial begin + + // Wait for clock signal + @(posedge chipSelect); + @(posedge sck); + @(posedge sck); + + // Check device 0 config + @(posedge nextTestOutput); + + // Check that the first byte was received correctly + wait(shiftValue == 8'h1F); + + // Check device isn't busy + @(posedge nextTestOutput); + + // Check data data was received + @(posedge nextTestOutput); + + // Check that CS is asserted + wait(chipSelect == 1'b0); + + // Check that the second byte was received correctly + wait(shiftValue == 8'hA3); + + // Check that CS is cleared + wait(chipSelect == 1'b1); + + // Check data received back in + @(posedge nextTestOutput); + + // Check that the third byte was received correctly + wait(shiftValue == 8'h9B); + + // Check clock period is correct + // Wait for signal start + @(negedge sck); + timerStart = $realtime; + + // Low time + @(posedge sck); + timerLength = $realtime - timerStart; + $display("SCK Low Time: ", timerLength); + if (timerLength < 190 || timerLength > 210) timingValid = 1'b0; + else $display("Invalid time, should be between 190 and 210"); + + // Period + @(negedge sck); + timerLength = $realtime - timerStart; + $display("SCK Period: ", timerLength); + if (timerLength < 390 || timerLength > 410) timingValid = 1'b0; + else $display("Invalid time, should be between 390 and 410"); + + + // Wait for management core to output the final output test result + @(posedge nextTestOutput); + + if (!timingValid) begin + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Peripherals SPI Timing (GL) Failed"); + `else + $display ("Monitor: Peripherals SPI Timing (RTL) Failed"); + `endif + $display("%c[0m",27); + end else if (succesOutput) begin + $display("%c[1;92m",27); + `ifdef GL + $display("Monitor: Peripherals SPI Test (GL) Passed"); + `else + $display("Monitor: Peripherals SPI Test (RTL) Passed"); + `endif + $display("%c[0m",27); + end else begin + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Peripherals SPI Test (GL) Failed"); + `else + $display ("Monitor: Peripherals SPI Test (RTL) Failed"); + `endif + $display("%c[0m",27); + end + $finish; + end + + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #300000; + CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #100; + power1 <= 1'b1; + #100; + power2 <= 1'b1; + #100; + power3 <= 1'b1; + #100; + power4 <= 1'b1; + end + + always @(succesOutput, nextTestOutput, timingValid) begin + #1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3; + wire VDD1V8; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vddio_2 (VDD3V3), + .vssio (VSS), + .vssio_2 (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda1_2 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa1_2 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("peripheralsSPI.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire