| ############################################################################### |
| # Created by write_sdc |
| # Fri Jun 3 13:34:51 2022 |
| ############################################################################### |
| current_design ExperiarCore |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name wb_clk_i -period 25.0000 [get_ports {wb_clk_i}] |
| set_clock_transition 0.1500 [get_clocks {wb_clk_i}] |
| set_clock_uncertainty 0.2500 wb_clk_i |
| set_propagated_clock [get_clocks {wb_clk_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {coreIndex[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {coreIndex[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {coreIndex[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {coreIndex[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {coreIndex[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {coreIndex[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {coreIndex[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {coreIndex[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_ack_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[24]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[25]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[26]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[27]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[28]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[29]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[30]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[31]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_i[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_error_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_stall_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[24]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[25]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[26]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[27]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[28]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[29]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[30]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[31]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[32]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[33]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[34]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[35]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[36]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[37]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[38]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[39]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[40]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[41]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[42]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[43]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[44]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[45]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[46]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[47]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[48]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[49]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[50]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[51]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[52]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[53]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[54]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[55]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[56]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[57]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[58]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[59]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[60]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[61]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[62]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[63]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout0[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[24]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[25]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[26]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[27]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[28]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[29]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[30]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[31]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[32]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[33]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[34]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[35]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[36]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[37]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[38]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[39]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[40]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[41]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[42]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[43]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[44]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[45]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[46]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[47]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[48]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[49]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[50]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[51]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[52]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[53]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[54]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[55]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[56]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[57]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[58]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[59]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[60]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[61]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[62]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[63]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {dout1[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {jtag_tck}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {jtag_tdi}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {jtag_tms}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_adr_i[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_cyc_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[24]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[25]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[26]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[27]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[28]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[29]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[30]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[31]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_i[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_sel_i[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_sel_i[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_sel_i[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_sel_i[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_stb_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_we_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {manufacturerID[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {partID[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {versionID[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {versionID[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {versionID[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {versionID[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr0[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr0[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr0[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr0[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr0[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr0[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr0[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr1[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr1[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr1[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr1[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr1[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr1[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr1[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr1[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {addr1[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {clk0}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {clk1}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[10]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[11]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[12]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[13]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[14]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[15]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[16]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[17]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[18]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[19]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[20]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[21]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[22]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[23]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[24]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[25]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[26]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[27]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_adr_o[9]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_cyc_o}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[10]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[11]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[12]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[13]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[14]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[15]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[16]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[17]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[18]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[19]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[20]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[21]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[22]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[23]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[24]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[25]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[26]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[27]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[28]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[29]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[30]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[31]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_data_o[9]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_sel_o[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_sel_o[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_sel_o[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_sel_o[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_stb_o}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {core_wb_we_o}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {csb0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {csb0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {csb1[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {csb1[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[10]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[11]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[12]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[13]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[14]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[15]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[16]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[17]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[18]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[19]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[20]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[21]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[22]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[23]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[24]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[25]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[26]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[27]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[28]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[29]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[30]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[31]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {din0[9]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {jtag_tdo}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_ack_o}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[10]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[11]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[12]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[13]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[14]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[15]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[16]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[17]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[18]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[19]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[20]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[21]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[22]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[23]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[24]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[25]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[26]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[27]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[28]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[29]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[30]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[31]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_data_o[9]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_error_o}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {localMemory_wb_stall_o}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_env[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_env[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_errorCode[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_errorCode[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_isBranch}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_isCompressed}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_isLoad}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_isStore}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_jtagInstruction[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_jtagInstruction[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_jtagInstruction[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_jtagInstruction[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_jtagInstruction[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_opcode[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_opcode[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_opcode[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_opcode[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_opcode[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_opcode[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_opcode[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[10]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[11]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[12]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[13]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[14]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[15]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[16]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[17]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[18]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[19]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[20]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[21]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[22]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[23]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[24]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[25]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[26]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[27]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[28]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[29]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[30]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[31]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_programCounter[9]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_state[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_state[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {probe_takeBranch}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {web0}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wmask0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wmask0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wmask0[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wmask0[3]}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {clk0}] |
| set_load -pin_load 0.0334 [get_ports {clk1}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_cyc_o}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_stb_o}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_we_o}] |
| set_load -pin_load 0.0334 [get_ports {jtag_tdo}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_ack_o}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_error_o}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_stall_o}] |
| set_load -pin_load 0.0334 [get_ports {probe_isBranch}] |
| set_load -pin_load 0.0334 [get_ports {probe_isCompressed}] |
| set_load -pin_load 0.0334 [get_ports {probe_isLoad}] |
| set_load -pin_load 0.0334 [get_ports {probe_isStore}] |
| set_load -pin_load 0.0334 [get_ports {probe_takeBranch}] |
| set_load -pin_load 0.0334 [get_ports {web0}] |
| set_load -pin_load 0.0334 [get_ports {addr0[8]}] |
| set_load -pin_load 0.0334 [get_ports {addr0[7]}] |
| set_load -pin_load 0.0334 [get_ports {addr0[6]}] |
| set_load -pin_load 0.0334 [get_ports {addr0[5]}] |
| set_load -pin_load 0.0334 [get_ports {addr0[4]}] |
| set_load -pin_load 0.0334 [get_ports {addr0[3]}] |
| set_load -pin_load 0.0334 [get_ports {addr0[2]}] |
| set_load -pin_load 0.0334 [get_ports {addr0[1]}] |
| set_load -pin_load 0.0334 [get_ports {addr0[0]}] |
| set_load -pin_load 0.0334 [get_ports {addr1[8]}] |
| set_load -pin_load 0.0334 [get_ports {addr1[7]}] |
| set_load -pin_load 0.0334 [get_ports {addr1[6]}] |
| set_load -pin_load 0.0334 [get_ports {addr1[5]}] |
| set_load -pin_load 0.0334 [get_ports {addr1[4]}] |
| set_load -pin_load 0.0334 [get_ports {addr1[3]}] |
| set_load -pin_load 0.0334 [get_ports {addr1[2]}] |
| set_load -pin_load 0.0334 [get_ports {addr1[1]}] |
| set_load -pin_load 0.0334 [get_ports {addr1[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_adr_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_data_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_sel_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_sel_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_sel_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {core_wb_sel_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {csb0[1]}] |
| set_load -pin_load 0.0334 [get_ports {csb0[0]}] |
| set_load -pin_load 0.0334 [get_ports {csb1[1]}] |
| set_load -pin_load 0.0334 [get_ports {csb1[0]}] |
| set_load -pin_load 0.0334 [get_ports {din0[31]}] |
| set_load -pin_load 0.0334 [get_ports {din0[30]}] |
| set_load -pin_load 0.0334 [get_ports {din0[29]}] |
| set_load -pin_load 0.0334 [get_ports {din0[28]}] |
| set_load -pin_load 0.0334 [get_ports {din0[27]}] |
| set_load -pin_load 0.0334 [get_ports {din0[26]}] |
| set_load -pin_load 0.0334 [get_ports {din0[25]}] |
| set_load -pin_load 0.0334 [get_ports {din0[24]}] |
| set_load -pin_load 0.0334 [get_ports {din0[23]}] |
| set_load -pin_load 0.0334 [get_ports {din0[22]}] |
| set_load -pin_load 0.0334 [get_ports {din0[21]}] |
| set_load -pin_load 0.0334 [get_ports {din0[20]}] |
| set_load -pin_load 0.0334 [get_ports {din0[19]}] |
| set_load -pin_load 0.0334 [get_ports {din0[18]}] |
| set_load -pin_load 0.0334 [get_ports {din0[17]}] |
| set_load -pin_load 0.0334 [get_ports {din0[16]}] |
| set_load -pin_load 0.0334 [get_ports {din0[15]}] |
| set_load -pin_load 0.0334 [get_ports {din0[14]}] |
| set_load -pin_load 0.0334 [get_ports {din0[13]}] |
| set_load -pin_load 0.0334 [get_ports {din0[12]}] |
| set_load -pin_load 0.0334 [get_ports {din0[11]}] |
| set_load -pin_load 0.0334 [get_ports {din0[10]}] |
| set_load -pin_load 0.0334 [get_ports {din0[9]}] |
| set_load -pin_load 0.0334 [get_ports {din0[8]}] |
| set_load -pin_load 0.0334 [get_ports {din0[7]}] |
| set_load -pin_load 0.0334 [get_ports {din0[6]}] |
| set_load -pin_load 0.0334 [get_ports {din0[5]}] |
| set_load -pin_load 0.0334 [get_ports {din0[4]}] |
| set_load -pin_load 0.0334 [get_ports {din0[3]}] |
| set_load -pin_load 0.0334 [get_ports {din0[2]}] |
| set_load -pin_load 0.0334 [get_ports {din0[1]}] |
| set_load -pin_load 0.0334 [get_ports {din0[0]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {localMemory_wb_data_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {probe_env[1]}] |
| set_load -pin_load 0.0334 [get_ports {probe_env[0]}] |
| set_load -pin_load 0.0334 [get_ports {probe_errorCode[1]}] |
| set_load -pin_load 0.0334 [get_ports {probe_errorCode[0]}] |
| set_load -pin_load 0.0334 [get_ports {probe_jtagInstruction[4]}] |
| set_load -pin_load 0.0334 [get_ports {probe_jtagInstruction[3]}] |
| set_load -pin_load 0.0334 [get_ports {probe_jtagInstruction[2]}] |
| set_load -pin_load 0.0334 [get_ports {probe_jtagInstruction[1]}] |
| set_load -pin_load 0.0334 [get_ports {probe_jtagInstruction[0]}] |
| set_load -pin_load 0.0334 [get_ports {probe_opcode[6]}] |
| set_load -pin_load 0.0334 [get_ports {probe_opcode[5]}] |
| set_load -pin_load 0.0334 [get_ports {probe_opcode[4]}] |
| set_load -pin_load 0.0334 [get_ports {probe_opcode[3]}] |
| set_load -pin_load 0.0334 [get_ports {probe_opcode[2]}] |
| set_load -pin_load 0.0334 [get_ports {probe_opcode[1]}] |
| set_load -pin_load 0.0334 [get_ports {probe_opcode[0]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[31]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[30]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[29]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[28]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[27]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[26]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[25]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[24]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[23]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[22]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[21]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[20]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[19]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[18]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[17]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[16]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[15]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[14]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[13]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[12]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[11]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[10]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[9]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[8]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[7]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[6]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[5]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[4]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[3]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[2]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[1]}] |
| set_load -pin_load 0.0334 [get_ports {probe_programCounter[0]}] |
| set_load -pin_load 0.0334 [get_ports {probe_state[1]}] |
| set_load -pin_load 0.0334 [get_ports {probe_state[0]}] |
| set_load -pin_load 0.0334 [get_ports {wmask0[3]}] |
| set_load -pin_load 0.0334 [get_ports {wmask0[2]}] |
| set_load -pin_load 0.0334 [get_ports {wmask0[1]}] |
| set_load -pin_load 0.0334 [get_ports {wmask0[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_ack_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_error_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_stall_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {jtag_tck}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {jtag_tdi}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {jtag_tms}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_cyc_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_stb_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_we_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {coreIndex[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {coreIndex[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {coreIndex[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {coreIndex[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {coreIndex[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {coreIndex[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {coreIndex[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {coreIndex[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_wb_data_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout0[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dout1[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_adr_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_data_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_sel_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_sel_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_sel_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {localMemory_wb_sel_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {manufacturerID[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {partID[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {versionID[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {versionID[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {versionID[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {versionID[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 5.0000 [current_design] |
