Added buffers to data registers.
diff --git a/verilog/rtl/ExperiarCore/CSR/Traps/Traps.v b/verilog/rtl/ExperiarCore/CSR/Traps/Traps.v
index e9f2d57..db277eb 100644
--- a/verilog/rtl/ExperiarCore/CSR/Traps/Traps.v
+++ b/verilog/rtl/ExperiarCore/CSR/Traps/Traps.v
@@ -46,10 +46,16 @@
reg[31:0] mtvalValue;
reg[31:0] mipValue;
+ reg[15:0] userInterruptsBuffered;
+ always @(posedge clk) begin
+ if (rst) userInterruptsBuffered <= 16'b0;
+ else userInterruptsBuffered <= userInterrupts;
+ end
+
wire[11:0] systemInterrupts = { isMachineExternalInterrupt, 1'b0, 1'b0, 1'b0,
isMachineTimerInterrupt, 1'b0, 1'b0, 1'b0,
isMachineSoftwareInterrupt, 1'b0, 1'b0, 1'b0 };
- wire[31:0] pendingInterrupts = { userInterrupts, 4'b0000, systemInterrupts } & mieValue;
+ wire[31:0] pendingInterrupts = { userInterruptsBuffered, 4'b0000, systemInterrupts } & mieValue;
wire misalignedInstructionFetch = (isAddressMisaligned && (coreState == CORE_STATE_FETCH)) || isJumpMissaligned;
@@ -59,7 +65,7 @@
case (1'b1)
isMachineSoftwareInterrupt: trapCause <= 30'd3;
isMachineTimerInterrupt: trapCause <= 30'd7;
- |userInterrupts: trapCause <= 30'd8;
+ |userInterruptsBuffered: trapCause <= 30'd8;
isMachineExternalInterrupt: trapCause <= 30'd11;
default: trapCause <= 30'b0;
endcase
diff --git a/verilog/rtl/ExperiarCore/CoreManagement.v b/verilog/rtl/ExperiarCore/CoreManagement.v
index efcf3c0..2ec8664 100644
--- a/verilog/rtl/ExperiarCore/CoreManagement.v
+++ b/verilog/rtl/ExperiarCore/CoreManagement.v
@@ -88,6 +88,7 @@
// State register
// b00-b03: probe_errorCode
// b04: isRunning
+ reg[4:0] stateBuffered;
wire[31:0] stateOutputData;
wire stateOutputRequest;
wire stateBusBusy_nc;
@@ -109,10 +110,15 @@
.writeData(stateWriteData_nc),
.writeData_en(stateWriteDataEnable_nc),
.writeData_busy(1'b0),
- .readData({ management_run, core_env, core_errorCode }),
+ .readData(stateBuffered),
.readData_en(stateReadDataEnable_nc),
.readData_busy(1'b0));
+ always @(posedge clk) begin
+ if (rst) stateBuffered <= 3'b0;
+ else stateBuffered <= { management_run, core_env, core_errorCode };
+ end
+
// Core
assign management_run = control[0];
assign management_trapEnable = control[1];
diff --git a/verilog/rtl/Flash/QSPIDevice.v b/verilog/rtl/Flash/QSPIDevice.v
index 9de1143..f1e3d7f 100644
--- a/verilog/rtl/Flash/QSPIDevice.v
+++ b/verilog/rtl/Flash/QSPIDevice.v
@@ -120,7 +120,7 @@
// reg[CLOCK_WIDTH-1:0] clockCounter = {CLOCK_WIDTH{1'b0}};
// wire nextClockCounter = clockCounter + 1;
- // wire[CLOCK_WIDTH-1:0] clockScaleHalfMask = {CLOCK_BITS{1'b1}} << clockScale;
+ // wire[CLOCK_WIDTH-1:0] clockScaleHalfMask = {(CLOCK_WIDTH-1){1'b0}, 1'b1} << clockScale;
// wire[CLOCK_WIDTH-1:0] clockScaleMask = { clockScaleMask[CLOCK_WIDTH-2:0], 1'b0 };
// wire spiHalfClock = clockCounter == (clockScaleHalfMask - 1);//|(clockCounter & clockScaleHalfMask);
// wire spiClock = clockCounter == (clockScaleMask - 1);
diff --git a/verilog/rtl/Peripherals/GPIO/GPIODevice.v b/verilog/rtl/Peripherals/GPIO/GPIODevice.v
index 948445e..4567403 100644
--- a/verilog/rtl/Peripherals/GPIO/GPIODevice.v
+++ b/verilog/rtl/Peripherals/GPIO/GPIODevice.v
@@ -23,6 +23,12 @@
output reg gpio_irq
);
+ reg[IO_COUNT-1:0] inputBuffered;
+ always @(posedge clk) begin
+ if (rst) inputBuffered <= {IO_COUNT{1'b0}};
+ else inputBuffered <= gpio_input;
+ end
+
// Device select
wire[11:0] localAddress;
wire deviceEnable;
@@ -87,7 +93,7 @@
.writeData(inputRegisterWriteData_nc),
.writeData_en(inputRegisterWriteDataEnable_nc),
.writeData_busy(1'b0),
- .readData(gpio_input),
+ .readData(inputBuffered),
.readData_en(inputRegisterReadDataEnable_nc),
.readData_busy(1'b0));
@@ -117,7 +123,7 @@
assign peripheralBus_busy = 1'b0;
- wire[IO_COUNT-1:0] pinIRQ = irqEnable & gpio_oe & gpio_input;
+ wire[IO_COUNT-1:0] pinIRQ = irqEnable & gpio_oe & inputBuffered;
always @(posedge clk) begin
if (rst) gpio_irq <= 1'b0;
diff --git a/verilog/rtl/Peripherals/PWM/PWMDevice.v b/verilog/rtl/Peripherals/PWM/PWMDevice.v
index d20a219..1facc9e 100644
--- a/verilog/rtl/Peripherals/PWM/PWMDevice.v
+++ b/verilog/rtl/Peripherals/PWM/PWMDevice.v
@@ -123,6 +123,7 @@
// Current data register (for .WIDTH(16), .OUTPUTS(4))
// b00-b15: counterValue
// b16-b19: output
+ reg[WIDTH+OUTPUTS-1:0] dataRegisterBuffered;
wire[OUTPUTS-1:0] outputs;
wire[31:0] dataRegisterOutputData;
wire dataRegisterOutputRequest;
@@ -145,11 +146,16 @@
.writeData(dataRegisterWriteData_nc),
.writeData_en(dataRegisterWriteDataEnable_nc),
.writeData_busy(1'b0),
- .readData({ outputs, counterValue }),
+ .readData(dataRegisterBuffered),
.readData_en(dataRegisterReadDataEnable_nc),
.readData_busy(1'b0));
always @(posedge clk) begin
+ if (rst) dataRegisterBuffered <= {(WIDTH + OUTPUTS){1'b0}};
+ else dataRegisterBuffered <= { outputs, counterValue };
+ end
+
+ always @(posedge clk) begin
if (rst) begin
baseCounter <= 'b0;
topCompare <= DEFAULT_TOP_COMPARE_VALUE;
diff --git a/verilog/rtl/Peripherals/UART/UARTDevice.v b/verilog/rtl/Peripherals/UART/UARTDevice.v
index 07cf361..3503765 100644
--- a/verilog/rtl/Peripherals/UART/UARTDevice.v
+++ b/verilog/rtl/Peripherals/UART/UARTDevice.v
@@ -131,6 +131,7 @@
// b03: txDataAvailable
// b04: txBufferFull
// b05: txDataLost
+ reg[5:0] statusRegisterBuffered;
wire[31:0] statusRegisterOutputData;
wire statusRegisterOutputRequest;
wire statusRegisterBusBusy_nc;
@@ -152,17 +153,26 @@
.writeData(statusRegisterWriteData_nc),
.writeData_en(statusRegisterWriteDataEnable_nc),
.writeData_busy(1'b0),
- .readData({
- txDataLostBuffered,
- txBufferFullBuffered,
- txDataAvailableBuffered,
- rxDataLostBuffered,
- rxBufferFullBuffered,
- rxDataAvailableBuffered }),
+ .readData(statusRegisterBuffered),
.readData_en(statusRegisterReadDataEnable_nc),
.readData_busy(1'b0));
+ always @(posedge clk) begin
+ if (rst) statusRegisterBuffered <= 6'b0;
+ else begin
+ statusRegisterBuffered <= {
+ txDataLostBuffered,
+ txBufferFullBuffered,
+ txDataAvailableBuffered,
+ rxDataLostBuffered,
+ rxBufferFullBuffered,
+ rxDataAvailableBuffered
+ };
+ end
+ end
+
// Rx register
+ reg[8:0] rxRegisterBuffered;
wire[31:0] rxRegisterOutputData;
wire rxRegisterOutputRequest;
wire[7:0] rxReadData;
@@ -185,10 +195,15 @@
.writeData(rxRegisterWriteData_nc),
.writeData_en(rxRegisterWriteDataEnable_nc),
.writeData_busy(1'b0),
- .readData(rxDataAvailable ? { 1'b1, rxReadData } : 9'h0),
+ .readData(rxRegisterBuffered),
.readData_en(rxReadDataEnable),
.readData_busy(1'b0));
+ always @(posedge clk) begin
+ if (rst) rxRegisterBuffered <= 9'b0;
+ else rxRegisterBuffered <= rxDataAvailable ? { 1'b1, rxReadData } : 9'h0;
+ end
+
// Tx register
wire[31:0] txRegisterOutputData;
wire txRegisterOutputRequest;
diff --git a/verilog/rtl/Video/VGA_top.v b/verilog/rtl/Video/VGA_top.v
index 0dd3a62..9190e8b 100644
--- a/verilog/rtl/Video/VGA_top.v
+++ b/verilog/rtl/Video/VGA_top.v
@@ -222,6 +222,7 @@
.currentValue(verticalWholeLineCompare));
// VGA state register
+ reg[4:0] stateRegisterBuffered;
reg inVerticalVisibleArea = 1'b1;
reg inHorizontalVisibleArea = 1'b1;
wire[31:0] stateRegisterOutputData;
@@ -245,10 +246,15 @@
.writeData(stateRegisterWriteData_nc),
.writeData_en(stateRegisterWriteDataEnable_nc),
.writeData_busy(1'b0),
- .readData({ inVerticalVisibleArea, inHorizontalVisibleArea, !vga_vsync, !vga_hsync, enableOutput }),
+ .readData(stateRegisterBuffered),
.readData_en(stateReadDataEnable_nc),
.readData_busy(1'b0));
+ always @(posedge clk) begin
+ if (rst) stateRegisterBuffered <= 5'b0;
+ else stateRegisterBuffered <= { inVerticalVisibleArea, inHorizontalVisibleArea, !vga_vsync, !vga_hsync, enableOutput };
+ end
+
assign peripheralBus_busy = 1'b0;
assign requestOutput = configurationRegisterOutputRequest
|| horizontalVisibleAreaCompareRegisterOutputRequest
