| 0x0xxx_xxxx: Per core local memory |
| 0x0000_0000-0x007F_FFFF: SRAM |
| 0x1xxx_xxxx: Wishbone bus |
| 0x10xx_xxxx: Slave 0 (Core 0 local memory) |
| 0x1000_0000-0x107F_FFFF: SRAM |
| 0x1080_xxxx: Management |
| 0x1080_xxxx: Control |
| 0x1080_0000: Management control |
| 0x1080_0004: Core state |
| 0x1081_xxxx: Core registers |
| 0x1081_0000: PC |
| 0x1081_0004: Relative Jump |
| 0x1081_0008: Step |
| 0x1081_0010: Current Instruction |
| 0x1081_0020: Clear error |
| 0x1081_1000-0x1081_101F: Register |
| 0x1081_2000-0x1081_2FFF: CSRs |
| 0x11xx_xxxx: Slave 1 (Core 1 local memory) |
| 0x1100_0000-0x117F_FFFF: SRAM |
| 0x1180_xxxx: Management |
| 0x1180_xxxx: Control |
| 0x1180_0000: Management control |
| 0x1180_0004: Core state |
| 0x1181_xxxx: Core registers |
| 0x1181_0000: PC |
| 0x1181_0004: Relative Jump |
| 0x1181_0008: Step |
| 0x1181_0010: Current Instruction |
| 0x1181_0020: Clear error |
| 0x1181_1000-0x1181_101F: Register |
| 0x1181_2000-0x1181_2FFF: CSRs |
| 0x12xx_xxxx: Slave 2 (Video SRAM) |
| 0x1200_0000-0x127F_FFFF |
| 0x1280_0xxx: VGA Configuration |
| 0x1280_0000: Configuration register |
| 0x1280_0010: Horizontal visible area compare |
| 0x1280_0014: Horizontal front porch compare |
| 0x1280_0018: Horizontal sync pulse compare |
| 0x1280_001C: Horizontal whole line compare |
| 0x1280_0020: Vertical visible area compare |
| 0x1280_0024: Vertical front porch compare |
| 0x1280_0028: Vertical sync pulse compare |
| 0x1280_002C: Vertical whole line compare |
| 0x1280_0030: VGA screen state |
| 0x13xx_xxxx: Slave 3 (Peripherals) |
| 0x1300_xxxx: Peripheral 0 (UART) |
| 0x1300_0xxx: Peripheral configuration |
| 0x1300_0000: Peripheral configuration register (Might not exist) |
| 0x1300_1xxx: Device 0 (Internal to caravel) |
| 0x1300_1000: Configuration register |
| 0x1300_1004: Clear register |
| 0x1300_1008: Status register |
| 0x1300_1010: Rx register |
| 0x1300_1014: Tx register |
| 0x1300_2xxx: Device 1 |
| 0x1300_2000: Configuration register |
| 0x1300_2004: Clear register |
| 0x1300_2008: Status register |
| 0x1300_2010: Rx register |
| 0x1300_2014: Tx register |
| 0x1300_3xxx: Device 2 |
| 0x1300_3000: Configuration register |
| 0x1300_3004: Clear register |
| 0x1300_3008: Status register |
| 0x1300_3010: Rx register |
| 0x1300_3014: Tx register |
| 0x1300_4xxx: Device 3 |
| 0x1300_4000: Configuration register |
| 0x1300_4004: Clear register |
| 0x1300_4008: Status register |
| 0x1300_4010: Rx register |
| 0x1300_4014: Tx register |
| 0x1301_xxxx: Peripheral 1 (SPI) |
| 0x1301_0xxx: Peripheral configuration |
| 0x1301_0000: Peripheral configuration register (Might not exist) |
| 0x1301_1xxx: Device 0 |
| 0x1301_1000: Configuration register |
| 0x1301_1004: Status register |
| 0x1301_1008: Data |
| 0x1302_xxxx: Peripheral 2 (PWM) |
| 0x1302_0xxx: Peripheral configuration |
| 0x1302_0000: Peripheral configuration register (Might not exist) |
| 0x1302_1xxx: Device 0 |
| 0x1302_1000: Configuration register |
| 0x1302_1004: Counter top |
| 0x1302_1008: Counter value |
| 0x1302_1010: Output 0 compare |
| 0x1302_1014: Output 1 compare |
| 0x1302_1018: Output 2 compare |
| 0x1302_101C: Output 3 compare |
| 0x1302_2xxx: Device 1 |
| 0x1302_2000: Configuration register |
| 0x1302_2004: Counter top |
| 0x1302_2008: Counter value |
| 0x1302_2010: Output 0 compare |
| 0x1302_2014: Output 1 compare |
| 0x1302_2018: Output 2 compare |
| 0x1302_201C: Output 3 compare |
| 0x1302_3xxx: Device 2 |
| 0x1302_3000: Configuration register |
| 0x1302_3004: Counter top |
| 0x1302_3008: Counter value |
| 0x1302_3010: Output 0 compare |
| 0x1302_3014: Output 1 compare |
| 0x1302_3018: Output 2 compare |
| 0x1302_301C: Output 3 compare |
| 0x1302_4xxx: Device 3 |
| 0x1302_4000: Configuration register |
| 0x1302_4004: Counter top |
| 0x1302_4008: Counter value |
| 0x1302_4010: Output 0 compare |
| 0x1302_4014: Output 1 compare |
| 0x1302_4018: Output 2 compare |
| 0x1302_401C: Output 3 compare |
| 0x1303_xxxx: Peripheral 3 (GPIO) |
| 0x1303_0xxx: Peripheral configuration |
| 0x1303_0000: Peripheral configuration register (Might not exist) |
| 0x1303_1xxx: Device 0 (Side 1) |
| 0x1303_100x: OutputEnable |
| 0x1303_1000: Write |
| 0x1303_1004: Set |
| 0x1303_1008: Clear |
| 0x1303_100C: Toggle |
| 0x1303_101x: Output |
| 0x1303_1010: Write |
| 0x1303_1014: Set |
| 0x1303_1018: Clear |
| 0x1303_101C: Toggle |
| 0x1303_1020: Input |
| 0x1303_101x: IRQ |
| 0x1303_1010: Write |
| 0x1303_1014: Set |
| 0x1303_1018: Clear |
| 0x1303_101C: Toggle |
| 0x1303_2xxx: Device 1 (Side 2) |
| 0x1303_200x: OutputEnable |
| 0x1303_2000: Write |
| 0x1303_2004: Set |
| 0x1303_2008: Clear |
| 0x1303_200C: Toggle |
| 0x1303_201x: Output |
| 0x1303_2010: Write |
| 0x1303_2014: Set |
| 0x1303_2018: Clear |
| 0x1303_201C: Toggle |
| 0x1303_2020: Input |
| 0x14xx_xxxx: Slave 4 (Flash) |
| 0x1400_0000-0x1400_0FFF: Flash cache |
| 0x1400_1000: Base address |
| 0x1400_1004: Cached address |
| 0x1Fxx_xxxx: Reserved for caravel interface |
| Caravel accessed everything with 0x3xxx_xxxx, but has its own UART interface at 0x3F00_0000 so would not be able to access 0x1Fxx_xxxx |
| 0x3xxx_xxxx: Reserved for caravel interface |
| 0x30xx_xxxx: SoC wishbone slave 0 (Core 0 SRAM) |
| 0x31xx_xxxx: SoC wishbone slave 1 (Core 1 SRAM) |
| 0x32xx_xxxx: SoC wishbone slave 2 (Block SRAM) |
| 0x33xx_xxxx: SoC wishbone slave 3 (Peripherals) |
| 0x33xx_xxxx: SoC wishbone slave 3 (Flash) |
| 0x3F00_xxxx: Peripheral 0 (UART) |
| 0x3F00_0xxx: Peripheral configuration |
| 0x3000_0000: Peripheral configuration register (Might not exist) |
| 0x3F00_1xxx: Internal Device |
| 0x3F00_1000: Configuration register |
| 0x3F00_1004: Clear register |
| 0x3F00_1008: Status register |
| 0x3F00_1010: Rx register |
| 0x3F00_1014: Tx register |
| |
