Fixed cores not being able to access the wishbone bus.
diff --git a/verilog/dv/coreMemory/coreMemory.c b/verilog/dv/coreMemory/coreMemory.c
index 6ef204c..0b78f60 100644
--- a/verilog/dv/coreMemory/coreMemory.c
+++ b/verilog/dv/coreMemory/coreMemory.c
@@ -163,7 +163,7 @@
wbWrite (GPIO0_OE_WRITE_ADDR, ~0x03000);
wbWrite (CORE0_SRAM + 3, 0x0000a183);
- wbWrite (CORE0_SRAM + 4, 0x00312223);
+ wbWrite (CORE0_SRAM + 4, 0x0030a223);
if (!testMemory (0x30000000, 0x000000b7, 0x12345678)) testPass = false;
nextTest (testPass);
diff --git a/verilog/dv/memory/memory.c b/verilog/dv/memory/memory.c
index c29b951..4b2b6e1 100644
--- a/verilog/dv/memory/memory.c
+++ b/verilog/dv/memory/memory.c
@@ -39,7 +39,6 @@
#define GPIO1_INPUT_ADDR ((uint32_t*)0x33032020)
#define CORE0_SRAM ((uint32_t*)0x30000000)
-#define CORE0_SRAM ((uint32_t*)0x30000000)
#define CORE1_SRAM ((uint32_t*)0x31000000)
#define VGA_SRAM ((uint32_t*)0x32000000)
#define SRAM_BANK_SIZE 0x200
diff --git a/verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v b/verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v
index fc0735d..ecdf0d0 100644
--- a/verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v
+++ b/verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v
@@ -26,8 +26,10 @@
localparam STATE_IDLE = 2'h0;
localparam STATE_WRITE_SINGLE = 2'h1;
localparam STATE_READ_SINGLE = 2'h2;
+ localparam STATE_END = 2'h3;
reg[1:0] state = STATE_IDLE;
+ reg[31:0] readDataBuffered;
reg stb = 1'b0;
@@ -35,9 +37,12 @@
if (wb_rst_i || (wb_error_i && state != STATE_IDLE)) begin
state <= STATE_IDLE;
stb <= 1'b0;
+ readDataBuffered <= ~32'b0;
end else begin
case (state)
STATE_IDLE: begin
+ readDataBuffered <= ~32'b0;
+
if (wbWriteEnable) begin
state <= STATE_WRITE_SINGLE;
stb <= 1'b1;
@@ -51,7 +56,7 @@
stb <= 1'b0;
if (wb_ack_i) begin
- state <= STATE_IDLE;
+ state <= STATE_END;
end
end
@@ -59,9 +64,14 @@
stb <= 1'b0;
if (wb_ack_i) begin
- state <= STATE_IDLE;
+ state <= STATE_END;
+ readDataBuffered <= wb_data_i;
end
end
+
+ STATE_END: begin
+ state <= STATE_IDLE;
+ end
default: begin
state <= STATE_IDLE;
@@ -79,7 +89,7 @@
assign wb_data_o = wbDataWrite;
assign wb_adr_o = wbAddress;
- assign wbDataRead = wb_data_i;
- assign wbBusy = state != STATE_IDLE;
+ assign wbDataRead = readDataBuffered;
+ assign wbBusy = (state != STATE_IDLE || wbWriteEnable || wbReadEnable) && (state != STATE_END);
endmodule
\ No newline at end of file
diff --git a/verilog/rtl/WishboneInterconnect/MasterArbiter.v b/verilog/rtl/WishboneInterconnect/MasterArbiter.v
index 044a605..0edf600 100644
--- a/verilog/rtl/WishboneInterconnect/MasterArbiter.v
+++ b/verilog/rtl/WishboneInterconnect/MasterArbiter.v
@@ -57,6 +57,6 @@
else currentMaster <= nextMaster;
end
- assign masterSelected = currentMaster;
+ assign masterSelected = nextMaster;
endmodule
\ No newline at end of file