| ############################################################################### |
| # Created by write_sdc |
| # Sun May 22 15:03:11 2022 |
| ############################################################################### |
| current_design Video |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name wb_clk_i -period 25.0000 [get_ports {wb_clk_i}] |
| set_clock_transition 0.1500 [get_clocks {wb_clk_i}] |
| set_clock_uncertainty 0.2500 wb_clk_i |
| set_propagated_clock [get_clocks {wb_clk_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[24]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[25]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[26]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[27]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[28]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[29]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[30]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[31]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[32]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[33]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[34]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[35]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[36]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[37]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[38]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[39]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[40]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[41]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[42]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[43]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[44]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[45]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[46]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[47]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[48]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[49]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[50]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[51]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[52]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[53]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[54]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[55]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[56]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[57]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[58]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[59]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[60]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[61]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[62]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[63]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout0[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[24]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[25]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[26]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[27]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[28]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[29]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[30]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[31]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[32]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[33]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[34]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[35]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[36]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[37]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[38]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[39]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[40]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[41]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[42]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[43]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[44]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[45]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[46]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[47]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[48]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[49]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[50]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[51]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[52]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[53]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[54]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[55]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[56]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[57]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[58]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[59]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[60]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[61]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[62]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[63]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_dout1[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[24]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[25]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[26]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[27]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[28]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[29]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[30]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[31]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[32]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[33]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[34]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[35]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[36]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[37]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[38]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[39]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[40]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[41]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[42]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[43]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[44]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[45]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[46]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[47]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[48]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[49]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[50]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[51]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[52]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[53]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[54]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[55]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[56]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[57]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[58]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[59]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[60]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[61]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[62]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[63]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout0[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[24]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[25]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[26]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[27]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[28]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[29]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[30]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[31]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[32]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[33]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[34]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[35]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[36]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[37]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[38]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[39]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[40]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[41]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[42]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[43]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[44]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[45]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[46]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[47]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[48]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[49]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[50]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[51]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[52]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[53]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[54]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[55]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[56]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[57]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[58]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[59]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[60]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[61]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[62]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[63]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_dout1[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[10]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[11]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[12]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[13]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[14]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[15]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[16]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[17]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[18]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[19]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[20]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[21]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[22]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[23]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[24]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[25]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[26]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[27]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[28]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[29]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[30]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[31]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[4]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[5]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[6]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[7]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[8]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_i[9]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}] |
| set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr0[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr0[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr0[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr0[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr0[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr0[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr0[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr1[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr1[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr1[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr1[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr1[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr1[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr1[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr1[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_addr1[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_clk0}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_clk1}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_csb0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_csb0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_csb1[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_csb1[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[10]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[11]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[12]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[13]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[14]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[15]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[16]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[17]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[18]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[19]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[20]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[21]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[22]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[23]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[24]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[25]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[26]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[27]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[28]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[29]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[30]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[31]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_din0[9]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_web0}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_wmask0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_wmask0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_wmask0[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram0_wmask0[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr0[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr0[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr0[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr0[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr0[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr0[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr0[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr1[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr1[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr1[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr1[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr1[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr1[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr1[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr1[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_addr1[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_clk0}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_clk1}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_csb0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_csb0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_csb1[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_csb1[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[10]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[11]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[12]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[13]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[14]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[15]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[16]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[17]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[18]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[19]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[20]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[21]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[22]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[23]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[24]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[25]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[26]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[27]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[28]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[29]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[30]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[31]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_din0[9]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_web0}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_wmask0[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_wmask0[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_wmask0[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram1_wmask0[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_b[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_b[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_g[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_g[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_hsync}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_r[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_r[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {vga_vsync}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[0]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[10]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[11]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[12]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[13]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[14]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[15]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[16]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[17]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[18]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[19]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[1]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[20]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[21]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[22]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[23]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[24]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[25]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[26]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[27]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[28]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[29]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[2]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[30]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[31]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[3]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[4]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[5]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[6]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[7]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[8]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_data_o[9]}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_error_o}] |
| set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stall_o}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {sram0_clk0}] |
| set_load -pin_load 0.0334 [get_ports {sram0_clk1}] |
| set_load -pin_load 0.0334 [get_ports {sram0_web0}] |
| set_load -pin_load 0.0334 [get_ports {sram1_clk0}] |
| set_load -pin_load 0.0334 [get_ports {sram1_clk1}] |
| set_load -pin_load 0.0334 [get_ports {sram1_web0}] |
| set_load -pin_load 0.0334 [get_ports {vga_hsync}] |
| set_load -pin_load 0.0334 [get_ports {vga_vsync}] |
| set_load -pin_load 0.0334 [get_ports {wb_ack_o}] |
| set_load -pin_load 0.0334 [get_ports {wb_error_o}] |
| set_load -pin_load 0.0334 [get_ports {wb_stall_o}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[8]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[7]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[6]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[5]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[4]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr0[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[8]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[7]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[6]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[5]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[4]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_addr1[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_csb0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_csb0[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_csb1[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_csb1[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[31]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[30]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[29]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[28]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[27]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[26]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[25]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[24]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[23]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[22]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[21]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[20]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[19]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[18]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[17]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[16]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[15]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[14]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[13]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[12]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[11]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[10]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[9]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[8]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[7]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[6]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[5]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[4]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_din0[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_wmask0[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_wmask0[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_wmask0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram0_wmask0[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr0[8]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr0[7]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr0[6]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr0[5]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr0[4]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr0[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr0[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr0[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr1[8]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr1[7]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr1[6]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr1[5]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr1[4]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr1[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr1[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr1[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_addr1[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_csb0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_csb0[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_csb1[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_csb1[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[31]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[30]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[29]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[28]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[27]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[26]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[25]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[24]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[23]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[22]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[21]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[20]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[19]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[18]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[17]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[16]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[15]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[14]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[13]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[12]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[11]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[10]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[9]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[8]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[7]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[6]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[5]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[4]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_din0[0]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_wmask0[3]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_wmask0[2]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_wmask0[1]}] |
| set_load -pin_load 0.0334 [get_ports {sram1_wmask0[0]}] |
| set_load -pin_load 0.0334 [get_ports {vga_b[1]}] |
| set_load -pin_load 0.0334 [get_ports {vga_b[0]}] |
| set_load -pin_load 0.0334 [get_ports {vga_g[1]}] |
| set_load -pin_load 0.0334 [get_ports {vga_g[0]}] |
| set_load -pin_load 0.0334 [get_ports {vga_r[1]}] |
| set_load -pin_load 0.0334 [get_ports {vga_r[0]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wb_data_o[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_stb_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout0[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram1_dout1[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_data_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 5.0000 [current_design] |
