Fixed wishbone slaves not providing read data on the correct clock cycle.

verilog/rtl/CaravelHost/WBAddressExtension.v

diff --git a/verilog/rtl/CaravelHost/WBAddressExtension.v b/verilog/rtl/CaravelHost/WBAddressExtension.v
index e31c60a..c5c10e3 100644
--- a/verilog/rtl/CaravelHost/WBAddressExtension.v
+++ b/verilog/rtl/CaravelHost/WBAddressExtension.v
@@ -47,15 +47,18 @@
 	reg[31:0] currentDataIn;
 
 	reg acknowledge = 1'b0;
+	reg[31:0] dataRead_buffered;
 
 	always @(posedge wb_clk_i) begin
 		if (wb_rst_i) begin
 			state <= STATE_IDLE;
 			acknowledge <= 1'b0;
+			dataRead_buffered <= 32'b0;
 		end else begin
 			case (state)
 				STATE_IDLE: begin
 					acknowledge <= 1'b0;
+					dataRead_buffered <= 32'b0;
 
 					if (wbs_cyc_i && !userSpaceSelect) begin
 						if (wbs_stb_i) begin
@@ -80,6 +83,7 @@
 				STATE_READ_SINGLE: begin
 					state <= STATE_FINISH;
 					acknowledge <= 1'b1;
+					dataRead_buffered <= currentAddress;
 				end
 
 				STATE_FINISH: begin
@@ -97,6 +101,6 @@
 
 	// Connect wishbone return signals
 	assign wbs_ack_o = userSpaceSelect ? userSpace_wb_ack_o : acknowledge;
-	assign wbs_data_o = userSpaceSelect ? userSpace_wb_data_o : currentAddress;
+	assign wbs_data_o = userSpaceSelect ? userSpace_wb_data_o : dataRead_buffered;
 	
 endmodule
\ No newline at end of file

verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v

diff --git a/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v b/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
index 9be0969..f4f6fe1 100644
--- a/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
+++ b/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
@@ -48,21 +48,25 @@
 	wire isStateWriteSingle = state == STATE_WRITE_SINGLE;
 	wire isStateIdle = state == STATE_IDLE;
 
+	wire[31:0] peripheralBus_dataRead;
 	wire peripheralBus_busy;
 
 	reg stall = 1'b0;
 	reg acknowledge = 1'b0;
+	reg[31:0] dataRead_buffered;
 	
 	always @(posedge wb_clk_i) begin
 		if (wb_rst_i) begin
 			state <= STATE_IDLE;
 			stall <= 1'b0;
 			acknowledge <= 1'b0;
+			dataRead_buffered <= 32'b0;
 		end else begin
 			case (state)
 				STATE_IDLE: begin
 					stall <= 1'b0;
 					acknowledge <= 1'b0;
+					dataRead_buffered <= 32'b0;
 
 					if (wb_cyc_i) begin
 						if (wb_stb_i) begin
@@ -91,6 +95,7 @@
 					if (!peripheralBus_busy) begin
 						state <= STATE_FINISH;
 						acknowledge <= 1'b1;
+						dataRead_buffered <= peripheralBus_dataRead;
 					end
 				end
 
@@ -118,9 +123,8 @@
 	wire peripheralBus_oe = isStateReadSingle;
 	wire[19:0] peripheralBus_address = !isStateIdle ? currentAddress : 24'b0;
 	wire[3:0] peripheralBus_byteSelect = !isStateIdle ? currentByteSelect : 4'b0;
-	wire[31:0] peripheralBus_dataWrite = isStateWriteSingle ? wb_data_i : 32'b0;
-	wire[31:0] peripheralBus_dataRead;
-	assign wb_data_o = isStateReadSingle ? peripheralBus_dataRead : 32'b0;
+	wire[31:0] peripheralBus_dataWrite = isStateWriteSingle ? wb_data_i : 32'b0;	
+	assign wb_data_o = dataRead_buffered;
 
 	// Connect local memory and management interface signals
 	wire localMemoryEnable = wb_adr_i[23] == 1'b0;

verilog/rtl/Flash/WBFlashInterface.v

diff --git a/verilog/rtl/Flash/WBFlashInterface.v b/verilog/rtl/Flash/WBFlashInterface.v
index 30c4645..a09ec56 100644
--- a/verilog/rtl/Flash/WBFlashInterface.v
+++ b/verilog/rtl/Flash/WBFlashInterface.v
@@ -33,17 +33,20 @@
 
 	reg stall = 1'b0;
 	reg acknowledge = 1'b0;
+	reg[31:0] dataRead_buffered;
 
 	always @(posedge wb_clk_i) begin
 		if (wb_rst_i) begin
 			state <= STATE_IDLE;
 			stall <= 1'b0;
 			acknowledge <= 1'b0;
+			dataRead_buffered <= 32'b0;
 		end else begin
 			case (state)
 				STATE_IDLE: begin
 					stall <= 1'b0;
 					acknowledge <= 1'b0;
+					dataRead_buffered <= 32'b0;
 
 					if (wb_cyc_i) begin
 						if (wb_stb_i) begin
@@ -71,6 +74,7 @@
 					if (!flashCache_busy) begin
 						state <= STATE_FINISH;
 						acknowledge <= 1'b1;
+						dataRead_buffered <= flashCache_dataRead;
 					end
 				end
 
@@ -99,6 +103,6 @@
 	assign flashCache_address = state != STATE_IDLE ? currentAddress : 24'b0;
 	assign flashCache_byteSelect = state != STATE_IDLE ? currentByteSelect : 4'b0;
 
-	assign wb_data_o = state == STATE_READ_SINGLE ? flashCache_dataRead : 32'b0;
+	assign wb_data_o = dataRead_buffered;
 	
 endmodule
\ No newline at end of file

verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v

diff --git a/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v b/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v
index d0a337d..f8fcd0b 100644
--- a/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v
+++ b/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v
@@ -40,17 +40,20 @@
 
 	reg stall = 1'b0;
 	reg acknowledge = 1'b0;
+	reg[31:0] dataRead_buffered;
 
 	always @(posedge wb_clk_i) begin
 		if (wb_rst_i) begin
 			state <= STATE_IDLE;
 			stall <= 1'b0;
 			acknowledge <= 1'b0;
+			dataRead_buffered <= 32'b0;
 		end else begin
 			case (state)
 				STATE_IDLE: begin
 					stall <= 1'b0;
 					acknowledge <= 1'b0;
+					dataRead_buffered <= 32'b0;
 
 					if (wb_cyc_i) begin
 						if (wb_stb_i) begin
@@ -79,6 +82,7 @@
 					if (!peripheralBus_busy) begin
 						state <= STATE_FINISH;
 						acknowledge <= 1'b1;
+						dataRead_buffered <= peripheralBus_dataRead;
 					end
 				end
 
@@ -108,7 +112,7 @@
 	assign peripheralBus_address = state != STATE_IDLE ? currentAddress : 24'b0;
 	assign peripheralBus_byteSelect = state != STATE_IDLE ? currentByteSelect : 4'b0;
 
-	assign wb_data_o = state == STATE_READ_SINGLE ? peripheralBus_dataRead : 32'b0;
+	assign wb_data_o = dataRead_buffered;
 	assign peripheralBus_dataWrite = state == STATE_WRITE_SINGLE ? wb_data_i : 32'b0;
 
 endmodule
\ No newline at end of file