mpw_precheck/logs/spdx_compliance_report.log

/root/experiar_soc/Makefile
/root/experiar_soc/docs/Makefile
/root/experiar_soc/docs/environment.yml
/root/experiar_soc/docs/Design/.$ExperiarSoC.drawio.bkp
/root/experiar_soc/docs/Design/.$ExperiarSoC.drawio.dtmp
/root/experiar_soc/docs/Design/.$Macros.drawio.bkp
/root/experiar_soc/docs/Design/.$Macros.drawio.dtmp
/root/experiar_soc/docs/Design/.$MemoryMap.drawio.bkp
/root/experiar_soc/docs/Design/ExperiarSoC.drawio
/root/experiar_soc/docs/Design/Macros.drawio
/root/experiar_soc/docs/Design/MemoryMap.drawio
/root/experiar_soc/docs/Images/detailed.guide
/root/experiar_soc/docs/Scripts/CollateErrors.py
/root/experiar_soc/docs/Scripts/GenerateMacroPlacement.py
/root/experiar_soc/docs/Scripts/JSONWrapper.py
/root/experiar_soc/docs/Scripts/ViewRoutingGuide.py
/root/experiar_soc/docs/source/conf.py
/root/experiar_soc/docs/source/index.rst
/root/experiar_soc/docs/source/quickstart.rst
/root/experiar_soc/openlane/CaravelHost/config.tcl
/root/experiar_soc/openlane/ExperiarCore/config.tcl
/root/experiar_soc/openlane/Flash/config.tcl
/root/experiar_soc/openlane/Peripherals_Flat/config.tcl
/root/experiar_soc/openlane/Video/config.tcl
/root/experiar_soc/openlane/WishboneInterconnect/config.tcl
/root/experiar_soc/openlane/user_project_wrapper/config.tcl
/root/experiar_soc/openlane/user_project_wrapper/macros.json
/root/experiar_soc/sdc/CaravelHost.sdc
/root/experiar_soc/sdc/ExperiarCore.sdc
/root/experiar_soc/sdc/Flash.sdc
/root/experiar_soc/sdc/Peripherals.sdc
/root/experiar_soc/sdc/Video.sdc
/root/experiar_soc/sdc/WishboneInterconnect.sdc
/root/experiar_soc/sdc/user_project_wrapper.sdc
/root/experiar_soc/sdf/CaravelHost.sdf
/root/experiar_soc/sdf/ExperiarCore.sdf
/root/experiar_soc/sdf/Flash.sdf
/root/experiar_soc/sdf/Peripherals.sdf
/root/experiar_soc/sdf/Video.sdf
/root/experiar_soc/sdf/WishboneInterconnect.sdf
/root/experiar_soc/sdf/user_project_wrapper.sdf
/root/experiar_soc/spef/CaravelHost.spef
/root/experiar_soc/spef/ExperiarCore.spef
/root/experiar_soc/spef/Flash.spef
/root/experiar_soc/spef/Peripherals.spef
/root/experiar_soc/spef/Video.spef
/root/experiar_soc/spef/WishboneInterconnect.spef
/root/experiar_soc/spef/user_project_wrapper.spef
/root/experiar_soc/verilog/dv/CopyOutput.py
/root/experiar_soc/verilog/dv/Makefile
/root/experiar_soc/verilog/dv/coreArch/Makefile
/root/experiar_soc/verilog/dv/coreArch/coreArch_tb.v
/root/experiar_soc/verilog/dv/coreArch/runArchTest.py
/root/experiar_soc/verilog/dv/coreArch/riscof/config.ini
/root/experiar_soc/verilog/dv/coreArch/riscof/ExperiarSoC/ExperiarSoC_isa.yaml
/root/experiar_soc/verilog/dv/coreArch/riscof/ExperiarSoC/ExperiarSoC_platform.yaml
/root/experiar_soc/verilog/dv/coreArch/riscof/ExperiarSoC/riscof_ExperiarSoC.py
/root/experiar_soc/verilog/dv/coreArch/riscof/ExperiarSoC/env/link.ld
/root/experiar_soc/verilog/dv/coreArch/riscof/ExperiarSoC/env/model_test.h
/root/experiar_soc/verilog/dv/coreArch/riscof/sail_cSim/__init__.py
/root/experiar_soc/verilog/dv/coreArch/riscof/sail_cSim/riscof_sail_cSim.py
/root/experiar_soc/verilog/dv/coreArch/riscof/sail_cSim/env/link.ld
/root/experiar_soc/verilog/dv/coreArch/riscof/sail_cSim/env/model_test.h
/root/experiar_soc/verilog/dv/coreMemory/GenerateTestInstructions.py
/root/experiar_soc/verilog/dv/coreMemory/Makefile
/root/experiar_soc/verilog/dv/coreMemory/coreMemory.c
/root/experiar_soc/verilog/dv/coreMemory/coreMemory_tb.v
/root/experiar_soc/verilog/dv/corePC/Makefile
/root/experiar_soc/verilog/dv/corePC/corePC.c
/root/experiar_soc/verilog/dv/corePC/corePC_tb.v
/root/experiar_soc/verilog/dv/flash/Makefile
/root/experiar_soc/verilog/dv/flash/flash.c
/root/experiar_soc/verilog/dv/flash/flash_tb.v
/root/experiar_soc/verilog/dv/memory/Makefile
/root/experiar_soc/verilog/dv/memory/memory.c
/root/experiar_soc/verilog/dv/memory/memory_tb.v
/root/experiar_soc/verilog/dv/peripheralsGPIO/Makefile
/root/experiar_soc/verilog/dv/peripheralsGPIO/peripheralsGPIO.c
/root/experiar_soc/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v
/root/experiar_soc/verilog/dv/peripheralsPWM/Makefile
/root/experiar_soc/verilog/dv/peripheralsPWM/peripheralsPWM.c
/root/experiar_soc/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v
/root/experiar_soc/verilog/dv/peripheralsSPI/Makefile
/root/experiar_soc/verilog/dv/peripheralsSPI/peripheralsSPI.c
/root/experiar_soc/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v
/root/experiar_soc/verilog/dv/peripheralsUART/Makefile
/root/experiar_soc/verilog/dv/peripheralsUART/peripheralsUART.c
/root/experiar_soc/verilog/dv/peripheralsUART/peripheralsUART_tb.v
/root/experiar_soc/verilog/dv/video/Makefile
/root/experiar_soc/verilog/dv/video/video.c
/root/experiar_soc/verilog/dv/video/video_tb.v
/root/experiar_soc/verilog/includes/includes.gl+sdf.caravel_user_project
/root/experiar_soc/verilog/includes/includes.gl.caravel_user_project
/root/experiar_soc/verilog/includes/includes.rtl.caravel_user_project
/root/experiar_soc/verilog/rtl/uprj_netlists.v
/root/experiar_soc/verilog/rtl/user_project_wrapper.v
/root/experiar_soc/verilog/rtl/Art/Art_top.v
/root/experiar_soc/verilog/rtl/CaravelHost/CaravelHost_top.v
/root/experiar_soc/verilog/rtl/CaravelHost/WBAddressExtension.v
/root/experiar_soc/verilog/rtl/ExperiarCore/CoreManagement.v
/root/experiar_soc/verilog/rtl/ExperiarCore/ExperiarCore_top.v
/root/experiar_soc/verilog/rtl/ExperiarCore/JTAG.v
/root/experiar_soc/verilog/rtl/ExperiarCore/JTAGRegister.v
/root/experiar_soc/verilog/rtl/ExperiarCore/RV32ICore.v
/root/experiar_soc/verilog/rtl/ExperiarCore/CSR/CSR.v
/root/experiar_soc/verilog/rtl/ExperiarCore/CSR/CSR_ConfigurationRegister.v
/root/experiar_soc/verilog/rtl/ExperiarCore/CSR/CSR_DataRegister.v
/root/experiar_soc/verilog/rtl/ExperiarCore/CSR/CSR_ReadRegister.v
/root/experiar_soc/verilog/rtl/ExperiarCore/CSR/CSR_TimerRegister.v
/root/experiar_soc/verilog/rtl/ExperiarCore/CSR/Traps/Traps.v
/root/experiar_soc/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
/root/experiar_soc/verilog/rtl/ExperiarCore/Memory/MemoryController.v
/root/experiar_soc/verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v
/root/experiar_soc/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
/root/experiar_soc/verilog/rtl/ExperiarSoC/ExperiarSoC_top.v
/root/experiar_soc/verilog/rtl/Flash/FlashBuffer.v
/root/experiar_soc/verilog/rtl/Flash/Flash_top.v
/root/experiar_soc/verilog/rtl/Flash/QSPIDevice.v
/root/experiar_soc/verilog/rtl/Peripherals/Peripherals_top.v
/root/experiar_soc/verilog/rtl/Peripherals/GPIO/GPIODevice.v
/root/experiar_soc/verilog/rtl/Peripherals/GPIO/GPIO_top.v
/root/experiar_soc/verilog/rtl/Peripherals/IOMultiplexer/GenerateGPIOAssigns.py
/root/experiar_soc/verilog/rtl/Peripherals/IOMultiplexer/IOMultiplexer_top.v
/root/experiar_soc/verilog/rtl/Peripherals/PWM/PWMDevice.v
/root/experiar_soc/verilog/rtl/Peripherals/PWM/PWMOutput.v
/root/experiar_soc/verilog/rtl/Peripherals/PWM/PWM_top.v
/root/experiar_soc/verilog/rtl/Peripherals/Registers/ConfigurationRegister.v
/root/experiar_soc/verilog/rtl/Peripherals/Registers/DataRegister.v
/root/experiar_soc/verilog/rtl/Peripherals/Registers/DeviceSelect.v
/root/experiar_soc/verilog/rtl/Peripherals/Registers/OutputRegister.v
/root/experiar_soc/verilog/rtl/Peripherals/Registers/PeripheralSelect.v
/root/experiar_soc/verilog/rtl/Peripherals/SPI/SPIDevice.v
/root/experiar_soc/verilog/rtl/Peripherals/SPI/SPI_top.v
/root/experiar_soc/verilog/rtl/Peripherals/UART/UARTDevice.v
/root/experiar_soc/verilog/rtl/Peripherals/UART/UART_rx.v
/root/experiar_soc/verilog/rtl/Peripherals/UART/UART_top.v
/root/experiar_soc/verilog/rtl/Peripherals/UART/UART_tx.v
/root/experiar_soc/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v
/root/experiar_soc/verilog/rtl/Utility/Counter.v
/root/experiar_soc/verilog/rtl/Utility/FIFO.v
/root/experiar_soc/verilog/rtl/Utility/Mux.v
/root/experiar_soc/verilog/rtl/Utility/ShiftRegister.v
/root/experiar_soc/verilog/rtl/Utility/reset_conditioner.v
/root/experiar_soc/verilog/rtl/Utility/Memory/AsyncFIFO.v
/root/experiar_soc/verilog/rtl/Utility/Memory/AsyncRAM.v
/root/experiar_soc/verilog/rtl/Video/VGA_top.v
/root/experiar_soc/verilog/rtl/Video/VideoMemory_top.v
/root/experiar_soc/verilog/rtl/Video/Video_top.v
/root/experiar_soc/verilog/rtl/WishboneInterconnect/MasterArbiter.v
/root/experiar_soc/verilog/rtl/WishboneInterconnect/WishboneInterconnect_top.v
/root/experiar_soc/verilog/rtl/WishboneInterconnect/WishboneMultiMasterSlave.v