sdc/PWM.sdc

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# Created by write_sdc
# Sat Apr 30 00:31:46 2022
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current_design PWM
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# Timing Constraints
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create_clock -name clk -period 10.0000 [get_ports {clk}]
set_clock_transition 0.1500 [get_clocks {clk}]
set_clock_uncertainty 0.2500 clk
set_propagated_clock [get_clocks {clk}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_address[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataIn[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_oe}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_we}]
set_input_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {rst}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_busy}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[16]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[17]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[18]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[19]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[20]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[21]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[22]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[23]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[24]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[25]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[26]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[27]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[28]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[29]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[30]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[31]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {peripheralBus_dataOut[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_en[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {pwm_out[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk}] -add_delay [get_ports {requestOutput}]
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# Environment
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set_load -pin_load 0.0334 [get_ports {peripheralBus_busy}]
set_load -pin_load 0.0334 [get_ports {requestOutput}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[31]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[30]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[29]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[28]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[27]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[26]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[25]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[24]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[23]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[22]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[21]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[20]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[19]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[18]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[17]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[16]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[15]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[14]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[13]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[12]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[11]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[10]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[9]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[8]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[7]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[6]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[5]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[4]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[3]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[2]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[1]}]
set_load -pin_load 0.0334 [get_ports {peripheralBus_dataOut[0]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[15]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[14]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[13]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[12]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[11]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[10]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[9]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[8]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[7]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[6]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[5]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[4]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[3]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[2]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[1]}]
set_load -pin_load 0.0334 [get_ports {pwm_en[0]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[15]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[14]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[13]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[12]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[11]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[10]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[9]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[8]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[7]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[6]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[5]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[4]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[3]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[2]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[1]}]
set_load -pin_load 0.0334 [get_ports {pwm_out[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_oe}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_we}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_address[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {peripheralBus_dataIn[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]