| design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| /home/crab/windows/ASIC/ExperiarSoC/openlane/WishboneInterconnect,WishboneInterconnect,WishboneInterconnect,flow completed,0h4m5s0ms,0h1m14s0ms,-2.0,0.385,-1,3.76,1670.98,-1,0,0,0,0,0,0,0,30,0,0,-1,556900,25922,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,486353600.0,0.0,37.31,59.02,1.81,24.3,-1,1738,5415,486,4163,0,0,0,1692,15,0,9,21,315,0,0,1063,387,430,8,792,5174,0,5966,26.0,38.46153846153846,25,AREA 0,5,50,1,153.6,153.18,0.045,0.3,sky130_fd_sc_hd,4,4 |
