Fixed an additional clock cycle being generated by the flash controller.

verilog/rtl/Flash/QSPIDevice.v

diff --git a/verilog/rtl/Flash/QSPIDevice.v b/verilog/rtl/Flash/QSPIDevice.v
index c59e366..0ab1010 100644
--- a/verilog/rtl/Flash/QSPIDevice.v
+++ b/verilog/rtl/Flash/QSPIDevice.v
@@ -107,11 +107,12 @@
 							qspi_readDataValid <= 1'b1;
 						end	else begin
 							bitCounter <= nextBitCounter;
+							outputClock <= 1'b1;
 						end
+					end else begin
+						outputClock <= 1'b0;
 					end
 
-					outputClock <= !outputClock;
-
 					if (qspi_changeAddress) state <= STATE_IDLE;
 				end