Fixed flash controller using the wrong address when storing data in the sram cache. Also fixed some problems with the flash test.

diff --git a/verilog/dv/.gitignore b/verilog/dv/.gitignore
index 8d265df..866428d 100644
--- a/verilog/dv/.gitignore
+++ b/verilog/dv/.gitignore

@@ -9,4 +9,5 @@
 coreArch/riscof/sail_cSim/__pycache__/
 coreArch/riscof/ExperiarSoC/__pycache__/
 coreArch/DUT-ExperiarSoC.signature
-coreArch/coreArch.disass
\ No newline at end of file
+coreArch/coreArch.disass
+!flash/test.hex
\ No newline at end of file

diff --git a/verilog/dv/flash/flash.c b/verilog/dv/flash/flash.c
index a3fedea..16f67b6 100644
--- a/verilog/dv/flash/flash.c
+++ b/verilog/dv/flash/flash.c

@@ -38,7 +38,7 @@
 #define GPIO1_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303201C)
 #define GPIO1_INPUT_ADDR ((uint32_t*)0x33032020)
 
-#define FLASH_DATA ((uint32_t*)0x3400000)
+#define FLASH_DATA ((uint32_t*)0x34000000)
 #define FLASH_CONFIGURATION ((uint32_t*)0x34001000)
 #define FLASH_BASE_ADDRESS ((uint32_t*)0x34001004)
 #define FLASH_CACHED_ADDRESS ((uint32_t*)0x34001008)
@@ -143,8 +143,8 @@
 	nextTest (testPass);
 
 	// Check that data is marked as cached
-	uint32_t tries = 5;
-	while (tries > 0 && wbRead (FLASH_CACHED_ADDRESS) < 0x20) tries--;
+	uint32_t tries = 2;
+	while (tries > 0 && wbRead (FLASH_CACHED_ADDRESS) != 0x800) tries--;
 	if (tries == 0) testPass = false;
 	nextTest (testPass);
 
@@ -165,12 +165,12 @@
 	// Set the base address
 	// This will probably be the default value
 	wbWrite (FLASH_BASE_ADDRESS, 0xF000);
-	if (wbRead (FLASH_BASE_ADDRESS) != 0x0) testPass = false;
+	if (wbRead (FLASH_BASE_ADDRESS) != 0xF000) testPass = false;
 	nextTest (testPass);
 
 	// Check that data is marked as cached
-	tries = 5;
-	while (tries > 0 && wbRead (FLASH_CACHED_ADDRESS) < 0x20) tries--;
+	tries = 2;
+	while (tries > 0 && wbRead (FLASH_CACHED_ADDRESS) != 0xF800) tries--;
 	if (tries == 0) testPass = false;
 	nextTest (testPass);
 

diff --git a/verilog/dv/flash/flash_tb.v b/verilog/dv/flash/flash_tb.v
index 01cb8e9..491b538 100644
--- a/verilog/dv/flash/flash_tb.v
+++ b/verilog/dv/flash/flash_tb.v

@@ -64,7 +64,7 @@
 `endif
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (300) begin
+		repeat (500) begin
 			repeat (1000) @(posedge clock);
 			//$display("+1000 cycles");
 		end

diff --git a/verilog/dv/flash/test.hex b/verilog/dv/flash/test.hex
new file mode 100644
index 0000000..c64984d
--- /dev/null
+++ b/verilog/dv/flash/test.hex

@@ -0,0 +1,4 @@
+@00000000
+00 01 02 03 54 60 70 A2 A0 B1 C2 D3 E4 F5 06 17
+@0000F000
+81 2C 23 CB F6 DF F0 EF E7 A0 23 FE 88 05 05 13

diff --git a/verilog/rtl/Flash/FlashBuffer.v b/verilog/rtl/Flash/FlashBuffer.v
index 29c2171..088d303 100644
--- a/verilog/rtl/Flash/FlashBuffer.v
+++ b/verilog/rtl/Flash/FlashBuffer.v

@@ -154,7 +154,7 @@
 			cachedCount <= {SRAM_ADDRESS_SIZE{1'b0}};
 			qspi_requestData <= 1'b0;
 		end	else if (baseAddressRegisterWriteDataEnable) begin
-			cachedAddress <= baseAddressRegisterWriteData[23:2];
+			cachedAddress <= { baseAddressRegisterWriteData[23:2], 2'b00 };
 			cachedCount <= {SRAM_ADDRESS_SIZE{1'b0}};
 			qspi_requestData <= 1'b1;
 		end else if (qspi_requestData && qspi_readDataValid) begin

diff --git a/verilog/rtl/Flash/QSPIDevice.v b/verilog/rtl/Flash/QSPIDevice.v
index 0ab1010..494581d 100644
--- a/verilog/rtl/Flash/QSPIDevice.v
+++ b/verilog/rtl/Flash/QSPIDevice.v

@@ -40,6 +40,7 @@
 	wire deviceBusy = state != STATE_IDLE;
 	reg[1:0] resetState = RESET_NONE;
 	wire resetDevice = resetState != RESET_NONE;
+	reg settingAddress = 1'b0;
 
 	reg outputClock = 1'b0;	
 	reg[4:0] bitCounter = 5'b0;
@@ -81,6 +82,7 @@
 			outputClock <= 1'b0;
 			bitCounter <= 5'b0;
 			resetState <= RESET_START;
+			settingAddress <= 1'b0;
 			qspi_readDataValid <= 1'b0;
 		end else begin
 			case (state)
@@ -89,7 +91,10 @@
 					bitCounter <= 5'b0;
 
 					if (qspi_enable) begin
-						if (resetDevice || qspi_changeAddress) state <= STATE_SETUP;
+						if (resetDevice || qspi_changeAddress) begin
+							state <= STATE_SETUP;
+							settingAddress <= qspi_changeAddress;
+						end
 					end
 				end
 
@@ -104,7 +109,7 @@
 					if (!outputClock) begin
 						if ((resetDevice && bitCounter == 5'h07) || (bitCounter == 5'h1F)) begin
 							state <= STATE_END;
-							qspi_readDataValid <= 1'b1;
+							qspi_readDataValid <= !settingAddress;
 						end	else begin
 							bitCounter <= nextBitCounter;
 							outputClock <= 1'b1;
@@ -121,6 +126,7 @@
 					else state <= STATE_IDLE;
 
 					outputClock <= 1'b0;
+					settingAddress <= 1'b0;
 					qspi_readDataValid <= 1'b0;
 					
 					if (resetState == RESET_START) resetState <= RESET_WAKE;
@@ -131,6 +137,7 @@
 					state <= STATE_IDLE;
 					bitCounter <= 5'b0;
 					outputClock <= 1'b0;
+					settingAddress <= 1'b0;
 					qspi_readDataValid <= 1'b0;
 					resetState <= RESET_START;
 				end