Made a number of fixes and changes which now allows the cores to pass the corePC simulation test. This has required the core size to increased
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml index e960b27..4c3190b 100644 --- a/.github/workflows/user_project_ci.yml +++ b/.github/workflows/user_project_ci.yml
@@ -159,7 +159,7 @@ make verify-peripheralsPWM-rtl make verify-memory-rtl make verify-video-rtl - make verify-core-rtl + make verify-corePC-rtl - name: Run DV GL tests run: | @@ -169,4 +169,4 @@ make verify-peripheralsPWM-gl make verify-memory-gl make verify-video-gl - make verify-core-gl + make verify-corePC-gl
diff --git a/README.md b/README.md index e66e106..a7d8dd7 100644 --- a/README.md +++ b/README.md
@@ -42,7 +42,9 @@ ### verify-peripheralsPWM-rtl: Not implemented ### verify-memory-rtl: Not implemented ### verify-video-rtl: Not implemented -### verify-core-rtl: Not implemented +### verify-corePC-rtl: Not implemented +### verify-coreMem-rtl: Not implemented +### verify-coreArch-rtl: Not implemented ## GL ### verify-peripheralsGPIO-gl: Failed @@ -54,7 +56,7 @@ ### verify-core-gl: Not implemented # Need to do -- Investigate why core is not actually being built +- Add gpio registers for set, clear, and toggle which use the write data as a mask - Write remaining tests (and fix everything until they pass) - Fix timing violations @@ -64,6 +66,8 @@ - CSRs - More tests - Tile map rendering +- Change peripheral bus design to have a read ready signal +- Fetch next instruction a clock cycle earlier so instructions only take 2 cycles # Reference work and inspiration - [Zero to ASIC Course](https://www.zerotoasiccourse.com/): Complete course on ASIC design. Also has useful references and terminology definitions.
diff --git a/docs/Design/MemoryMap.txt b/docs/Design/MemoryMap.txt index e637d6b..10f476b 100644 --- a/docs/Design/MemoryMap.txt +++ b/docs/Design/MemoryMap.txt
@@ -11,6 +11,7 @@ 0x1081_0000: PC 0x1081_0004: Relative Jump 0x1081_0008: Step + 0x1081_0010: Current Instruction 0x1081_1000-0x1081_101F: Register 0x1081_2000-0x1081_2FFF: CSRs 0x11xx_xxxx: Slave 1 (Core 1 local memory) @@ -23,6 +24,7 @@ 0x1181_0000: PC 0x1181_0004: Relative Jump 0x1181_0008: Step + 0x1181_0010: Current Instruction 0x1181_1000-0x1181_101F: Register 0x1181_2000-0x1181_2FFF: CSRs 0x12xx_xxxx: Slave 2 (Video SRAM)
diff --git a/docs/Testing/Testing.md b/docs/Testing/Testing.md index 1154da7..08261ff 100644 --- a/docs/Testing/Testing.md +++ b/docs/Testing/Testing.md
@@ -30,6 +30,10 @@ - Read back from each SRAM macro and compare data - Read back as byte and half values and compare data - Read back byte and half with offset and compare data +- Read from unused memory on wishbone and check that the data back is -1 +- Read from unused memory in peripheral bus and check that the data back is -1 +- Read from unused memory in a core and check that the data back is -1 +- Read from unused memory in video config and check that the data back is -1 - Set GPIO high if pass ## Video verify-video-rtl (-gl) @@ -38,7 +42,7 @@ - Check that output is as expected ## Core (these will run for both cores) verify-core-rtl (-gl) -- Program Counter +- Program Counter and management - Write to program counter - Check that the program counter is correct - Write NOP for step (this does require instruction reads to work) @@ -49,36 +53,16 @@ - Free run the program counter - Check that the program counter increases - Set GPIO high if pass -- Registers - - Write to r0, r1, r2 - - Check that r0==0, and r1, and r2 have correct data - - Set GPIO high if pass -- Basic register instructions - - Write basic program to memory - - Set program counter to start - - Step through instructions - - Read back register values - - Set GPIO high if pass - Store/Load instructions - Write basic program to memory - Write to location in local memory, then read back - Set program counter - Step through instructions - Read back register values - - Set GPIO high if pass -- Jump instructions - - Write basic program to memory - - Check conditional and unconditional jumps - - Set program counter - - Step through instructions - - Read back program counter - - Set GPIO high if pass -- Memory access - Run management memory test on user core -- Peripheral access - Run management peripheral test on user core - UART test modified so user core transfers data to management core, which transfers data back -- Video access - Run management video test on user core + - Set GPIO high if pass - riscv-arch-test - Integrate test into makefile \ No newline at end of file
diff --git a/openlane/ExperiarCore/config.tcl b/openlane/ExperiarCore/config.tcl index 314eed0..af416e3 100644 --- a/openlane/ExperiarCore/config.tcl +++ b/openlane/ExperiarCore/config.tcl
@@ -36,7 +36,7 @@ # Modules should be bigger than 200x200 # Also generally best to leave bottom left as 0,0 set ::env(FP_SIZING) "absolute" -set ::env(DIE_AREA) "0 0 400 800" +set ::env(DIE_AREA) "0 0 450 800" # Alternatively use an adaptive size #set ::env(FP_SIZING) "relative" @@ -64,4 +64,6 @@ # Save a .png after each SYNTH_TOP_LEVEL # This doesn't work right now :( -#set ::env(TAKE_LAYOUT_SCROT) 1 \ No newline at end of file +#set ::env(TAKE_LAYOUT_SCROT) 1 + +#set ::env(GLB_RT_ALLOW_CONGESTION) 1 \ No newline at end of file
diff --git a/verilog/dv/corePC/corePC.c b/verilog/dv/corePC/corePC.c index 42fc7f6..1176863 100644 --- a/verilog/dv/corePC/corePC.c +++ b/verilog/dv/corePC/corePC.c
@@ -65,6 +65,7 @@ #define CORE_RUNNING_NOERROR 0x10 #define RV32I_NOP 0x00000013 +#define RV32I_JMP_PREV 0xFFDFF06F void wbWrite (uint32_t* location, uint32_t value) { @@ -142,16 +143,26 @@ // This does assume that instructions can be read // Maybe test current instruction wbWrite (CORE0_SRAM_ADDR, RV32I_NOP); - wbWrite (CORE0_SRAM_ADDR + 4, RV32I_NOP); + wbWrite (CORE0_SRAM_ADDR + 0x40, RV32I_NOP); + wbWrite (CORE0_SRAM_ADDR + 0x41, RV32I_NOP); + wbWrite (CORE0_SRAM_ADDR + 0x42, RV32I_JMP_PREV); wbWrite (CORE1_SRAM_ADDR, RV32I_NOP); - wbWrite (CORE1_SRAM_ADDR + 4, RV32I_NOP); + wbWrite (CORE1_SRAM_ADDR + 0x40, RV32I_NOP); + wbWrite (CORE1_SRAM_ADDR + 0x41, RV32I_NOP); + wbWrite (CORE1_SRAM_ADDR + 0x42, RV32I_JMP_PREV); // Make sure the test data has been written correctly // If it isn't probably run a specific memory test, rather than this one - if (wbRead (CORE0_SRAM_ADDR) != CORE_HALT) testPass = false; - if (wbRead (CORE0_SRAM_ADDR + 4) != CORE_HALT) testPass = false; - if (wbRead (CORE1_SRAM_ADDR) != CORE_HALT) testPass = false; - if (wbRead (CORE1_SRAM_ADDR + 4) != CORE_HALT) testPass = false; + if (wbRead (CORE0_SRAM_ADDR) != RV32I_NOP) testPass = false; + if (wbRead (CORE0_SRAM_ADDR + 0x40) != RV32I_NOP) testPass = false; + if (wbRead (CORE0_SRAM_ADDR + 0x41) != RV32I_NOP) testPass = false; + if (wbRead (CORE0_SRAM_ADDR + 0x42) != RV32I_JMP_PREV) testPass = false; + nextTest (testPass); + + if (wbRead (CORE1_SRAM_ADDR) != RV32I_NOP) testPass = false; + if (wbRead (CORE1_SRAM_ADDR + 0x40) != RV32I_NOP) testPass = false; + if (wbRead (CORE1_SRAM_ADDR + 0x41) != RV32I_NOP) testPass = false; + if (wbRead (CORE1_SRAM_ADDR + 0x42) != RV32I_JMP_PREV) testPass = false; nextTest (testPass); // Test core 0 @@ -188,15 +199,17 @@ if (wbRead (CORE0_STATUS_ADDR) != CORE_RUNNING_NOERROR) testPass = false; nextTest (testPass); - // Check that the PC has increased - if (wbRead (CORE0_REG_PC_ADDR) >= 0x100) testPass = false; - nextTest (testPass); - // Halt the core wbWrite (CORE0_CONFIG_ADDR, CORE_HALT); // Make sure the core halted if (wbRead (CORE0_CONFIG_ADDR) != CORE_HALT) testPass = false; + nextTest (testPass); + + // Check that the PC has increased should be either 0x104 or 0x108 + uint32_t newAddress = wbRead (CORE0_REG_PC_ADDR); + if (newAddress != 0x104 && newAddress != 0x108) testPass = false; + nextTest (testPass); // Test core 1 // Read that the config defaulted to 0 @@ -232,15 +245,16 @@ if (wbRead (CORE1_STATUS_ADDR) != CORE_RUNNING_NOERROR) testPass = false; nextTest (testPass); - // Check that the PC has increased - if (wbRead (CORE1_REG_PC_ADDR) >= 0x100) testPass = false; - nextTest (testPass); - // Halt the core wbWrite (CORE1_CONFIG_ADDR, CORE_HALT); // Make sure the core halted if (wbRead (CORE1_CONFIG_ADDR) != CORE_HALT) testPass = false; + nextTest (testPass); + + // Check that the PC has increased should be either 0x104 or 0x108 + newAddress = wbRead (CORE1_REG_PC_ADDR); + if (newAddress != 0x104 && newAddress != 0x108) testPass = false; // Finish test nextTest (testPass);
diff --git a/verilog/dv/corePC/corePC_tb.v b/verilog/dv/corePC/corePC_tb.v index 546d80d..2c08de1 100644 --- a/verilog/dv/corePC/corePC_tb.v +++ b/verilog/dv/corePC/corePC_tb.v
@@ -46,7 +46,7 @@ $dumpvars(0, corePC_tb); // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (500) begin + repeat (700) begin repeat (1000) @(posedge clock); //$display("+1000 cycles"); end @@ -78,6 +78,7 @@ @(posedge nextTestOutput); @(posedge nextTestOutput); @(posedge nextTestOutput); + @(posedge nextTestOutput); // Wait for management core to output a output test result @(posedge nextTestOutput);
diff --git a/verilog/rtl/CaravelHost/CaravelHost_top.v b/verilog/rtl/CaravelHost/CaravelHost_top.v index 01d8ddc..8588b20 100644 --- a/verilog/rtl/CaravelHost/CaravelHost_top.v +++ b/verilog/rtl/CaravelHost/CaravelHost_top.v
@@ -97,7 +97,7 @@ assign caravel_wb_stb_o = userSpace_wb_stb_i && caravelEnable; assign caravel_wb_we_o = userSpace_wb_we_i && caravelEnable; assign caravel_wb_sel_o = caravelEnable ? userSpace_wb_sel_i : 4'b0000; - assign caravel_wb_data_o = caravelEnable ? userSpace_wb_data_i : 32'b0; + assign caravel_wb_data_o = caravelEnable ? userSpace_wb_data_i : ~32'b0; assign caravel_wb_adr_o = caravelEnable ? userSpace_wb_adr_i[27:0] : 28'b0; assign userSpace_wb_ack_o = hostConfigEnable ? caravelHost_wb_ack_o : caravel_wb_ack_i || caravel_wb_error_i;
diff --git a/verilog/rtl/CaravelHost/WBAddressExtension.v b/verilog/rtl/CaravelHost/WBAddressExtension.v index c5c10e3..c793ae0 100644 --- a/verilog/rtl/CaravelHost/WBAddressExtension.v +++ b/verilog/rtl/CaravelHost/WBAddressExtension.v
@@ -47,18 +47,18 @@ reg[31:0] currentDataIn; reg acknowledge = 1'b0; - reg[31:0] dataRead_buffered; + reg[31:0] dataRead_buffered = ~32'b0; always @(posedge wb_clk_i) begin if (wb_rst_i) begin state <= STATE_IDLE; acknowledge <= 1'b0; - dataRead_buffered <= 32'b0; + dataRead_buffered <= ~32'b0; end else begin case (state) STATE_IDLE: begin acknowledge <= 1'b0; - dataRead_buffered <= 32'b0; + dataRead_buffered <= ~32'b0; if (wbs_cyc_i && !userSpaceSelect) begin if (wbs_stb_i) begin @@ -89,6 +89,7 @@ STATE_FINISH: begin state <= STATE_IDLE; acknowledge <= 1'b0; + dataRead_buffered <= ~32'b0; end default: begin
diff --git a/verilog/rtl/ExperiarCore/CoreManagement.v b/verilog/rtl/ExperiarCore/CoreManagement.v index 621fd87..4130065 100644 --- a/verilog/rtl/ExperiarCore/CoreManagement.v +++ b/verilog/rtl/ExperiarCore/CoreManagement.v
@@ -102,13 +102,13 @@ // Core assign management_run = control; - assign management_writeEnable = peripheralBus_we; + assign management_writeEnable = coreEnable && peripheralBus_we; assign management_byteSelect = peripheralBus_byteSelect; assign management_address = peripheralBus_address[15:0]; assign management_writeData = peripheralBus_dataWrite; assign peripheralBus_dataRead = coreEnable ? management_readData : controlOutputRequest ? controlOutputData : - stateOutputRequest ? stateOutputData : 32'b0; + stateOutputRequest ? stateOutputData : ~32'b0; endmodule \ No newline at end of file
diff --git a/verilog/rtl/ExperiarCore/ExperiarCore_top.v b/verilog/rtl/ExperiarCore/ExperiarCore_top.v index 0feb05f..80c12e1 100644 --- a/verilog/rtl/ExperiarCore/ExperiarCore_top.v +++ b/verilog/rtl/ExperiarCore/ExperiarCore_top.v
@@ -252,6 +252,7 @@ LocalMemoryInterface #(.SRAM_ADDRESS_SIZE(SRAM_ADDRESS_SIZE)) localMemoryInterface ( .clk(wb_clk_i), + .rst(wb_rst_i), .coreAddress(coreLocalMemoryAddress), .coreByteSelect(coreLocalMemoryByteSelect), .coreWriteEnable(coreLocalMemoryWriteEnable),
diff --git a/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v b/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v index 90c3cfe..ca74d52 100644 --- a/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v +++ b/verilog/rtl/ExperiarCore/Memory/LocalMemoryInterface.v
@@ -2,6 +2,7 @@ parameter SRAM_ADDRESS_SIZE = 9 )( input wire clk, + input wire rst, // Core interface input wire[23:0] coreAddress, @@ -45,42 +46,82 @@ output wire[SRAM_ADDRESS_SIZE-1:0] addr1, input wire[63:0] dout1 ); - - assign coreBusy = 1'b0; - // SRAM + // Core enable pins wire coreSRAMEnable = coreAddress[23:SRAM_ADDRESS_SIZE+3] == 'b0 && (coreWriteEnable || coreReadEnable); wire coreSRAMWriteEnable = coreSRAMEnable && coreWriteEnable && !coreReadEnable; + wire coreSRAMReadEnable = coreSRAMEnable && !coreSRAMWriteEnable; + // Wishbone enable pins wire wbSRAMEnable = wbAddress[23:SRAM_ADDRESS_SIZE+3] == 'b0 && (wbWriteEnable || wbReadEnable); wire wbSRAMWriteEnable = wbSRAMEnable && wbWriteEnable && !wbReadEnable; + wire wbSRAMReadEnable = wbSRAMEnable && !wbSRAMWriteEnable; - wire rwPortEnable = coreSRAMEnable || wbSRAMWriteEnable; // Core can perform reads and writes, but only writes are valid from wb - wire rwWriteEnable = coreSRAMWriteEnable || (!coreSRAMEnable && wbSRAMWriteEnable); - wire[SRAM_ADDRESS_SIZE+2:0] rwAddress = coreSRAMEnable ? coreAddress[SRAM_ADDRESS_SIZE+2:2] : - wbSRAMWriteEnable ? wbAddress[SRAM_ADDRESS_SIZE+2:2] : 'b0; - wire rwBankSelect = rwAddress[SRAM_ADDRESS_SIZE+2]; + // Generate SRAM control signals + // Core can always read from read only port + // Core can always write to read/write port + // Wishbone can read/write to read/write port, but only if core is not writing to it + wire[31:0] rwPortReadData; + wire[31:0] rPortReadData; - wire rPortEnable = wbSRAMEnable && !wbSRAMWriteEnable; - wire[SRAM_ADDRESS_SIZE+2:0] rAddress = wbAddress[SRAM_ADDRESS_SIZE+2:2]; - wire rBankSelect = rAddress[SRAM_ADDRESS_SIZE+2]; + // Busy signals + reg coreReadReady = 1'b0; + always @(posedge clk) begin + if (rst) coreReadReady <= 1'b0; + else if (coreSRAMReadEnable) coreReadReady <= 1'b1; + else coreReadReady <= 1'b0; + end + reg wbReadReady = 1'b0; + always @(posedge clk) begin + if (rst) wbReadReady <= 1'b0; + else if (wbSRAMReadEnable) wbReadReady <= 1'b1; + else wbReadReady <= 1'b0; + end + assign coreBusy = coreSRAMReadEnable && !coreReadReady; + assign wbBusy = (wbSRAMEnable && coreSRAMWriteEnable) || (wbSRAMReadEnable && !wbReadReady); + + // Read/Write port + wire rwPortEnable = coreSRAMWriteEnable || wbSRAMWriteEnable || (wbSRAMReadEnable && !wbReadReady); + wire rwWriteEnable = coreSRAMWriteEnable || (!coreSRAMWriteEnable && wbSRAMWriteEnable); + wire[SRAM_ADDRESS_SIZE:0] rwAddress = coreSRAMWriteEnable ? coreAddress[SRAM_ADDRESS_SIZE+2:2] : + wbSRAMEnable ? wbAddress[SRAM_ADDRESS_SIZE+2:2] : 'b0; + wire rwBankSelect = rwAddress[SRAM_ADDRESS_SIZE]; + + assign wbDataRead = { + wbByteSelect[3] && wbReadReady ? rwPortReadData[31:24] : 8'h00, + wbByteSelect[2] && wbReadReady ? rwPortReadData[23:16] : 8'h00, + wbByteSelect[1] && wbReadReady ? rwPortReadData[15:8] : 8'h00, + wbByteSelect[0] && wbReadReady ? rwPortReadData[7:0] : 8'h00 + }; + + // Read port + wire rPortEnable = coreSRAMReadEnable && !coreReadReady; + wire[SRAM_ADDRESS_SIZE:0] rAddress = coreAddress[SRAM_ADDRESS_SIZE+2:2]; + wire rBankSelect = rAddress[SRAM_ADDRESS_SIZE]; + + assign coreDataRead = { + coreByteSelect[3] && coreReadReady ? rPortReadData[31:24] : 8'h00, + coreByteSelect[2] && coreReadReady ? rPortReadData[23:16] : 8'h00, + coreByteSelect[1] && coreReadReady ? rPortReadData[15:8] : 8'h00, + coreByteSelect[0] && coreReadReady ? rPortReadData[7:0] : 8'h00 + }; + + // SRAM connections assign clk0 = clk; assign csb0 = { !(rwPortEnable && rwBankSelect), !(rwPortEnable && !rwBankSelect) }; assign web0 = !rwWriteEnable; - assign wmask0 = coreSRAMEnable ? coreByteSelect : - wbSRAMWriteEnable ? wbByteSelect : 4'b0; - assign addr0 = rwAddress[SRAM_ADDRESS_SIZE+1:2]; + assign wmask0 = coreSRAMWriteEnable ? coreByteSelect : + wbSRAMWriteEnable ? wbByteSelect : 4'b0; + assign addr0 = rwAddress[SRAM_ADDRESS_SIZE-1:0]; assign din0 = coreSRAMWriteEnable ? coreDataWrite : wbSRAMWriteEnable ? wbDataWrite : 32'b0; - assign coreDataRead = rwBankSelect ? dout0[63:32] : dout0[31:0]; + assign rwPortReadData = rwBankSelect ? dout0[63:32] : dout0[31:0]; assign clk1 = clk; assign csb1 = { !(rPortEnable && rBankSelect), !(rPortEnable && !rBankSelect) }; - assign addr1 = rAddress[SRAM_ADDRESS_SIZE+1:2]; - assign wbDataRead = rBankSelect ? dout1[63:32] : dout1[31:0]; - - assign wbBusy = wbSRAMEnable && wbSRAMWriteEnable; + assign addr1 = rAddress[SRAM_ADDRESS_SIZE-1:0]; + assign rPortReadData = rBankSelect ? dout1[63:32] : dout1[31:0]; endmodule \ No newline at end of file
diff --git a/verilog/rtl/ExperiarCore/Memory/MemoryController.v b/verilog/rtl/ExperiarCore/Memory/MemoryController.v index b06714b..12c1e2d 100644 --- a/verilog/rtl/ExperiarCore/Memory/MemoryController.v +++ b/verilog/rtl/ExperiarCore/Memory/MemoryController.v
@@ -47,7 +47,7 @@ assign coreDataRead = enableLocalMemory ? localMemoryDataRead : enableWB ? wbDataRead : - 32'b0; + ~32'b0; assign coreBusy = enableLocalMemory ? localMemoryBusy : enableWB ? wbBusy :
diff --git a/verilog/rtl/ExperiarCore/RV32ICore.v b/verilog/rtl/ExperiarCore/RV32ICore.v index fc9fd7d..397a732 100644 --- a/verilog/rtl/ExperiarCore/RV32ICore.v +++ b/verilog/rtl/ExperiarCore/RV32ICore.v
@@ -36,28 +36,42 @@ output wire probe_isCompressed ); - localparam STATE_FETCH = 1'b0; - localparam STATE_EXECUTE = 1'b1; + localparam STATE_HALT = 2'b00; + localparam STATE_FETCH = 2'b10; + localparam STATE_EXECUTE = 2'b11; // System registers - reg state = STATE_FETCH; + reg[1:0] state = STATE_HALT; reg[3:0] currentError = 4'b0; reg[31:0] programCounter = 32'b0; reg[31:0] currentInstruction = 32'b0; reg[31:0] registers [0:31]; // Management control - localparam MANAGMENT_ADDRESS_PC = 2'b00; + localparam MANAGMENT_ADDRESS_SYSTEM = 2'b00; localparam MANAGMENT_ADDRESS_REGISTERS = 2'b01; localparam MANAGMENT_ADDRESS_CSR = 2'b10; + wire management_selectProgramCounter = (management_address[15:14] == MANAGMENT_ADDRESS_SYSTEM) && (management_address[13:4] == 10'h000); + wire management_selectInstructionRegister = (management_address[15:14] == MANAGMENT_ADDRESS_SYSTEM) && (management_address[13:4] == 10'h001); + wire management_selectRegister = (management_address[15:14] == MANAGMENT_ADDRESS_REGISTERS) && (management_address[13:7] == 7'h00); + //wire management_selectCSR = management_address[15:14] == MANAGMENT_ADDRESS_CSR; + wire management_writeValid = !management_run && management_writeEnable; - wire management_writeProgramCounter = management_writeValid && (management_address[15:14] == MANAGMENT_ADDRESS_PC) && (management_address[13:4] == 10'h000); + wire management_writeProgramCounter = management_writeValid && management_selectProgramCounter; wire management_writeProgramCounter_set = management_writeProgramCounter && (management_address[3:0] == 4'h0); wire management_writeProgramCounter_jump = management_writeProgramCounter && (management_address[3:0] == 4'h4); wire management_writeProgramCounter_step = management_writeProgramCounter && (management_address[3:0] == 4'h8); - wire management_writeRegister = management_writeValid && (management_address[15:14] == MANAGMENT_ADDRESS_REGISTERS) && (management_address[13:7] == 7'h00); - //wire management_writeCSR = management_writeValid && management_address[15:14] == MANAGMENT_ADDRESS_CSR; + wire management_writeRegister = management_writeValid && management_selectRegister; + //wire management_writeCSR = management_writeValid && management_selectCSR; + + wire management_readValid = !management_run && !management_writeEnable; + wire management_readProgramCounter = management_readValid && management_selectProgramCounter; + wire management_readInstructionRegister = management_readValid && management_selectInstructionRegister; + wire management_readRegister = management_readValid && management_selectRegister; + //wire management_readCSR = management_readValid && management_selectCSR; + + wire management_allowInstruction = management_run || management_writeProgramCounter_step; wire[4:0] management_registerIndex = management_address[6:2]; wire[31:0] management_jumpTarget = programCounter + management_writeData; @@ -66,8 +80,10 @@ always @(*) begin case (1'b1) - management_writeProgramCounter_set: management_dataOut <= programCounter; - management_writeProgramCounter_set: management_dataOut <= registers[management_registerIndex]; + management_readProgramCounter: management_dataOut <= programCounter; + management_readInstructionRegister : management_dataOut <= currentInstruction; + management_readRegister: management_dataOut <= registers[management_registerIndex]; + //management_readCSR: management_dataOut <= csr[management_registerIndex]; default: management_dataOut <= 32'b0; endcase end @@ -219,10 +235,9 @@ wire loadStoreByte = funct3[1:0] == 2'b00; wire loadStoreHalf = funct3[1:0] == 3'b01; wire loadStoreWord = funct3 == 3'b010; - wire[3:0] baseByteMask = loadStoreByte ? 4'b0001 : - loadStoreHalf ? 4'b0011 : - loadStoreWord ? 4'b1111 : - 4'b0000; + wire[3:0] baseByteMask = state == STATE_FETCH || loadStoreWord ? 4'b1111 : + loadStoreHalf ? 4'b0011 : + loadStoreByte ? 4'b0001 : 4'b0000; wire[6:0] loadStoreByteMask = {3'b0, baseByteMask} << targetMemoryAddress[1:0]; wire loadStoreByteMaskValid = |(loadStoreByteMask[3:0]); @@ -231,17 +246,30 @@ wire shouldStore = loadStoreByteMaskValid && !addressMissaligned && ((state == STATE_EXECUTE) && isStore); assign memoryAddress = shouldLoad || shouldStore ? { targetMemoryAddress[31:2], 2'b00 } : 32'b0; - wire[31:0] loadData = shouldLoad ? memoryDataRead : 32'b0; - wire[31:0] storeData = shouldStore ? rs2 : 32'b0; - assign memoryByteSelect = shouldStore || shouldLoad ? loadStoreByteMask[3:0] : 4'b0000; - assign memoryDataWrite = shouldStore && !shouldLoad ? storeData : 32'b0; + + wire[31:0] loadData = shouldLoad && !shouldStore ? dataIn : 32'b0; + wire[31:0] storeData = shouldStore && !shouldLoad ? rs2 : 32'b0; + + wire[31:0] dataIn = { + loadStoreByteMask[3] ? memoryDataRead[31:24] : 8'h00, + loadStoreByteMask[2] ? memoryDataRead[23:16] : 8'h00, + loadStoreByteMask[1] ? memoryDataRead[15:8] : 8'h00, + loadStoreByteMask[0] ? memoryDataRead[7:0] : 8'h00 + }; + + assign memoryDataWrite = { + loadStoreByteMask[3] ? storeData[31:24] : 8'h00, + loadStoreByteMask[2] ? storeData[23:16] : 8'h00, + loadStoreByteMask[1] ? storeData[15:8] : 8'h00, + loadStoreByteMask[0] ? storeData[7:0] : 8'h00 + }; assign memoryWriteEnable = shouldStore; assign memoryReadEnable = shouldLoad; - wire memoryReadReady = shouldLoad ? memoryBusy : 1'b0; - wire memoryWriteDone = shouldStore ? memoryBusy : 1'b0; + wire memoryReadReady = shouldLoad ? !memoryBusy : 1'b0; + wire memoryWriteDone = shouldStore ? !memoryBusy : 1'b0; // Register Write wire integerRegisterWriteEn = isLUI || isAUIPC || isJAL || isJALR || isALU || isALUImm || isLoad; @@ -259,7 +287,7 @@ always @(posedge clk) begin if (rst) begin - state <= STATE_FETCH; + state <= STATE_HALT; programCounter <= 32'b0; currentError <= 4'b0; programCounter <= 32'b0; @@ -267,19 +295,22 @@ end else begin if (!(|currentError)) begin case (state) - STATE_FETCH: begin - if (management_run || management_writeProgramCounter_step) begin - if (memoryReadReady) begin - currentInstruction <= memoryDataRead; - state <= STATE_EXECUTE; - end - end else begin + STATE_HALT: begin + if (management_allowInstruction) state <= STATE_FETCH; + else begin if (management_writeProgramCounter_set) programCounter <= { management_writeData[31:1] , 1'b0}; else if (management_writeProgramCounter_jump) programCounter <= { management_jumpTarget[31:1] , 1'b0}; else if (management_writeRegister) registers[management_registerIndex] <= management_writeData; end end + STATE_FETCH: begin + if (memoryReadReady) begin + currentInstruction <= dataIn; + state <= STATE_EXECUTE; + end + end + STATE_EXECUTE: begin if (addressMissaligned || invalidInstruction) begin currentError <= { 1'b0, 1'b0, addressMissaligned, invalidInstruction }; @@ -288,12 +319,14 @@ if (integerRegisterWriteEn && |rdIndex) registers[rdIndex] <= integerRegisterWriteData; programCounter <= { nextProgramCounter[31:1] , 1'b0}; - state <= STATE_FETCH; + + if (management_allowInstruction) state <= STATE_FETCH; + else state <= STATE_HALT; end end end - default: state <= STATE_FETCH; + default: state <= STATE_HALT; endcase end end @@ -301,7 +334,7 @@ // Debug - assign probe_state = { 1'b0, state }; + assign probe_state = state; assign probe_programCounter = programCounter; assign probe_opcode = opcode; assign probe_errorCode = currentError;
diff --git a/verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v b/verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v index f2ebdc1..fc0735d 100644 --- a/verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v +++ b/verilog/rtl/ExperiarCore/Wishbone/Core_WBInterface.v
@@ -75,11 +75,11 @@ assign wb_stb_o = stb; assign wb_we_o = state == STATE_WRITE_SINGLE; - assign wb_sel_o = stb ? wbByteSelect : 4'b0; - assign wb_data_o = stb ? wbDataWrite : 32'b0; - assign wb_adr_o = stb ? wbAddress : 28'b0; + assign wb_sel_o = wbByteSelect; + assign wb_data_o = wbDataWrite; + assign wb_adr_o = wbAddress; - assign wbDataRead = wb_ack_i ? wb_data_i : 32'b0; + assign wbDataRead = wb_data_i; assign wbBusy = state != STATE_IDLE; endmodule \ No newline at end of file
diff --git a/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v b/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v index ef96a12..07e7112 100644 --- a/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v +++ b/verilog/rtl/ExperiarCore/Wishbone/WB_SRAMInterface.v
@@ -60,13 +60,13 @@ state <= STATE_IDLE; stall <= 1'b0; acknowledge <= 1'b0; - dataRead_buffered <= 32'b0; + dataRead_buffered <= ~32'b0; end else begin case (state) STATE_IDLE: begin stall <= 1'b0; acknowledge <= 1'b0; - dataRead_buffered <= 32'b0; + dataRead_buffered <= ~32'b0; if (wb_cyc_i) begin if (wb_stb_i) begin @@ -103,6 +103,7 @@ state <= STATE_IDLE; stall <= 1'b0; acknowledge <= 1'b0; + dataRead_buffered <= ~32'b0; end default: begin @@ -132,7 +133,7 @@ wire managementEnable = wb_adr_i[23:20] == 4'h8; assign peripheralBus_dataRead = localMemoryEnable ? localMemoryDataRead : - managementEnable ? management_readData : 32'b0; + managementEnable ? management_readData : ~32'b0; assign peripheralBus_busy = (localMemoryEnable && localMemoryBusy) || (managementEnable && management_busy); assign localMemoryWriteEnable = localMemoryEnable && peripheralBus_we;
diff --git a/verilog/rtl/ExperiarSoC/ExperiarSoC_top.v b/verilog/rtl/ExperiarSoC/ExperiarSoC_top.v index acfee17..1521abc 100644 --- a/verilog/rtl/ExperiarSoC/ExperiarSoC_top.v +++ b/verilog/rtl/ExperiarSoC/ExperiarSoC_top.v
@@ -419,6 +419,8 @@ .probe_isCompressed(probe_core0_isCompressed), .probe_jtagInstruction(probe_core0_jtagInstruction)); + wire[31:0] core0SRAM0_dout0; + wire[31:0] core0SRAM0_dout1; sky130_sram_2kbyte_1rw1r_32x512_8 core0SRAM0( `ifdef USE_POWER_PINS .vccd1(vccd1), // User area 1 1.8V power @@ -430,12 +432,14 @@ .wmask0(core0SRAM_wmask0), .addr0(core0SRAM_addr0), .din0(core0SRAM_din0), - .dout0(core0SRAM_dout0[31:0]), + .dout0(core0SRAM0_dout0), .clk1(core0SRAM_clk1), .csb1(core0SRAM_csb1[0]), .addr1(core0SRAM_addr1), - .dout1(core0SRAM_dout1[31:0])); + .dout1(core0SRAM0_dout1)); + wire[31:0] core0SRAM1_dout0; + wire[31:0] core0SRAM1_dout1; sky130_sram_2kbyte_1rw1r_32x512_8 core0SRAM1( `ifdef USE_POWER_PINS .vccd1(vccd1), // User area 1 1.8V power @@ -447,11 +451,14 @@ .wmask0(core0SRAM_wmask0), .addr0(core0SRAM_addr0), .din0(core0SRAM_din0), - .dout0(core0SRAM_dout0[63:32]), + .dout0(core0SRAM1_dout0), .clk1(core0SRAM_clk1), .csb1(core0SRAM_csb1[1]), .addr1(core0SRAM_addr1), - .dout1(core0SRAM_dout1[63:32])); + .dout1(core0SRAM1_dout1)); + + assign core0SRAM_dout0 = { core0SRAM1_dout0, core0SRAM0_dout0 }; + assign core0SRAM_dout1 = { core0SRAM1_dout1, core0SRAM0_dout1 }; //-------------------------------------------------// //----------------------CORE1----------------------// @@ -558,6 +565,8 @@ .probe_isCompressed(probe_core1_isCompressed), .probe_jtagInstruction(probe_core1_jtagInstruction)); + wire[31:0] core1SRAM0_dout0; + wire[31:0] core1SRAM0_dout1; sky130_sram_2kbyte_1rw1r_32x512_8 core1SRAM0( `ifdef USE_POWER_PINS .vccd1(vccd1), // User area 1 1.8V power @@ -569,13 +578,15 @@ .wmask0(core1SRAM_wmask0), .addr0(core1SRAM_addr0), .din0(core1SRAM_din0), - .dout0(core1SRAM_dout0[31:0]), + .dout0(core1SRAM0_dout0), .clk1(core1SRAM_clk1), .csb1(core1SRAM_csb1[0]), .addr1(core1SRAM_addr1), - .dout1(core1SRAM_dout1[31:0])); + .dout1(core1SRAM0_dout1)); - sky130_sram_2kbyte_1rw1r_32x512_8 core1SRAM1( + wire[31:0] core1SRAM1_dout0; + wire[31:0] core1SRAM1_dout1; + sky130_sram_2kbyte_1rw1r_32x512_8 core1SRAM1( `ifdef USE_POWER_PINS .vccd1(vccd1), // User area 1 1.8V power .vssd1(vssd1), // User area 1 digital ground @@ -586,11 +597,14 @@ .wmask0(core1SRAM_wmask0), .addr0(core1SRAM_addr0), .din0(core1SRAM_din0), - .dout0(core1SRAM_dout0[63:32]), + .dout0(core1SRAM1_dout0), .clk1(core1SRAM_clk1), .csb1(core1SRAM_csb1[1]), .addr1(core1SRAM_addr1), - .dout1(core1SRAM_dout1[63:32])); + .dout1(core1SRAM1_dout1)); + + assign core1SRAM_dout0 = { core1SRAM1_dout0, core1SRAM0_dout0 }; + assign core1SRAM_dout1 = { core1SRAM1_dout1, core1SRAM0_dout1 }; //-------------------------------------------------// //----------------------Flash----------------------//
diff --git a/verilog/rtl/Flash/FlashBuffer.v b/verilog/rtl/Flash/FlashBuffer.v index 6f29f6c..acaae31 100644 --- a/verilog/rtl/Flash/FlashBuffer.v +++ b/verilog/rtl/Flash/FlashBuffer.v
@@ -37,6 +37,23 @@ assign dataRequest_address = flashCache_address; assign dataRequest_enable = 1'b0; + // Remember that the read data is only valid on the next clock cycle + reg flashCacheReadReady = 1'b0; + always @(posedge clk) begin + if (rst) flashCacheReadReady <= 1'b0; + else if (flashCache_readEnable) flashCacheReadReady <= 1'b1; + else flashCacheReadReady <= 1'b0; + end + + assign flashCache_dataRead = { + flashCache_byteSelect[3] && flashCacheReadReady ? sram_dout1[31:24] : 8'h00, + flashCache_byteSelect[2] && flashCacheReadReady ? sram_dout1[23:16] : 8'h00, + flashCache_byteSelect[1] && flashCacheReadReady ? sram_dout1[15:8] : 8'h00, + flashCache_byteSelect[0] && flashCacheReadReady ? sram_dout1[7:0] : 8'h00 + }; + + assign flashCache_busy = flashCache_readEnable && !flashCacheReadReady; + assign sram_clk0 = clk; assign sram_csb0 = 1'b1; // Active low chip enable assign sram_web0 = 1'b1; // Active low write enable (probably keep as always write) @@ -49,7 +66,5 @@ assign sram_clk1 = clk; assign sram_csb1 = !(validAddress && flashCache_readEnable); assign sram_addr1 = flashCache_address[SRAM_ADDRESS_SIZE+1:2]; - assign flashCache_dataRead = sram_dout1; - assign flashCache_busy = 1'b0; endmodule \ No newline at end of file
diff --git a/verilog/rtl/Flash/WBFlashInterface.v b/verilog/rtl/Flash/WBFlashInterface.v index fb22c24..60ea02d 100644 --- a/verilog/rtl/Flash/WBFlashInterface.v +++ b/verilog/rtl/Flash/WBFlashInterface.v
@@ -40,13 +40,13 @@ state <= STATE_IDLE; stall <= 1'b0; acknowledge <= 1'b0; - dataRead_buffered <= 32'b0; + dataRead_buffered <= ~32'b0; end else begin case (state) STATE_IDLE: begin stall <= 1'b0; acknowledge <= 1'b0; - dataRead_buffered <= 32'b0; + dataRead_buffered <= ~32'b0; if (wb_cyc_i) begin if (wb_stb_i) begin @@ -82,6 +82,7 @@ state <= STATE_IDLE; stall <= 1'b0; acknowledge <= 1'b0; + dataRead_buffered <= ~32'b0; end default: begin
diff --git a/verilog/rtl/Peripherals/GPIO/GPIODevice.v b/verilog/rtl/Peripherals/GPIO/GPIODevice.v index 1e742e9..ea5e53a 100644 --- a/verilog/rtl/Peripherals/GPIO/GPIODevice.v +++ b/verilog/rtl/Peripherals/GPIO/GPIODevice.v
@@ -94,7 +94,7 @@ assign peripheralBus_dataRead = oeRegisterOutputRequest ? oeRegisterOutputData : outputRegisterOutputRequest ? outputRegisterOutputData : inputRegisterOutputRequest ? inputRegisterOutputData : - 32'b0; + ~32'b0; assign peripheralBus_busy = 1'b0; endmodule \ No newline at end of file
diff --git a/verilog/rtl/Peripherals/GPIO/GPIO_top.v b/verilog/rtl/Peripherals/GPIO/GPIO_top.v index 6213c7b..c911402 100644 --- a/verilog/rtl/Peripherals/GPIO/GPIO_top.v +++ b/verilog/rtl/Peripherals/GPIO/GPIO_top.v
@@ -80,7 +80,7 @@ assign requestOutput = device1OutputRequest || device1OutputRequest; assign peripheralBus_dataRead = device0OutputRequest ? device0OutputData : device1OutputRequest ? device1OutputData : - 32'b0; + ~32'b0; assign peripheralBus_busy = 1'b0; assign gpio0_input = gpio_input[`MPRJ_IO_PADS_1-1:0];
diff --git a/verilog/rtl/Peripherals/Registers/OutputRegister.v b/verilog/rtl/Peripherals/Registers/OutputRegister.v new file mode 100644 index 0000000..6c252b9 --- /dev/null +++ b/verilog/rtl/Peripherals/Registers/OutputRegister.v
@@ -0,0 +1,63 @@ +// module OutputRegister #( +// parameter WIDTH = 32, +// parameter ADDRESS = 8'b0, +// parameter DEFAULT = 32'b0 +// )( +// input wire clk, +// input wire rst, + +// // Peripheral Bus +// input wire enable, +// input wire peripheralBus_we, +// input wire peripheralBus_oe, +// input wire[11:0] peripheralBus_address, +// input wire[3:0] peripheralBus_byteSelect, +// output wire[31:0] peripheralBus_dataRead, +// input wire[31:0] peripheralBus_dataWrite, +// output wire requestOutput, + +// output wire[WIDTH-1:0] currentValue +// ); + +// localparam WRITE_ADDRESS = 4'h0; +// localparam SET_ADDRESS = 4'h4; +// localparam CLEAR_ADDRESS = 4'h8; +// localparam TOGGLE_ADDRESS = 4'hC; + +// wire[31:0] dataMask = { +// peripheralBus_byteSelect[3] ? 8'hFF : 8'h00, +// peripheralBus_byteSelect[2] ? 8'hFF : 8'h00, +// peripheralBus_byteSelect[1] ? 8'hFF : 8'h00, +// peripheralBus_byteSelect[0] ? 8'hFF : 8'h00 +// }; + +// reg[WIDTH-1:0] registerValue; +// wire[31:0] maskedWriteData = (peripheralBus_dataWrite & dataMask) | (registerValue & ~dataMask); + +// wire registerSelect = enable && (peripheralBus_address[11:4] == ADDRESS); +// wire we = registerSelect && peripheralBus_we && !peripheralBus_oe; +// wire oe = registerSelect && peripheralBus_oe && !peripheralBus_we; + +// always @(posedge clk) begin +// if (rst) begin +// registerValue <= DEFAULT; +// end else begin +// if (we) registerValue <= maskedWriteData[WIDTH-1:0]; +// end +// end + +// wire[31:0] baseReadData; +// generate +// if (WIDTH == 32) begin +// assign baseReadData = registerValue; +// end else begin +// wire[32-WIDTH-1:0] zeroPadding = 'b0; +// assign baseReadData = { zeroPadding, registerValue }; +// end +// endgenerate + +// assign peripheralBus_dataRead = oe ? baseReadData & dataMask : 32'b0; +// assign requestOutput = oe; +// assign currentValue = registerValue; + +// endmodule \ No newline at end of file
diff --git a/verilog/rtl/Peripherals/SPI/SPIDevice.v b/verilog/rtl/Peripherals/SPI/SPIDevice.v index 8cacb6a..60d078a 100644 --- a/verilog/rtl/Peripherals/SPI/SPIDevice.v +++ b/verilog/rtl/Peripherals/SPI/SPIDevice.v
@@ -218,7 +218,7 @@ assign requestOutput = configurationRegisterOutputRequest || dataRegisterOutputRequest; assign peripheralBus_dataRead = configurationRegisterOutputRequest ? configurationRegisterOutputData : dataRegisterOutputRequest ? dataRegisterOutputData : - 32'b0; + ~32'b0; assign peripheralBus_busy = busy; assign spi_clk = spiClockPolarity ? !(spiClock && busy) : spiClock && busy;
diff --git a/verilog/rtl/Peripherals/UART/UARTDevice.v b/verilog/rtl/Peripherals/UART/UARTDevice.v index e52e86f..68d55c0 100644 --- a/verilog/rtl/Peripherals/UART/UARTDevice.v +++ b/verilog/rtl/Peripherals/UART/UARTDevice.v
@@ -224,7 +224,7 @@ statusRegisterOutputRequest ? statusRegisterOutputData : rxRegisterOutputRequest ? rxRegisterOutputData : txRegisterOutputRequest ? txRegisterOutputData : - 32'b0; + ~32'b0; assign peripheralBus_busy = txBusy;
diff --git a/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v b/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v index 5cd9d14..6440bf4 100644 --- a/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v +++ b/verilog/rtl/Peripherals/WBPeripheralBusInterface/WBPeripheralBusInterface_top.v
@@ -47,13 +47,13 @@ state <= STATE_IDLE; stall <= 1'b0; acknowledge <= 1'b0; - dataRead_buffered <= 32'b0; + dataRead_buffered <= ~32'b0; end else begin case (state) STATE_IDLE: begin stall <= 1'b0; acknowledge <= 1'b0; - dataRead_buffered <= 32'b0; + dataRead_buffered <= ~32'b0; if (wb_cyc_i) begin if (wb_stb_i) begin @@ -90,6 +90,7 @@ state <= STATE_IDLE; stall <= 1'b0; acknowledge <= 1'b0; + dataRead_buffered <= ~32'b0; end default: begin
diff --git a/verilog/rtl/Video/VGA_top.v b/verilog/rtl/Video/VGA_top.v index 41950bd..7de94c4 100644 --- a/verilog/rtl/Video/VGA_top.v +++ b/verilog/rtl/Video/VGA_top.v
@@ -242,7 +242,7 @@ peripheralBus_dataRead <= verticalSyncPulseCompareRegisterOutputData; verticalWholeLineCompareRegisterOutputRequest: peripheralBus_dataRead <= verticalWholeLineCompareRegisterOutputData; - default: peripheralBus_dataRead <= 32'b0; + default: peripheralBus_dataRead <= ~32'b0; endcase end
diff --git a/verilog/rtl/Video/Video_top.v b/verilog/rtl/Video/Video_top.v index 0a7ef48..c1c756f 100644 --- a/verilog/rtl/Video/Video_top.v +++ b/verilog/rtl/Video/Video_top.v
@@ -170,6 +170,6 @@ assign peripheralBus_busy = videoMemoryBusBusy || vgaBusBusy; assign peripheralBus_dataRead = videoMemoryRequestOutput ? videoMemoryDataRead : - vgaRequestOutput ? vgaDataRead : 32'b0; + vgaRequestOutput ? vgaDataRead : ~32'b0; endmodule \ No newline at end of file
diff --git a/verilog/rtl/WishboneInterconnect/WishboneInterconnect_top.v b/verilog/rtl/WishboneInterconnect/WishboneInterconnect_top.v index d9f3617..a46616b 100644 --- a/verilog/rtl/WishboneInterconnect/WishboneInterconnect_top.v +++ b/verilog/rtl/WishboneInterconnect/WishboneInterconnect_top.v
@@ -145,7 +145,7 @@ wire master3_wb_stb_o = 1'b0; wire master3_wb_we_o = 1'b0; wire[3:0] master3_wb_sel_o = 4'b0; - wire[31:0] master3_wb_data_o = 32'b0; + wire[31:0] master3_wb_data_o = ~32'b0; wire[27:0] master3_wb_adr_o = 28'b0; reg master3_wb_ack_i; reg master3_wb_stall_i; @@ -594,7 +594,7 @@ master0_wb_ack_i <= master0_wb_cyc_o; master0_wb_stall_i <= 1'b0; master0_wb_error_i <= 1'b0; - master0_wb_data_i <= 32'b0; + master0_wb_data_i <= ~32'b0; end endcase @@ -642,7 +642,7 @@ master1_wb_ack_i <= master1_wb_cyc_o; master1_wb_stall_i <= 1'b0; master1_wb_error_i <= 1'b0; - master1_wb_data_i <= 32'b0; + master1_wb_data_i <= ~32'b0; end endcase @@ -690,7 +690,7 @@ master2_wb_ack_i <= master2_wb_cyc_o; master2_wb_stall_i <= 1'b0; master2_wb_error_i <= 1'b0; - master2_wb_data_i <= 32'b0; + master2_wb_data_i <= ~32'b0; end endcase @@ -738,7 +738,7 @@ master3_wb_ack_i <= master3_wb_cyc_o; master3_wb_stall_i <= 1'b0; master3_wb_error_i <= 1'b0; - master3_wb_data_i <= 32'b0; + master3_wb_data_i <= ~32'b0; end endcase