Added UART test .
diff --git a/verilog/dv/peripheralsUART/Makefile b/verilog/dv/peripheralsUART/Makefile new file mode 100644 index 0000000..3fd0b56 --- /dev/null +++ b/verilog/dv/peripheralsUART/Makefile
@@ -0,0 +1,32 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + + +include $(MCW_ROOT)/verilog/dv/make/env.makefile +include $(MCW_ROOT)/verilog/dv/make/var.makefile +include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +include $(MCW_ROOT)/verilog/dv/make/sim.makefile + +
diff --git a/verilog/dv/peripheralsUART/peripheralsUART.c b/verilog/dv/peripheralsUART/peripheralsUART.c new file mode 100644 index 0000000..c96a07a --- /dev/null +++ b/verilog/dv/peripheralsUART/peripheralsUART.c
@@ -0,0 +1,191 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include <defs.h> +#include <stub.c> + +/* + IO Test: + - Configures MPRJ lower 8-IO pins as outputs + - Observes counter value through the MPRJ lower 8 IO pins (in the testbench) +*/ + +#define GPIO0_OE_ADDR ((uint32_t*)0x33031000) +#define GPIO0_OUTPUT_ADDR ((uint32_t*)0x33031004) +#define GPIO0_INPUT_ADDR ((uint32_t*)0x33031008) +#define GPIO1_OE_ADDR ((uint32_t*)0x33032000) +#define GPIO1_OUTPUT_ADDR ((uint32_t*)0x33032004) +#define GPIO1_INPUT_ADDR ((uint32_t*)0x33032008) + +#define GPIO0_OE (*GPIO0_OE_ADDR) +#define GPIO0_OUTPUT (*GPIO0_OUTPUT_ADDR) +#define GPIO0_INPUT (*GPIO0_INPUT_ADDR) +#define GPIO1_OE (*GPIO1_OE_ADDR) +#define GPIO1_OUTPUT (*GPIO1_OUTPUT_ADDR) +#define GPIO1_INPUT (*GPIO1_INPUT_ADDR) + +#define CARAVEL_UART_CONFIGURATION_ADDR ((uint32_t*)0x3F001000) +#define CARAVEL_UART_CLEAR_ADDR ((uint32_t*)0x3F001004) +#define CARAVEL_UART_STATUS_ADDR ((uint32_t*)0x3F001008) +#define CARAVEL_UART_RX_ADDR ((uint32_t*)0x3F001010) +#define CARAVEL_UART_TX__ADDR ((uint32_t*)0x3F001014) + +#define SOC_UART0_CONFIGURATION_ADDR ((uint32_t*)0x33001000) +#define SOC_UART0_CLEAR_ADDR ((uint32_t*)0x33001004) +#define SOC_UART0_STATUS_ADDR ((uint32_t*)0x33001008) +#define SOC_UART0_RX_ADDR ((uint32_t*)0x33001010) +#define SOC_UART0_TX__ADDR ((uint32_t*)0x33001014) + +#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000) +#define MPRJ_WB_DATA_LOCATION 0x30008000 + +void wbWrite (uint32_t* location, uint32_t value) +{ + // Write the address + uint32_t locationData = (uint32_t)location; + MPRJ_WB_ADDRESS = locationData & 0xFFFF8000; + + // Write the data + uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION; + *((volatile uint32_t*)writeAddress) = value; +} + +uint32_t wbRead (uint32_t* location) +{ + // Write the address + uint32_t locationData = (uint32_t)location; + MPRJ_WB_ADDRESS = locationData & 0xFFFF8000; + + // Write the data + uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION; + return *((volatile uint32_t*)writeAddress); +} + +void nextTest (bool testPassing) +{ + uint32_t testPassingOutput = testPassing ? 0x1 << 12 : 0; + wbWrite (GPIO0_OUTPUT_ADDR, testPassingOutput | (0x1 << 13)); + wbWrite (GPIO0_OUTPUT_ADDR, testPassingOutput); +} + +void main () +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* Set up the housekeeping SPI to be connected internally so */ + /* that external pin changes don't affect it. */ + + // Connect the housekeeping SPI to the SPI master + // so that the CSB line is not left floating. This allows + // all of the GPIO pins to be used for user functions. + + // https://github.com/efabless/caravel/blob/main/docs/other/gpio.txt + + // Enable the wishbone bus + reg_wb_enable = 1; + + // Enable GPIO + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1) {} + + // Setup test output + bool testPass = true; + wbWrite (GPIO0_OUTPUT_ADDR, 0x1 << 12); + wbWrite (GPIO0_OE_ADDR, ~0x03000); + + // Write caravel device config and clear + uint32_t enabledDeviceConfig = 0x20014; // This effectively has baudrate of ~2MHz + uint32_t disabledDeviceConfig = 0x00014; // This effectively has baudrate of ~2MHz + wbWrite (CARAVEL_UART_CONFIGURATION_ADDR, disabledDeviceConfig); + wbWrite (CARAVEL_UART_CLEAR_ADDR, 0xF); + + // Read that the config was set correctly + if (wbRead (CARAVEL_UART_CONFIGURATION_ADDR) != disabledDeviceConfig) testPass = false; + if (wbRead (CARAVEL_UART_STATUS_ADDR) != 0) testPass = false; + nextTest (testPass); + + // Write peripheral device config and clear + wbWrite (SOC_UART0_CONFIGURATION_ADDR, enabledDeviceConfig); + wbWrite (SOC_UART0_CLEAR_ADDR, 0xF); + + // Read that the config was set correctly + if (wbRead (SOC_UART0_CONFIGURATION_ADDR) != enabledDeviceConfig) testPass = false; + if (wbRead (SOC_UART0_STATUS_ADDR) != 0) testPass = false; + nextTest (testPass); + + // Send data from caravel + uint32_t testData[] = { 0xCD, 0x55, 0xBE, 0xEF }; + + // Write one byte with the device still disabled to make sure it doesn't send + wbWrite (CARAVEL_UART_TX__ADDR, testData[0]); + + // Check that the data is there + if (wbRead (CARAVEL_UART_STATUS_ADDR) != 0) testPass = false; + nextTest (testPass); + + // Check that no data has arrived at the SoC UART device + if (wbRead (SOC_UART0_STATUS_ADDR) != 0) testPass = false; + nextTest (testPass); + + // Now enable the device and send the remaining data + wbWrite (CARAVEL_UART_CONFIGURATION_ADDR, enabledDeviceConfig); + + wbWrite (CARAVEL_UART_TX__ADDR, testData[1]); + wbWrite (CARAVEL_UART_TX__ADDR, testData[2]); + wbWrite (CARAVEL_UART_TX__ADDR, testData[3]); + + // Read back data from peripheral + if (wbRead (SOC_UART0_RX_ADDR) != testData[0]) testPass = false; + if (wbRead (SOC_UART0_RX_ADDR) != testData[1]) testPass = false; + if (wbRead (SOC_UART0_RX_ADDR) != testData[2]) testPass = false; + if (wbRead (SOC_UART0_RX_ADDR) != testData[3]) testPass = false; + nextTest (testPass); + + // Send data from peripheral + wbWrite (SOC_UART0_TX__ADDR, testData[0]); + wbWrite (SOC_UART0_TX__ADDR, testData[1]); + wbWrite (SOC_UART0_TX__ADDR, testData[2]); + wbWrite (SOC_UART0_TX__ADDR, testData[3]); + + // Read back data from caravel + if (wbRead (CARAVEL_UART_RX_ADDR) != testData[0]) testPass = false; + if (wbRead (CARAVEL_UART_RX_ADDR) != testData[1]) testPass = false; + if (wbRead (CARAVEL_UART_RX_ADDR) != testData[2]) testPass = false; + if (wbRead (CARAVEL_UART_RX_ADDR) != testData[3]) testPass = false; + + // Finish test + nextTest (testPass); +}
diff --git a/verilog/dv/peripheralsUART/peripheralsUART_tb.v b/verilog/dv/peripheralsUART/peripheralsUART_tb.v new file mode 100644 index 0000000..0d5d2e9 --- /dev/null +++ b/verilog/dv/peripheralsUART/peripheralsUART_tb.v
@@ -0,0 +1,174 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 1 ps + +module peripheralsUART_tb; + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + + wire succesOutput = mprj_io[12]; + wire nextTestOutput = mprj_io[13]; + + assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("peripheralsUART.vcd"); + $dumpvars(0, peripheralsUART_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (500) begin + repeat (1000) @(posedge clock); + //$display("+1000 cycles"); + end + $display("%c[1;35m",27); + `ifdef GL + $display ("Monitor: Timeout, Peripherals UART Test (GL) Failed"); + `else + $display ("Monitor: Timeout, Peripherals UART Test (RTL) Failed"); + `endif + $display("%c[0m",27); + $finish; + end + + initial begin + // Wait for tests + @(posedge nextTestOutput); + @(posedge nextTestOutput); + @(posedge nextTestOutput); + + // Wait for management core to output a output test result + @(posedge nextTestOutput); + + if (succesOutput) begin + $display("%c[1;92m",27); + `ifdef GL + $display("Monitor: Peripherals UART Test (GL) Passed"); + `else + $display("Monitor: Peripherals UART Test (RTL) Passed"); + `endif + $display("%c[0m",27); + end else begin + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Peripherals UART Test (GL) Failed"); + `else + $display ("Monitor: Peripherals UART Test (RTL) Failed"); + `endif + $display("%c[0m",27); + end + $finish; + end + + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #300000; + CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #100; + power1 <= 1'b1; + #100; + power2 <= 1'b1; + #100; + power3 <= 1'b1; + #100; + power4 <= 1'b1; + end + + always @(mprj_io) begin + #1 $display("Success:0b%b Next test:0b%b", succesOutput, nextTestOutput); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3; + wire VDD1V8; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vddio_2 (VDD3V3), + .vssio (VSS), + .vssio_2 (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda1_2 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa1_2 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("peripheralsUART.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire