Added read back of test memory to core program counter test.

verilog/dv/corePC/corePC.c

diff --git a/verilog/dv/corePC/corePC.c b/verilog/dv/corePC/corePC.c
index 5f78d80..42fc7f6 100644
--- a/verilog/dv/corePC/corePC.c
+++ b/verilog/dv/corePC/corePC.c
@@ -142,7 +142,17 @@
 	// This does assume that instructions can be read
 	// Maybe test current instruction
 	wbWrite (CORE0_SRAM_ADDR, RV32I_NOP);
+	wbWrite (CORE0_SRAM_ADDR + 4, RV32I_NOP);
 	wbWrite (CORE1_SRAM_ADDR, RV32I_NOP);
+	wbWrite (CORE1_SRAM_ADDR + 4, RV32I_NOP);
+
+	// Make sure the test data has been written correctly
+	// If it isn't probably run a specific memory test, rather than this one
+	if (wbRead (CORE0_SRAM_ADDR) != CORE_HALT) testPass = false;
+	if (wbRead (CORE0_SRAM_ADDR + 4) != CORE_HALT) testPass = false;
+	if (wbRead (CORE1_SRAM_ADDR) != CORE_HALT) testPass = false;
+	if (wbRead (CORE1_SRAM_ADDR + 4) != CORE_HALT) testPass = false;
+	nextTest (testPass);
 
 	// Test core 0
 	// Read that the config defaulted to 0

verilog/dv/corePC/corePC_tb.v

diff --git a/verilog/dv/corePC/corePC_tb.v b/verilog/dv/corePC/corePC_tb.v
index a1d6de9..546d80d 100644
--- a/verilog/dv/corePC/corePC_tb.v
+++ b/verilog/dv/corePC/corePC_tb.v
@@ -75,6 +75,9 @@
 		@(posedge nextTestOutput);
 		@(posedge nextTestOutput);
 		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
+		@(posedge nextTestOutput);
 
 		// Wait for management core to output a output test result
 		@(posedge nextTestOutput);