Added additional modules to variable dump after GL simulations. This means that its actually possible to see what's happening on the wishbone bus in the event of a simulation failing.

verilog/dv/corePC/corePC_tb.v

diff --git a/verilog/dv/corePC/corePC_tb.v b/verilog/dv/corePC/corePC_tb.v
index 143f8c5..3fd799b 100644
--- a/verilog/dv/corePC/corePC_tb.v
+++ b/verilog/dv/corePC/corePC_tb.v
@@ -49,6 +49,7 @@
 		$dumpvars(0, corePC_tb);
 `else
 		$dumpvars(1, corePC_tb);
+		$dumpvars(2, user_project_wrapper);
 `endif
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench

verilog/dv/memory/memory_tb.v

diff --git a/verilog/dv/memory/memory_tb.v b/verilog/dv/memory/memory_tb.v
index b20e63c..03619d1 100644
--- a/verilog/dv/memory/memory_tb.v
+++ b/verilog/dv/memory/memory_tb.v
@@ -49,6 +49,7 @@
 		$dumpvars(0, memory_tb);
 `else
 		$dumpvars(1, memory_tb);
+		$dumpvars(2, user_project_wrapper);
 `endif
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench

verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v

diff --git a/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v b/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v
index f3e5224..411a8cf 100644
--- a/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v
+++ b/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v
@@ -82,6 +82,7 @@
 		$dumpvars(0, peripheralsGPIO_tb);
 `else
 		$dumpvars(1, peripheralsGPIO_tb);
+		$dumpvars(2, user_project_wrapper);
 `endif
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench

verilog/dv/peripheralsUART/peripheralsUART_tb.v

diff --git a/verilog/dv/peripheralsUART/peripheralsUART_tb.v b/verilog/dv/peripheralsUART/peripheralsUART_tb.v
index 29b4bc8..cc5eb15 100644
--- a/verilog/dv/peripheralsUART/peripheralsUART_tb.v
+++ b/verilog/dv/peripheralsUART/peripheralsUART_tb.v
@@ -49,6 +49,7 @@
 		$dumpvars(0, peripheralsUART_tb);
 `else
 		$dumpvars(1, peripheralsUART_tb);
+		$dumpvars(2, user_project_wrapper);
 `endif
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench

verilog/dv/video/video_tb.v

diff --git a/verilog/dv/video/video_tb.v b/verilog/dv/video/video_tb.v
index 9266622..ef5fe7c 100644
--- a/verilog/dv/video/video_tb.v
+++ b/verilog/dv/video/video_tb.v
@@ -56,6 +56,7 @@
 		$dumpvars(0, video_tb);
 `else
 		$dumpvars(1, video_tb);
+		$dumpvars(2, user_project_wrapper);
 `endif
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench