verilog/includes/includes.gl.caravel_user_project

# Experiar SoC includes	     
-v $(CARAVEL_ROOT)/verilog/rtl/defines.v 
-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v 
-v $(USER_PROJECT_VERILOG)/gl/CaravelHost.v 
-v $(USER_PROJECT_VERILOG)/gl/ExperiarCore.v 
-v $(USER_PROJECT_VERILOG)/gl/Flash.v 
-v $(USER_PROJECT_VERILOG)/gl/Peripherals.v 
-v $(USER_PROJECT_VERILOG)/gl/Video.v 
-v $(USER_PROJECT_VERILOG)/gl/WishboneInterconnect.v 
-v $(USER_PROJECT_VERILOG)/rtl/Art/Art_top.v 
# Make sure there is a blank line at the end, otherwise things wont work